Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T14
1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T14
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T14
0	1	Covered	T8,T68,T69
1	0	Covered	T8,T154,T247

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T14
0	1	Covered	T1,T12,T14
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T14
1	-	Covered	T1,T12,T14

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T14
DetectSt	168	Covered	T1,T12,T14
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T1,T12,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T14
DebounceSt->IdleSt	163	Covered	T92,T75,T56
DetectSt->IdleSt	186	Covered	T8,T68,T69
DetectSt->StableSt	191	Covered	T1,T12,T14
IdleSt->DebounceSt	148	Covered	T1,T12,T14
StableSt->IdleSt	206	Covered	T1,T12,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T12,T14
0	1	Covered	T1,T12,T14
0	0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T14
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T12,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T75,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T14
DetectSt	-	-	-	-	1	-	-	Covered	T8,T68,T69
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T14
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T14
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T14
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T14
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	2967	0	0
CntIncr_A	8157508	101813	0	0
CntNoWrap_A	8157508	7529317	0	0
DetectStDropOut_A	8157508	413	0	0
DetectedOut_A	8157508	69250	0	0
DetectedPulseOut_A	8157508	804	0	0
DisabledIdleSt_A	8157508	7059578	0	0
DisabledNoDetection_A	8157508	7061657	0	0
EnterDebounceSt_A	8157508	1487	0	0
EnterDetectSt_A	8157508	1480	0	0
EnterStableSt_A	8157508	804	0	0
PulseIsPulse_A	8157508	804	0	0
StayInStableSt	8157508	68355	0	0
gen_high_event_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	713	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	2967	0	0
T1	7769	16	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	60	0	0
T12	15221	50	0	0
T13	2206	0	0	0
T14	9688	24	0	0
T29	0	12	0	0
T42	0	62	0	0
T68	0	24	0	0
T69	0	30	0	0
T70	0	30	0	0
T71	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	101813	0	0
T1	7769	280	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	1691	0	0
T12	15221	1575	0	0
T13	2206	0	0	0
T14	9688	912	0	0
T29	0	444	0	0
T42	0	1922	0	0
T68	0	557	0	0
T69	0	877	0	0
T70	0	1395	0	0
T71	0	1335	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7529317	0	0
T1	7769	7344	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14748	0	0
T13	2206	603	0	0
T14	9688	9263	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	413	0	0
T8	10797	21	0	0
T9	22998	0	0	0
T10	726	0	0	0
T22	502	0	0	0
T23	697	0	0	0
T42	10980	0	0	0
T51	409	0	0	0
T52	426	0	0	0
T53	502	0	0	0
T54	1065	0	0	0
T68	0	12	0	0
T69	0	15	0	0
T75	0	1	0	0
T91	0	6	0	0
T92	0	1	0	0
T94	0	22	0	0
T96	0	14	0	0
T154	0	17	0	0
T244	0	25	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	69250	0	0
T1	7769	1368	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	2228	0	0
T13	2206	0	0	0
T14	9688	459	0	0
T29	0	963	0	0
T42	0	2131	0	0
T70	0	2382	0	0
T71	0	244	0	0
T108	0	181	0	0
T245	0	1045	0	0
T246	0	3285	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	804	0	0
T1	7769	8	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	25	0	0
T13	2206	0	0	0
T14	9688	12	0	0
T29	0	6	0	0
T42	0	31	0	0
T70	0	15	0	0
T71	0	15	0	0
T108	0	11	0	0
T245	0	27	0	0
T246	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7059578	0	0
T1	7769	4028	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17802	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	8228	0	0
T13	2206	603	0	0
T14	9688	3442	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7061657	0	0
T1	7769	4028	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	8228	0	0
T13	2206	606	0	0
T14	9688	3442	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1487	0	0
T1	7769	8	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	30	0	0
T12	15221	25	0	0
T13	2206	0	0	0
T14	9688	12	0	0
T29	0	6	0	0
T42	0	31	0	0
T68	0	12	0	0
T69	0	15	0	0
T70	0	15	0	0
T71	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	1480	0	0
T1	7769	8	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T8	0	30	0	0
T12	15221	25	0	0
T13	2206	0	0	0
T14	9688	12	0	0
T29	0	6	0	0
T42	0	31	0	0
T68	0	12	0	0
T69	0	15	0	0
T70	0	15	0	0
T71	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	804	0	0
T1	7769	8	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	25	0	0
T13	2206	0	0	0
T14	9688	12	0	0
T29	0	6	0	0
T42	0	31	0	0
T70	0	15	0	0
T71	0	15	0	0
T108	0	11	0	0
T245	0	27	0	0
T246	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	804	0	0
T1	7769	8	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	25	0	0
T13	2206	0	0	0
T14	9688	12	0	0
T29	0	6	0	0
T42	0	31	0	0
T70	0	15	0	0
T71	0	15	0	0
T108	0	11	0	0
T245	0	27	0	0
T246	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	68355	0	0
T1	7769	1359	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	2200	0	0
T13	2206	0	0	0
T14	9688	447	0	0
T29	0	954	0	0
T42	0	2099	0	0
T70	0	2367	0	0
T71	0	229	0	0
T108	0	170	0	0
T245	0	1018	0	0
T246	0	3254	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	713	0	0
T1	7769	7	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	0	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	22	0	0
T13	2206	0	0	0
T14	9688	12	0	0
T29	0	3	0	0
T42	0	30	0	0
T70	0	15	0	0
T71	0	15	0	0
T108	0	11	0	0
T245	0	27	0	0
T246	0	29	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T4
1	Covered	T1,T2,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T4
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T6	VC_COV_UNR
1	Covered	T1,T12,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T12,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T4
1	0	Covered	T1,T12,T4
1	1	Covered	T1,T12,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T4
0	1	Covered	T86,T87,T89
1	0	Covered	T75,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T4
0	1	Covered	T1,T4,T44
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T4
1	-	Covered	T1,T4,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T4
DetectSt	168	Covered	T1,T12,T4
IdleSt	163	Covered	T1,T2,T6
StableSt	191	Covered	T1,T12,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T4
DebounceSt->IdleSt	163	Covered	T12,T42,T44
DetectSt->IdleSt	186	Covered	T86,T87,T89
DetectSt->StableSt	191	Covered	T1,T12,T4
IdleSt->DebounceSt	148	Covered	T1,T12,T4
StableSt->IdleSt	206	Covered	T1,T12,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T4
0	1	Covered	T1,T12,T4
0	0	Excluded	T1,T2,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T4
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T42,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T4
DetectSt	-	-	-	-	1	-	-	Covered	T86,T87,T89
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T44
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8157508	744	0	0
CntIncr_A	8157508	42281	0	0
CntNoWrap_A	8157508	7531540	0	0
DetectStDropOut_A	8157508	76	0	0
DetectedOut_A	8157508	11480	0	0
DetectedPulseOut_A	8157508	267	0	0
DisabledIdleSt_A	8157508	7168414	0	0
DisabledNoDetection_A	8157508	7170061	0	0
EnterDebounceSt_A	8157508	397	0	0
EnterDetectSt_A	8157508	348	0	0
EnterStableSt_A	8157508	267	0	0
PulseIsPulse_A	8157508	267	0	0
StayInStableSt	8157508	11178	0	0
gen_high_level_sva.HighLevelEvent_A	8157508	7534546	0	0
gen_not_sticky_sva.StableStDropOut_A	8157508	229	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	744	0	0
T1	7769	2	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	10	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	8	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	7	0	0
T28	0	15	0	0
T29	0	4	0	0
T42	0	3	0	0
T44	0	13	0	0
T86	0	10	0	0
T87	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	42281	0	0
T1	7769	71	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	620	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	152	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	371	0	0
T28	0	1227	0	0
T29	0	146	0	0
T42	0	84	0	0
T44	0	596	0	0
T86	0	1391	0	0
T87	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7531540	0	0
T1	7769	7358	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	17792	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	14790	0	0
T13	2206	603	0	0
T14	9688	9287	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	76	0	0
T32	491	0	0	0
T36	551	0	0	0
T70	11656	0	0	0
T71	8613	0	0	0
T86	22896	5	0	0
T87	19252	1	0	0
T89	0	6	0	0
T95	0	7	0	0
T98	0	1	0	0
T99	0	5	0	0
T104	494	0	0	0
T105	493	0	0	0
T106	460	0	0	0
T107	750	0	0	0
T256	0	4	0	0
T268	0	1	0	0
T269	0	3	0	0
T270	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	11480	0	0
T1	7769	50	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	142	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	178	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	229	0	0
T28	0	614	0	0
T29	0	150	0	0
T30	0	9	0	0
T42	0	54	0	0
T44	0	329	0	0
T88	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	267	0	0
T1	7769	1	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	5	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	3	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	3	0	0
T28	0	7	0	0
T29	0	2	0	0
T30	0	1	0	0
T42	0	1	0	0
T44	0	6	0	0
T88	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7168414	0	0
T1	7769	5993	0	0
T2	1045	644	0	0
T3	500	99	0	0
T4	19047	14222	0	0
T5	826	425	0	0
T6	375494	375093	0	0
T7	592	191	0	0
T12	15221	12573	0	0
T13	2206	603	0	0
T14	9688	8828	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7170061	0	0
T1	7769	5994	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	14223	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	12574	0	0
T13	2206	606	0	0
T14	9688	8829	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	397	0	0
T1	7769	1	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	5	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	5	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	4	0	0
T28	0	8	0	0
T29	0	2	0	0
T42	0	2	0	0
T44	0	7	0	0
T86	0	5	0	0
T87	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	348	0	0
T1	7769	1	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	5	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	3	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	3	0	0
T28	0	7	0	0
T29	0	2	0	0
T42	0	1	0	0
T44	0	6	0	0
T86	0	5	0	0
T87	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	267	0	0
T1	7769	1	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	5	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	3	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	3	0	0
T28	0	7	0	0
T29	0	2	0	0
T30	0	1	0	0
T42	0	1	0	0
T44	0	6	0	0
T88	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	267	0	0
T1	7769	1	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	5	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	3	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	3	0	0
T28	0	7	0	0
T29	0	2	0	0
T30	0	1	0	0
T42	0	1	0	0
T44	0	6	0	0
T88	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	11178	0	0
T1	7769	49	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	137	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	172	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	226	0	0
T28	0	607	0	0
T29	0	148	0	0
T30	0	8	0	0
T42	0	52	0	0
T44	0	323	0	0
T88	0	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	7534546	0	0
T1	7769	7362	0	0
T2	1045	645	0	0
T3	500	100	0	0
T4	19047	17810	0	0
T5	826	426	0	0
T6	375494	375094	0	0
T7	592	192	0	0
T12	15221	14802	0	0
T13	2206	606	0	0
T14	9688	9288	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8157508	229	0	0
T1	7769	1	0	0
T2	1045	0	0	0
T3	500	0	0	0
T4	19047	5	0	0
T5	826	0	0	0
T6	375494	0	0	0
T7	592	0	0	0
T12	15221	0	0	0
T13	2206	0	0	0
T14	9688	0	0	0
T27	0	3	0	0
T28	0	7	0	0
T29	0	2	0	0
T30	0	1	0	0
T34	0	7	0	0
T44	0	6	0	0
T74	0	1	0	0
T88	0	1	0	0