Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1995

1

T3

6

T10

12

T11

8

auto[1]

602

1

T3

2

T10

4

T21

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2001

1

T3

4

T10

16

T11

8

auto[1]

596

1

T3

4

T37

16

T53

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1931

1

T3

6

T10

16

T11

6

auto[1]

666

1

T3

2

T11

2

T37

7

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2007

1

T3

4

T10

16

T11

6

auto[1]

590

1

T3

4

T11

2

T37

27

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2376

1

T3

4

T10

16

T11

8

auto[1]

221

1

T3

4

T37

16

T53

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2431

1

T3

8

T10

14

T11

6

auto[1]

166

1

T10

2

T11

2

T37

11

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2397

1

T3

6

T10

12

T11

8

auto[1]

200

1

T3

2

T10

4

T32

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2392

1

T3

6

T10

14

T11

8

auto[1]

205

1

T3

2

T10

2

T34

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2408

1

T3

2

T10

16

T11

8

auto[1]

189

1

T3

6

T37

7

T34

6

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1968

1

T3

6

T10

14

T11

8

auto[1]

629

1

T3

2

T10

2

T21

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	948	1			T21	4		T38	10		T35	11
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	87	1			T3	2		T37	16		T115	10
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	72	1			T37	7		T32	4		T80	10
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	36	1			T3	2		T34	4		T350	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	102	1			T34	2		T32	4		T111	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	8	1			T32	2		T356	1		T239	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	11	1			T3	2		T111	1		T309	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	5	1			T229	5		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	85	1			T10	4		T33	7		T227	10
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T115	1		T357	3		T354	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	16	1			T3	2		T33	4		T350	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T356	4		T358	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	16	1			T32	4		T341	9		T239	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T359	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	6	1			T360	6		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	60	1			T11	2		T37	11		T34	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	28	1			T342	3		T79	8		T361	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	2	1			T362	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	2	1			T34	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	6	1			T10	2		T258	1		T309	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T363	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	16	1			T79	1		T224	2		T364	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	14	1			T342	2		T225	3		T364	4
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T341	4		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T111	2		T365	3		T366	1

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

136

1

T10

4

T34

2

T111

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

164

1

T10

2

T94

12

T336

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

44

1

T21

4

T33

7

T227

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

140

1

T3

2

T37

11

T333

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T3

2

T254

4

T350

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T163

6

T340

8

T335

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

44

1

T47

3

T365

8

T367

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

177

1

T37

7

T34

2

T229

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

50

1

T38

8

T111

4

T240

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

37

1

T342

3

T349

1

T255

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T113

2

T111

4

T333

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T11

2

T35

6

T163

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T94

3

T293

3

T242

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T77

3

T36

4

T340

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T36

1

T198

1

T368

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

94

1

T32

6

T227

6

T353

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

52

1

T116

1

T181

5

T360

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T3

2

T35

3

T77

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T35

2

T227

5

T163

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

63

1

T37

16

T242

6

T350

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T33

4

T369

1

T367

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T113

4

T295

4

T80

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T370

1

T371

2

T372

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

81

1

T3

2

T34

4

T111

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T295

1

T240

1

T337

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T77

1

T353

2

T293

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T34

2

T32

4

T335

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T32

4

T337

1

T373

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T38

2

T113

1

T374

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T259

1

T168

2

T102

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T240

1

T47

2

T181

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded