Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

936

1

T7

11

T26

13

T21

8

auto[1]

931

1

T7

9

T26

7

T21

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

439

1

T7

5

T26

6

T21

3

from_0to1

431

1

T7

5

T26

6

T21

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

925

1

T7

6

T26

12

T21

14

auto[1]

942

1

T7

14

T26

8

T21

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

911

1

T7

9

T26

9

T21

10

auto[1]

956

1

T7

11

T26

11

T21

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

48

1

T7

1

T21

1

T72

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T7

2

T26

2

T52

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T7

1

T26

1

T52

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T26

1

T52

2

T71

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T52

3

T71

1

T72

2

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T26

1

T72

1

T233

2

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T26

1

T71

1

T233

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T7

3

T26

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T21

1

T72

1

T233

2

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T26

1

T71

1

T233

1

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T7

1

T71

1

T72

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T26

1

T21

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T26

2

T21

2

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T26

1

T52

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T7

1

T248

1

T65

4

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T7

1

T21

1

T52

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

932

1

T7

9

T26

5

T21

12

auto[1]

935

1

T7

11

T26

15

T21

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

444

1

T7

4

T26

4

T21

6

from_0to1

450

1

T7

3

T26

4

T21

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T7

14

T26

8

T21

13

auto[1]

888

1

T7

6

T26

12

T21

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

929

1

T7

8

T26

11

T21

12

auto[1]

938

1

T7

12

T26

9

T21

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T7

1

T21

1

T261

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T21

1

T52

2

T71

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T21

3

T52

1

T72

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T52

1

T72

1

T233

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T7

2

T26

1

T21

3

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T52

1

T72

1

T248

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T71

1

T233

1

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T21

1

T233

3

T45

2

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T26

2

T21

1

T71

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T7

2

T72

1

T233

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T72

1

T233

1

T45

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T7

1

T26

2

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T71

2

T233

2

T248

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T7

1

T26

1

T21

3

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T26

1

T72

1

T248

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T26

1

T72

2

T65

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

919

1

T7

11

T26

9

T21

10

auto[1]

948

1

T7

9

T26

11

T21

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

453

1

T7

4

T26

5

T21

6

from_0to1

447

1

T7

5

T26

5

T21

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

908

1

T7

11

T26

11

T21

9

auto[1]

959

1

T7

9

T26

9

T21

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

940

1

T7

7

T26

10

T21

10

auto[1]

927

1

T7

13

T26

10

T21

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T7

1

T26

1

T21

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T7

1

T21

1

T52

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T26

1

T21

1

T71

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T7

1

T261

1

T150

3

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T7

1

T26

1

T52

2

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T7

2

T21

1

T233

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T26

1

T21

3

T71

2

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T7

1

T52

1

T71

2

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T26

1

T21

1

T52

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T26

1

T72

1

T233

2

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T7

1

T21

1

T71

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T26

1

T21

1

T52

2

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T26

1

T52

1

T233

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T7

1

T26

1

T52

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T52

1

T71

1

T233

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T26

1

T21

1

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T7

11

T26

12

T21

13

auto[1]

906

1

T7

9

T26

8

T21

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

437

1

T7

4

T26

3

T21

5

from_0to1

437

1

T7

4

T26

3

T21

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T7

11

T26

9

T21

12

auto[1]

906

1

T7

9

T26

11

T21

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

914

1

T7

9

T26

15

T21

7

auto[1]

953

1

T7

11

T26

5

T21

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T26

2

T52

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T21

1

T72

2

T248

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T7

1

T26

1

T52

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T7

2

T21

3

T52

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T7

2

T21

2

T261

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T7

1

T52

1

T71

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T26

1

T45

1

T248

2

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T21

1

T52

2

T71

2

auto[1]

from_1to0

auto[0]

auto[0]

44

1

T21

1

T71

1

T45

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T52

1

T72

1

T248

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T45

1

T248

1

T65

5

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T7

1

T71

2

T261

2

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T71

1

T233

1

T261

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T7

1

T21

1

T52

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T26

2

T21

1

T233

2

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T71

1

T72

2

T233

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

943

1

T7

11

T26

13

T21

14

auto[1]

924

1

T7

9

T26

7

T21

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

432

1

T7

4

T26

3

T21

4

from_0to1

428

1

T7

3

T26

3

T21

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

928

1

T7

13

T26

10

T21

11

auto[1]

939

1

T7

7

T26

10

T21

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

914

1

T7

9

T26

9

T21

10

auto[1]

953

1

T7

11

T26

11

T21

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T7

1

T52

2

T72

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T7

1

T26

1

T21

2

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T7

1

T261

2

T65

4

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T26

1

T233

1

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T7

1

T21

2

T52

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T21

1

T52

1

T45

2

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T7

1

T21

1

T52

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T21

1

T52

1

T71

2

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T52

1

T71

2

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T21

2

T71

1

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T26

1

T52

2

T248

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T7

1

T71

1

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T26

1

T71

1

T72

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T7

1

T26

1

T52

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T72

2

T233

1

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

37

1

T26

1

T71

1

T65

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

954

1

T7

6

T26

9

T21

11

auto[1]

913

1

T7

14

T26

11

T21

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

445

1

T7

6

T26

3

T21

4

from_0to1

442

1

T7

5

T26

4

T21

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

895

1

T7

13

T26

11

T21

11

auto[1]

972

1

T7

7

T26

9

T21

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

909

1

T7

6

T26

11

T21

7

auto[1]

958

1

T7

14

T26

9

T21

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T26

1

T21

1

T52

2

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T7

1

T52

1

T71

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T52

1

T72

1

T248

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T21

2

T71

1

T233

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T7

2

T26

1

T52

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T26

1

T52

1

T71

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T26

1

T21

2

T52

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T45

1

T248

1

T261

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T7

1

T26

1

T72

2

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T7

2

T21

1

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T7

1

T26

1

T72

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T7

1

T52

1

T71

3

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T7

1

T71

1

T233

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T7

2

T21

3

T52

3

auto[1]

from_0to1

auto[1]

auto[0]

48

1

T72

1

T261

1

T65

3

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T26

1

T71

2

T248

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

970

1

T7

11

T26

15

T21

10

auto[1]

897

1

T7

9

T26

5

T21

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

435

1

T7

6

T26

4

T21

3

from_0to1

438

1

T7

5

T26

3

T21

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

937

1

T7

7

T26

13

T21

8

auto[1]

930

1

T7

13

T26

7

T21

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

941

1

T7

13

T26

11

T21

11

auto[1]

926

1

T7

7

T26

9

T21

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T7

1

T26

2

T21

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T7

1

T21

1

T71

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T233

1

T261

1

T65

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T7

2

T26

1

T52

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T21

1

T71

1

T72

2

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T71

2

T261

1

T65

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T7

2

T26

2

T21

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T7

2

T26

1

T21

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T21

1

T72

1

T233

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T7

1

T233

1

T248

2

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T7

1

T26

1

T52

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T52

1

T71

2

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T7

1

T71

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T52

1

T71

1

T72

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T21

1

T52

1

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T72

1

T233

1

T45

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

963

1

T7

16

T26

13

T21

8

auto[1]

904

1

T7

4

T26

7

T21

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

458

1

T7

2

T26

4

T21

7

from_0to1

462

1

T7

3

T26

5

T21

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

920

1

T7

7

T26

9

T21

13

auto[1]

947

1

T7

13

T26

11

T21

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

934

1

T7

9

T26

8

T21

9

auto[1]

933

1

T7

11

T26

12

T21

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T7

1

T21

1

T233

1

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T26

1

T45

1

T248

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T52

1

T72

1

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T7

1

T21

3

T71

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T7

2

T26

1

T71

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T26

1

T21

2

T52

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T52

1

T248

1

T261

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T7

1

T26

2

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T26

1

T21

2

T72

3

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T26

1

T21

1

T52

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T52

2

T71

3

T233

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T26

1

T71

1

T65

4

auto[1]

from_0to1

auto[0]

auto[0]

42

1

T26

1

T21

2

T71

2

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T21

3

T52

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T21

1

T52

1

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T52

1

T71

1

T72

1