Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156035	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122936

1

T5

12

T1

20

T6

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141009	1			T5	26		T1	25		T6	8
values[0x0]	68649	1			T1	9		T6	4		T13	8
values[0x1]	69313	1			T1	5		T6	5		T13	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152379

1

T5

12

T1

22

T6

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	807	1			T3	1		T7	9		T61	1
valid_sources[0x01]	1136	1			T3	1		T7	5		T27	2
valid_sources[0x02]	1335	1			T3	8		T8	1		T10	6
valid_sources[0x03]	862	1			T3	2		T7	1		T61	5
valid_sources[0x04]	2585	1			T3	4		T7	3		T58	1
valid_sources[0x05]	967	1			T6	1		T13	1		T7	19
valid_sources[0x06]	1016	1			T19	5		T3	3		T7	13
valid_sources[0x07]	985	1			T3	3		T7	1		T58	1
valid_sources[0x08]	772	1			T3	5		T9	2		T11	5
valid_sources[0x09]	943	1			T16	1		T3	6		T7	5
valid_sources[0x0a]	1024	1			T7	5		T58	1		T10	8
valid_sources[0x0b]	844	1			T3	2		T10	11		T11	7
valid_sources[0x0c]	933	1			T6	1		T3	1		T10	2
valid_sources[0x0d]	912	1			T14	2		T17	1		T3	1
valid_sources[0x0e]	1789	1			T3	4		T7	6		T9	1
valid_sources[0x0f]	1931	1			T3	4		T7	3		T9	5
valid_sources[0x10]	741	1			T3	3		T7	5		T61	1
valid_sources[0x11]	1013	1			T9	5		T11	2		T252	1
valid_sources[0x12]	1068	1			T3	4		T10	5		T11	5
valid_sources[0x13]	1397	1			T9	2		T10	4		T11	5
valid_sources[0x14]	2054	1			T1	1		T14	9		T3	8
valid_sources[0x15]	1213	1			T3	2		T7	3		T70	1
valid_sources[0x16]	822	1			T3	7		T7	8		T10	1
valid_sources[0x17]	1027	1			T1	2		T3	4		T7	16
valid_sources[0x18]	3612	1			T3	11		T7	7		T10	5
valid_sources[0x19]	999	1			T3	1		T7	1		T9	3
valid_sources[0x1a]	1286	1			T3	7		T7	6		T10	4
valid_sources[0x1b]	1191	1			T3	3		T7	3		T9	2
valid_sources[0x1c]	1004	1			T3	3		T7	21		T9	2
valid_sources[0x1d]	870	1			T16	1		T17	2		T7	4
valid_sources[0x1e]	955	1			T1	1		T3	2		T7	11
valid_sources[0x1f]	1997	1			T14	2		T3	4		T9	3
valid_sources[0x20]	1453	1			T3	4		T7	19		T27	1
valid_sources[0x21]	769	1			T3	2		T7	6		T9	5
valid_sources[0x22]	714	1			T3	1		T9	1		T11	2
valid_sources[0x23]	825	1			T13	1		T3	3		T9	1
valid_sources[0x24]	829	1			T3	5		T9	1		T10	2
valid_sources[0x25]	1020	1			T2	3		T3	5		T10	1
valid_sources[0x26]	863	1			T1	1		T13	1		T3	2
valid_sources[0x27]	954	1			T7	5		T10	9		T11	2
valid_sources[0x28]	1054	1			T5	3		T20	1		T3	1
valid_sources[0x29]	935	1			T13	1		T7	2		T58	2
valid_sources[0x2a]	924	1			T6	1		T13	1		T3	7
valid_sources[0x2b]	2339	1			T7	20		T9	1		T10	8
valid_sources[0x2c]	831	1			T3	6		T7	8		T61	2
valid_sources[0x2d]	749	1			T1	1		T3	4		T10	1
valid_sources[0x2e]	767	1			T3	3		T58	2		T9	1
valid_sources[0x2f]	1137	1			T13	2		T7	1		T61	1
valid_sources[0x30]	1032	1			T13	2		T3	1		T9	2
valid_sources[0x31]	1198	1			T1	2		T3	6		T7	5
valid_sources[0x32]	1189	1			T3	5		T9	1		T10	2
valid_sources[0x33]	865	1			T1	1		T3	5		T7	13
valid_sources[0x34]	825	1			T13	1		T3	1		T7	3
valid_sources[0x35]	955	1			T13	1		T3	1		T27	1
valid_sources[0x36]	904	1			T57	1		T3	4		T7	3
valid_sources[0x37]	907	1			T15	1		T3	1		T9	1
valid_sources[0x38]	928	1			T7	1		T9	4		T10	2
valid_sources[0x39]	949	1			T15	1		T7	1		T61	1
valid_sources[0x3a]	954	1			T3	5		T7	11		T9	1
valid_sources[0x3b]	921	1			T3	2		T7	5		T58	1
valid_sources[0x3c]	883	1			T57	2		T3	1		T7	2
valid_sources[0x3d]	974	1			T3	2		T10	3		T11	2
valid_sources[0x3e]	1217	1			T13	1		T3	6		T7	4
valid_sources[0x3f]	1146	1			T16	1		T10	1		T69	1
valid_sources[0x40]	912	1			T3	8		T7	9		T8	1
valid_sources[0x41]	924	1			T3	3		T10	4		T11	5
valid_sources[0x42]	2107	1			T6	3		T3	1		T7	8
valid_sources[0x43]	890	1			T3	10		T61	2		T10	2
valid_sources[0x44]	1061	1			T3	3		T7	1		T9	2
valid_sources[0x45]	1027	1			T15	1		T3	11		T61	1
valid_sources[0x46]	2077	1			T10	7		T11	4		T51	1
valid_sources[0x47]	1018	1			T3	4		T7	1		T10	8
valid_sources[0x48]	1053	1			T1	2		T3	3		T7	14
valid_sources[0x49]	934	1			T13	1		T3	4		T27	2
valid_sources[0x4a]	931	1			T3	8		T7	11		T61	5
valid_sources[0x4b]	921	1			T13	1		T3	3		T7	10
valid_sources[0x4c]	957	1			T20	1		T3	7		T7	9
valid_sources[0x4d]	913	1			T3	5		T58	2		T10	6
valid_sources[0x4e]	1216	1			T15	1		T20	1		T10	5
valid_sources[0x4f]	903	1			T5	1		T3	13		T9	1
valid_sources[0x50]	2265	1			T3	3		T9	2		T10	2
valid_sources[0x51]	840	1			T3	1		T9	2		T10	5
valid_sources[0x52]	1003	1			T3	2		T7	3		T27	1
valid_sources[0x53]	957	1			T3	2		T10	11		T11	6
valid_sources[0x54]	823	1			T3	2		T7	9		T61	2
valid_sources[0x55]	890	1			T15	1		T3	1		T58	1
valid_sources[0x56]	1283	1			T5	6		T14	1		T16	1
valid_sources[0x57]	906	1			T13	2		T3	3		T9	2
valid_sources[0x58]	907	1			T3	3		T9	2		T10	3
valid_sources[0x59]	861	1			T15	1		T9	4		T10	6
valid_sources[0x5a]	833	1			T3	7		T7	8		T9	1
valid_sources[0x5b]	880	1			T3	2		T7	3		T9	1
valid_sources[0x5c]	1297	1			T13	1		T3	4		T7	9
valid_sources[0x5d]	804	1			T14	1		T18	6		T3	2
valid_sources[0x5e]	1665	1			T14	5		T3	1		T27	1
valid_sources[0x5f]	1321	1			T3	4		T9	3		T11	5
valid_sources[0x60]	924	1			T13	1		T3	4		T9	2
valid_sources[0x61]	952	1			T3	3		T58	1		T61	1
valid_sources[0x62]	1167	1			T6	1		T3	3		T7	8
valid_sources[0x63]	1143	1			T1	2		T3	2		T7	3
valid_sources[0x64]	1095	1			T3	6		T7	11		T10	1
valid_sources[0x65]	1060	1			T1	1		T3	4		T7	2
valid_sources[0x66]	877	1			T1	1		T3	8		T7	2
valid_sources[0x67]	959	1			T14	4		T3	3		T7	1
valid_sources[0x68]	949	1			T13	1		T3	1		T10	3
valid_sources[0x69]	1205	1			T3	2		T9	2		T10	4
valid_sources[0x6a]	920	1			T3	4		T69	1		T11	7
valid_sources[0x6b]	1040	1			T1	2		T3	10		T7	20
valid_sources[0x6c]	1086	1			T3	2		T61	2		T9	3
valid_sources[0x6d]	1060	1			T3	1		T7	5		T10	4
valid_sources[0x6e]	874	1			T3	3		T7	5		T10	6
valid_sources[0x6f]	922	1			T27	7		T9	1		T10	6
valid_sources[0x70]	766	1			T6	1		T14	4		T3	4
valid_sources[0x71]	1025	1			T3	2		T10	2		T11	5
valid_sources[0x72]	760	1			T1	1		T16	1		T3	5
valid_sources[0x73]	1197	1			T13	1		T3	8		T10	3
valid_sources[0x74]	1347	1			T2	1		T3	4		T7	19
valid_sources[0x75]	997	1			T5	5		T3	5		T7	5
valid_sources[0x76]	770	1			T3	5		T7	1		T27	5
valid_sources[0x77]	1116	1			T3	3		T4	17		T10	4
valid_sources[0x78]	1026	1			T3	1		T58	1		T61	1
valid_sources[0x79]	1484	1			T7	2		T9	2		T63	1
valid_sources[0x7a]	1308	1			T13	1		T3	6		T27	1
valid_sources[0x7b]	2005	1			T13	1		T3	3		T7	5
valid_sources[0x7c]	1287	1			T13	1		T3	5		T10	1
valid_sources[0x7d]	961	1			T3	2		T9	3		T10	2
valid_sources[0x7e]	1521	1			T5	1		T3	1		T9	6
valid_sources[0x7f]	1054	1			T6	4		T7	1		T58	1
valid_sources[0x80]	1009	1			T16	2		T3	8		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64688

1

T5

12

T1

14

T6

4

values[0x0]

all_enables

biggest_size

34042

1

T1

5

T6

3

T13

3

values[0x1]

all_enables

biggest_size

24206

1

T1

1

T6

2

T13

3