Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T6,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T15,T16
1	0	Covered	T5,T1,T6
1	1	Covered	T6,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T15,T7
0	1	Covered	T6,T16,T99
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T7,T48
0	1	Covered	T6,T15,T7
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T7,T48
1	-	Covered	T6,T15,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T15,T16
DetectSt	168	Covered	T6,T15,T16
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T6,T15,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T15,T16
DebounceSt->IdleSt	163	Covered	T7,T51,T47
DetectSt->IdleSt	186	Covered	T6,T16,T99
DetectSt->StableSt	191	Covered	T6,T15,T7
IdleSt->DebounceSt	148	Covered	T6,T15,T16
StableSt->IdleSt	206	Covered	T6,T15,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T15,T16
0	1	Covered	T6,T15,T16
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T15,T16
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T51,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T6,T16,T99
DetectSt	-	-	-	-	0	1	-	Covered	T6,T15,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T15,T7
StableSt	-	-	-	-	-	-	0	Covered	T15,T7,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	297	0	0
CntIncr_A	8913551	237369	0	0
CntNoWrap_A	8913551	8219628	0	0
DetectStDropOut_A	8913551	4	0	0
DetectedOut_A	8913551	882	0	0
DetectedPulseOut_A	8913551	133	0	0
DisabledIdleSt_A	8913551	7970003	0	0
DisabledNoDetection_A	8913551	7972382	0	0
EnterDebounceSt_A	8913551	165	0	0
EnterDetectSt_A	8913551	137	0	0
EnterStableSt_A	8913551	133	0	0
PulseIsPulse_A	8913551	133	0	0
StayInStableSt	8913551	749	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	6953	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	132	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	297	0	0
T2	646	0	0	0
T6	688	4	0	0
T7	0	3	0	0
T9	0	4	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	2	0	0
T16	705	2	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	6	0	0
T48	0	6	0	0
T50	0	2	0	0
T51	0	3	0	0
T92	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	237369	0	0
T2	646	0	0	0
T6	688	149	0	0
T7	0	27	0	0
T9	0	197	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	79	0	0
T16	705	70	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	146	0	0
T48	0	111	0	0
T50	0	86	0	0
T51	0	52	0	0
T92	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219628	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	283	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	260	0	0
T16	705	302	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	4	0	0
T2	646	0	0	0
T6	688	1	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	1	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T86	0	1	0	0
T99	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	882	0	0
T2	646	0	0	0
T6	688	1	0	0
T7	0	7	0	0
T9	0	14	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	8	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	22	0	0
T48	0	24	0	0
T50	0	1	0	0
T51	0	2	0	0
T92	0	3	0	0
T109	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	133	0	0
T2	646	0	0	0
T6	688	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	1	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	3	0	0
T48	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T92	0	1	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7970003	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	64	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	144	0	0
T16	705	197	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7972382	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	64	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	145	0	0
T16	705	198	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	165	0	0
T2	646	0	0	0
T6	688	2	0	0
T7	0	2	0	0
T9	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	1	0	0
T16	705	1	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	3	0	0
T48	0	3	0	0
T50	0	1	0	0
T51	0	2	0	0
T92	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	137	0	0
T2	646	0	0	0
T6	688	2	0	0
T7	0	1	0	0
T9	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	1	0	0
T16	705	1	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	3	0	0
T48	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T92	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	133	0	0
T2	646	0	0	0
T6	688	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	1	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	3	0	0
T48	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T92	0	1	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	133	0	0
T2	646	0	0	0
T6	688	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	1	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	3	0	0
T48	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T92	0	1	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	749	0	0
T2	646	0	0	0
T3	11372	0	0	0
T4	167460	0	0	0
T7	0	6	0	0
T9	0	12	0	0
T15	663	7	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	19	0	0
T38	0	4	0	0
T48	0	21	0	0
T51	0	1	0	0
T57	402	0	0	0
T92	0	2	0	0
T109	0	6	0	0
T114	0	14	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6953	0	0
T1	1047	10	0	0
T3	0	26	0	0
T5	426	2	0	0
T6	688	3	0	0
T7	0	67	0	0
T13	489	5	0	0
T14	2715	8	0	0
T15	663	3	0	0
T16	705	3	0	0
T17	422	1	0	0
T18	410	0	0	0
T19	407	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	132	0	0
T2	646	0	0	0
T6	688	1	0	0
T7	0	1	0	0
T9	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	1	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	3	0	0
T48	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T92	0	1	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T7,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T21
1	0	Covered	T5,T1,T6
1	1	Covered	T1,T7,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T21
0	1	Covered	T1,T76,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T21
0	1	Unreachable
1	0	Covered	T1,T7,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T21
DetectSt	168	Covered	T1,T7,T21
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T21
DebounceSt->IdleSt	163	Covered	T1,T52,T65
DetectSt->IdleSt	186	Covered	T1,T76,T89
DetectSt->StableSt	191	Covered	T1,T7,T21
IdleSt->DebounceSt	148	Covered	T1,T7,T21
StableSt->IdleSt	206	Covered	T1,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T21
0	1	Covered	T1,T7,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T21
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T52,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T21
DetectSt	-	-	-	-	1	-	-	Covered	T1,T76,T89
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T21
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	195	0	0
CntIncr_A	8913551	161065	0	0
CntNoWrap_A	8913551	8219730	0	0
DetectStDropOut_A	8913551	24	0	0
DetectedOut_A	8913551	9035	0	0
DetectedPulseOut_A	8913551	51	0	0
DisabledIdleSt_A	8913551	6638893	0	0
DisabledNoDetection_A	8913551	6641327	0	0
EnterDebounceSt_A	8913551	122	0	0
EnterDetectSt_A	8913551	75	0	0
EnterStableSt_A	8913551	51	0	0
PulseIsPulse_A	8913551	51	0	0
StayInStableSt	8913551	8984	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	6953	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_sticky_sva.StableStDropOut_A	8913551	99155	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	195	0	0
T1	1047	7	0	0
T6	688	0	0	0
T7	0	4	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	2	0	0
T45	0	2	0	0
T52	0	5	0	0
T65	0	3	0	0
T66	0	4	0	0
T74	0	2	0	0
T75	0	4	0	0
T76	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	161065	0	0
T1	1047	104	0	0
T6	688	0	0	0
T7	0	39	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	96	0	0
T45	0	69	0	0
T52	0	318	0	0
T65	0	225	0	0
T66	0	258	0	0
T74	0	49	0	0
T75	0	122	0	0
T76	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219730	0	0
T1	1047	639	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	24	0	0
T1	1047	2	0	0
T6	688	0	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T76	0	1	0	0
T89	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T119	0	3	0	0
T120	0	2	0	0
T121	0	4	0	0
T122	0	1	0	0
T123	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	9035	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	262	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	423	0	0
T45	0	293	0	0
T52	0	56	0	0
T66	0	1	0	0
T74	0	11	0	0
T75	0	425	0	0
T76	0	12	0	0
T90	0	1097	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	51	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T66	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T90	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6638893	0	0
T1	1047	387	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6641327	0	0
T1	1047	388	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	122	0	0
T1	1047	4	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	4	0	0
T65	0	3	0	0
T66	0	3	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	75	0	0
T1	1047	3	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T66	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	2	0	0
T90	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	51	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T66	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T90	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	51	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T66	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T90	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8984	0	0
T7	209575	260	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	422	0	0
T26	503	0	0	0
T27	525	0	0	0
T45	0	292	0	0
T48	660	0	0	0
T52	0	55	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T74	0	10	0	0
T75	0	423	0	0
T76	0	11	0	0
T89	0	88	0	0
T90	0	1096	0	0
T91	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6953	0	0
T1	1047	10	0	0
T3	0	26	0	0
T5	426	2	0	0
T6	688	3	0	0
T7	0	67	0	0
T13	489	5	0	0
T14	2715	8	0	0
T15	663	3	0	0
T16	705	3	0	0
T17	422	1	0	0
T18	410	0	0	0
T19	407	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	99155	0	0
T1	1047	45	0	0
T6	688	0	0	0
T7	0	452	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	84	0	0
T45	0	85	0	0
T52	0	31	0	0
T66	0	80	0	0
T74	0	74	0	0
T75	0	430	0	0
T76	0	73	0	0
T90	0	97	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T13
1	1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T7,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T21
1	0	Covered	T5,T1,T13
1	1	Covered	T1,T7,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T21
0	1	Covered	T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T21
0	1	Unreachable
1	0	Covered	T1,T7,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T21
DetectSt	168	Covered	T1,T7,T21
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T21
DebounceSt->IdleSt	163	Covered	T52,T66,T75
DetectSt->IdleSt	186	Covered	T83
DetectSt->StableSt	191	Covered	T1,T7,T21
IdleSt->DebounceSt	148	Covered	T1,T7,T21
StableSt->IdleSt	206	Covered	T1,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T21
0	1	Covered	T1,T7,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T21
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T66,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T21
DetectSt	-	-	-	-	1	-	-	Covered	T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T21
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	144	0	0
CntIncr_A	8913551	132621	0	0
CntNoWrap_A	8913551	8219781	0	0
DetectStDropOut_A	8913551	2	0	0
DetectedOut_A	8913551	1134832	0	0
DetectedPulseOut_A	8913551	54	0	0
DisabledIdleSt_A	8913551	6638893	0	0
DisabledNoDetection_A	8913551	6641327	0	0
EnterDebounceSt_A	8913551	90	0	0
EnterDetectSt_A	8913551	56	0	0
EnterStableSt_A	8913551	54	0	0
PulseIsPulse_A	8913551	54	0	0
StayInStableSt	8913551	1134778	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_sticky_sva.StableStDropOut_A	8913551	228266	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	144	0	0
T1	1047	2	0	0
T6	688	0	0	0
T7	0	4	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	2	0	0
T45	0	2	0	0
T52	0	4	0	0
T65	0	2	0	0
T66	0	3	0	0
T74	0	2	0	0
T75	0	5	0	0
T76	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	132621	0	0
T1	1047	11	0	0
T6	688	0	0	0
T7	0	86	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	25	0	0
T45	0	32	0	0
T52	0	144	0	0
T65	0	36	0	0
T66	0	99	0	0
T74	0	44	0	0
T75	0	350	0	0
T76	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219781	0	0
T1	1047	644	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	2	0	0
T83	113920	2	0	0
T124	454	0	0	0
T125	475	0	0	0
T126	70099	0	0	0
T127	10480	0	0	0
T128	427	0	0	0
T129	498	0	0	0
T130	480	0	0	0
T131	138682	0	0	0
T132	649	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1134832	0	0
T1	1047	55	0	0
T6	688	0	0	0
T7	0	394	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	170	0	0
T45	0	202	0	0
T65	0	161	0	0
T74	0	3	0	0
T89	0	334	0	0
T91	0	218	0	0
T116	0	12	0	0
T117	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	54	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T89	0	1	0	0
T91	0	1	0	0
T116	0	2	0	0
T117	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6638893	0	0
T1	1047	387	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6641327	0	0
T1	1047	388	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	90	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	4	0	0
T65	0	1	0	0
T66	0	3	0	0
T74	0	1	0	0
T75	0	5	0	0
T76	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	56	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T89	0	1	0	0
T91	0	1	0	0
T116	0	2	0	0
T117	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	54	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T89	0	1	0	0
T91	0	1	0	0
T116	0	2	0	0
T117	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	54	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T89	0	1	0	0
T91	0	1	0	0
T116	0	2	0	0
T117	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1134778	0	0
T1	1047	54	0	0
T6	688	0	0	0
T7	0	392	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	169	0	0
T45	0	201	0	0
T65	0	160	0	0
T74	0	2	0	0
T89	0	333	0	0
T91	0	217	0	0
T116	0	10	0	0
T117	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	228266	0	0
T1	1047	170	0	0
T6	688	0	0	0
T7	0	274	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	409	0	0
T45	0	215	0	0
T65	0	315	0	0
T74	0	93	0	0
T89	0	79	0	0
T91	0	58	0	0
T116	0	216	0	0
T117	0	627	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T7,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T21
1	0	Covered	T5,T1,T13
1	1	Covered	T1,T7,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T21
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T21
0	1	Unreachable
1	0	Covered	T1,T7,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T21
DetectSt	168	Covered	T1,T7,T21
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T21
DebounceSt->IdleSt	163	Covered	T42,T90,T91
DetectSt->IdleSt	186	Covered	T82,T83,T84
DetectSt->StableSt	191	Covered	T1,T7,T21
IdleSt->DebounceSt	148	Covered	T1,T7,T21
StableSt->IdleSt	206	Covered	T1,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T21
0	1	Covered	T1,T7,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T21
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T90,T91,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T21
DetectSt	-	-	-	-	1	-	-	Covered	T82,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T21
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	175	0	0
CntIncr_A	8913551	119996	0	0
CntNoWrap_A	8913551	8219750	0	0
DetectStDropOut_A	8913551	14	0	0
DetectedOut_A	8913551	36939	0	0
DetectedPulseOut_A	8913551	52	0	0
DisabledIdleSt_A	8913551	6638893	0	0
DisabledNoDetection_A	8913551	6641327	0	0
EnterDebounceSt_A	8913551	111	0	0
EnterDetectSt_A	8913551	66	0	0
EnterStableSt_A	8913551	52	0	0
PulseIsPulse_A	8913551	52	0	0
StayInStableSt	8913551	36887	0	0
gen_high_event_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_sticky_sva.StableStDropOut_A	8913551	194715	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	175	0	0
T1	1047	2	0	0
T6	688	0	0	0
T7	0	4	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	2	0	0
T45	0	2	0	0
T52	0	4	0	0
T65	0	2	0	0
T66	0	4	0	0
T74	0	2	0	0
T75	0	4	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	119996	0	0
T1	1047	28	0	0
T6	688	0	0	0
T7	0	92	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	36	0	0
T45	0	37	0	0
T52	0	123	0	0
T65	0	64	0	0
T66	0	194	0	0
T74	0	63	0	0
T75	0	170	0	0
T76	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219750	0	0
T1	1047	644	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	14	0	0
T82	125368	8	0	0
T83	0	1	0	0
T84	0	1	0	0
T97	27400	0	0	0
T118	15682	0	0	0
T133	0	4	0	0
T134	422	0	0	0
T135	402	0	0	0
T136	423	0	0	0
T137	1077	0	0	0
T138	1113	0	0	0
T139	422	0	0	0
T140	1026	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	36939	0	0
T1	1047	169	0	0
T6	688	0	0	0
T7	0	472	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	152	0	0
T45	0	172	0	0
T52	0	218	0	0
T65	0	296	0	0
T66	0	245	0	0
T74	0	56	0	0
T75	0	395	0	0
T76	0	75	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6638893	0	0
T1	1047	387	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6641327	0	0
T1	1047	388	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	111	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	66	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T1	1047	1	0	0
T6	688	0	0	0
T7	0	2	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	36887	0	0
T1	1047	168	0	0
T6	688	0	0	0
T7	0	470	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	151	0	0
T45	0	171	0	0
T52	0	216	0	0
T65	0	295	0	0
T66	0	243	0	0
T74	0	55	0	0
T75	0	393	0	0
T76	0	74	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	194715	0	0
T1	1047	55	0	0
T6	688	0	0	0
T7	0	199	0	0
T13	489	0	0	0
T14	2715	0	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	0	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T21	0	427	0	0
T45	0	247	0	0
T52	0	222	0	0
T65	0	165	0	0
T66	0	71	0	0
T74	0	30	0	0
T75	0	436	0	0
T76	0	52	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T46,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T21
1	0	Covered	T5,T1,T6
1	1	Covered	T7,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T46,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T46,T42
0	1	Covered	T7,T46,T47
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T46,T42
1	-	Covered	T7,T46,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T45,T46
DetectSt	168	Covered	T7,T46,T42
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T46,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T46,T42
DebounceSt->IdleSt	163	Covered	T45,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T46,T42
IdleSt->DebounceSt	148	Covered	T7,T45,T46
StableSt->IdleSt	206	Covered	T7,T46,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T45,T46
0	1	Covered	T7,T45,T46
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T46,T42
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T46,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T45
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T45,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T46,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T46,T42
StableSt	-	-	-	-	-	-	0	Covered	T7,T46,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	80	0	0
CntIncr_A	8913551	60470	0	0
CntNoWrap_A	8913551	8219845	0	0
DetectStDropOut_A	8913551	0	0	0
DetectedOut_A	8913551	19969	0	0
DetectedPulseOut_A	8913551	39	0	0
DisabledIdleSt_A	8913551	7947529	0	0
DisabledNoDetection_A	8913551	7949908	0	0
EnterDebounceSt_A	8913551	41	0	0
EnterDetectSt_A	8913551	39	0	0
EnterStableSt_A	8913551	39	0	0
PulseIsPulse_A	8913551	39	0	0
StayInStableSt	8913551	19908	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	80	0	0
T7	209575	8	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	2	0	0
T45	0	1	0	0
T46	0	4	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	4	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	60470	0	0
T7	209575	58536	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	25	0	0
T45	0	10	0	0
T46	0	154	0	0
T47	0	19	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	172	0	0
T141	0	19	0	0
T142	0	33	0	0
T143	0	32	0	0
T144	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219845	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	19969	0	0
T7	209575	18077	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	18	0	0
T46	0	250	0	0
T47	0	92	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	79	0	0
T141	0	41	0	0
T142	0	37	0	0
T143	0	93	0	0
T144	0	43	0	0
T145	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	39	0	0
T7	209575	4	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7947529	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7949908	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	41	0	0
T7	209575	4	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	39	0	0
T7	209575	4	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	39	0	0
T7	209575	4	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	39	0	0
T7	209575	4	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	19908	0	0
T7	209575	18071	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	17	0	0
T46	0	247	0	0
T47	0	91	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T122	0	76	0	0
T141	0	39	0	0
T142	0	35	0	0
T143	0	91	0	0
T144	0	42	0	0
T145	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	16	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T85	0	1	0	0
T122	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T13,T14,T17
1	1	Covered	T7,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T21
0	1	Covered	T12,T43,T142
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T21
0	1	Covered	T7,T8,T21
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T21
1	-	Covered	T7,T8,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T12
DetectSt	168	Covered	T7,T8,T12
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T8,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T12
DebounceSt->IdleSt	163	Covered	T7,T116,T78
DetectSt->IdleSt	186	Covered	T12,T43,T142
DetectSt->StableSt	191	Covered	T7,T8,T21
IdleSt->DebounceSt	148	Covered	T7,T8,T12
StableSt->IdleSt	206	Covered	T7,T8,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T12
0	1	Covered	T7,T8,T12
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T12
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T116,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T12,T43,T142
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T21
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	117	0	0
CntIncr_A	8913551	61587	0	0
CntNoWrap_A	8913551	8219808	0	0
DetectStDropOut_A	8913551	3	0	0
DetectedOut_A	8913551	59890	0	0
DetectedPulseOut_A	8913551	52	0	0
DisabledIdleSt_A	8913551	7841101	0	0
DisabledNoDetection_A	8913551	7843482	0	0
EnterDebounceSt_A	8913551	62	0	0
EnterDetectSt_A	8913551	55	0	0
EnterStableSt_A	8913551	52	0	0
PulseIsPulse_A	8913551	52	0	0
StayInStableSt	8913551	59822	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	2748	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	117	0	0
T7	209575	7	0	0
T8	587	2	0	0
T9	5748	0	0	0
T12	0	2	0	0
T21	0	6	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	4	0	0
T41	0	4	0	0
T42	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	2	0	0
T88	0	4	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	61587	0	0
T7	209575	58536	0	0
T8	587	52	0	0
T9	5748	0	0	0
T12	0	54	0	0
T21	0	67	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	144	0	0
T41	0	158	0	0
T42	0	25	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	26	0	0
T88	0	132	0	0
T150	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219808	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	3	0	0
T12	558	1	0	0
T21	72090	0	0	0
T43	0	1	0	0
T50	705	0	0	0
T51	661	0	0	0
T52	8117	0	0	0
T67	496	0	0	0
T68	1387	0	0	0
T70	528	0	0	0
T142	0	1	0	0
T151	427	0	0	0
T152	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	59890	0	0
T7	209575	55275	0	0
T8	587	30	0	0
T9	5748	0	0	0
T21	0	308	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	241	0	0
T41	0	171	0	0
T42	0	19	0	0
T47	0	82	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	92	0	0
T88	0	239	0	0
T150	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T7	209575	3	0	0
T8	587	1	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	2	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7841101	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7843482	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	62	0	0
T7	209575	4	0	0
T8	587	1	0	0
T9	5748	0	0	0
T12	0	1	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	2	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	55	0	0
T7	209575	3	0	0
T8	587	1	0	0
T9	5748	0	0	0
T12	0	1	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	2	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T7	209575	3	0	0
T8	587	1	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	2	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T7	209575	3	0	0
T8	587	1	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	2	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	59822	0	0
T7	209575	55272	0	0
T8	587	29	0	0
T9	5748	0	0	0
T21	0	305	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	239	0	0
T41	0	169	0	0
T42	0	18	0	0
T47	0	79	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	90	0	0
T88	0	237	0	0
T150	0	19	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	2748	0	0
T2	646	1	0	0
T7	0	52	0	0
T13	489	3	0	0
T14	2715	5	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	2	0	0
T18	410	0	0	0
T19	407	0	0	0
T20	629	0	0	0
T26	0	4	0	0
T57	402	0	0	0
T58	0	4	0	0
T59	0	5	0	0
T60	0	2	0	0
T61	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	35	0	0
T7	209575	3	0	0
T8	587	1	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T131	0	1	0	0
T141	0	1	0	0
T150	0	1	0	0