Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T7,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T7,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T12
0	1	Covered	T88,T40,T47
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T12
1	-	Covered	T88,T40,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T12
DetectSt	168	Covered	T4,T7,T12
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T7,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T12
DebounceSt->IdleSt	163	Covered	T123,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T7,T12
IdleSt->DebounceSt	148	Covered	T4,T7,T12
StableSt->IdleSt	206	Covered	T7,T45,T88

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T12
0	1	Covered	T4,T7,T12
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T12
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T12
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T88,T40,T42
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	67	0	0
CntIncr_A	8913551	145706	0	0
CntNoWrap_A	8913551	8219858	0	0
DetectStDropOut_A	8913551	0	0	0
DetectedOut_A	8913551	330608	0	0
DetectedPulseOut_A	8913551	33	0	0
DisabledIdleSt_A	8913551	7238659	0	0
DisabledNoDetection_A	8913551	7241037	0	0
EnterDebounceSt_A	8913551	35	0	0
EnterDetectSt_A	8913551	33	0	0
EnterStableSt_A	8913551	33	0	0
PulseIsPulse_A	8913551	33	0	0
StayInStableSt	8913551	330556	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	67	0	0
T4	167460	2	0	0
T7	209575	2	0	0
T8	587	0	0	0
T12	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	4	0	0
T42	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	4	0	0
T153	0	2	0	0
T154	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	145706	0	0
T4	167460	51135	0	0
T7	209575	29212	0	0
T8	587	0	0	0
T12	0	54	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	144	0	0
T42	0	25	0	0
T45	0	10	0	0
T47	0	19	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	132	0	0
T153	0	90	0	0
T154	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219858	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	330608	0	0
T4	167460	51178	0	0
T7	209575	84476	0	0
T8	587	0	0	0
T12	0	39	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	83	0	0
T42	0	18	0	0
T45	0	48	0	0
T47	0	93	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	172	0	0
T153	0	41	0	0
T154	0	121	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	33	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T12	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7238659	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7241037	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	35	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T12	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	33	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T12	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	33	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T12	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	33	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T12	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T153	0	1	0	0
T154	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	330556	0	0
T4	167460	51176	0	0
T7	209575	84474	0	0
T8	587	0	0	0
T12	0	37	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	80	0	0
T42	0	17	0	0
T45	0	46	0	0
T47	0	92	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	170	0	0
T153	0	39	0	0
T154	0	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	13	0	0
T40	3631	1	0	0
T47	0	1	0	0
T66	1294	0	0	0
T88	1001	2	0	0
T143	0	1	0	0
T146	0	1	0	0
T150	10777	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	1591	0	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T13,T14
1	1	Covered	T4,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Covered	T12,T88,T165
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Covered	T4,T88,T46
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T9
1	-	Covered	T4,T88,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T9
DetectSt	168	Covered	T4,T7,T9
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T9
DebounceSt->IdleSt	163	Covered	T44,T137,T166
DetectSt->IdleSt	186	Covered	T12,T88,T165
DetectSt->StableSt	191	Covered	T4,T7,T9
IdleSt->DebounceSt	148	Covered	T4,T7,T9
StableSt->IdleSt	206	Covered	T4,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T9
0	1	Covered	T4,T7,T9
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T137,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T12,T88,T165
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T88,T46
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	118	0	0
CntIncr_A	8913551	54175	0	0
CntNoWrap_A	8913551	8219807	0	0
DetectStDropOut_A	8913551	4	0	0
DetectedOut_A	8913551	16929	0	0
DetectedPulseOut_A	8913551	52	0	0
DisabledIdleSt_A	8913551	7984521	0	0
DisabledNoDetection_A	8913551	7986904	0	0
EnterDebounceSt_A	8913551	63	0	0
EnterDetectSt_A	8913551	56	0	0
EnterStableSt_A	8913551	52	0	0
PulseIsPulse_A	8913551	52	0	0
StayInStableSt	8913551	16851	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	3174	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	118	0	0
T4	167460	2	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	0	2	0	0
T12	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	2	0	0
T42	0	2	0	0
T46	0	4	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	2	0	0
T88	0	6	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	54175	0	0
T4	167460	51135	0	0
T7	209575	56	0	0
T8	587	0	0	0
T9	0	68	0	0
T12	0	54	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	38	0	0
T42	0	25	0	0
T46	0	154	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	26	0	0
T88	0	198	0	0
T153	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219807	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	4	0	0
T12	558	1	0	0
T21	72090	0	0	0
T50	705	0	0	0
T51	661	0	0	0
T52	8117	0	0	0
T67	496	0	0	0
T68	1387	0	0	0
T70	528	0	0	0
T86	0	1	0	0
T88	0	1	0	0
T151	427	0	0	0
T152	422	0	0	0
T165	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	16929	0	0
T4	167460	13602	0	0
T7	209575	40	0	0
T8	587	0	0	0
T9	0	36	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	266	0	0
T42	0	18	0	0
T46	0	65	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	92	0	0
T88	0	85	0	0
T153	0	123	0	0
T167	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	2	0	0
T153	0	1	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7984521	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7986904	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	63	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	0	1	0	0
T12	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	3	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	56	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	0	1	0	0
T12	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	3	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	2	0	0
T153	0	1	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	52	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	2	0	0
T153	0	1	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	16851	0	0
T4	167460	13601	0	0
T7	209575	38	0	0
T8	587	0	0	0
T9	0	34	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	264	0	0
T42	0	17	0	0
T46	0	62	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	90	0	0
T88	0	82	0	0
T153	0	121	0	0
T167	0	26	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	3174	0	0
T1	1047	0	0	0
T4	0	1	0	0
T5	426	3	0	0
T6	688	0	0	0
T7	0	53	0	0
T13	489	5	0	0
T14	2715	18	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	3	0	0
T18	410	1	0	0
T19	407	0	0	0
T20	0	3	0	0
T58	0	4	0	0
T59	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	25	0	0
T4	167460	1	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	1	0	0
T116	0	1	0	0
T122	0	2	0	0
T137	0	1	0	0
T143	0	1	0	0
T154	0	2	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T13
1	1	Covered	T5,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T21,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T21,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T21,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T21
1	0	Covered	T5,T1,T13
1	1	Covered	T7,T21,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T45
0	1	Covered	T7,T21,T40
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T21,T45
1	-	Covered	T7,T21,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T21,T45
DetectSt	168	Covered	T7,T21,T45
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T21,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T21,T45
DebounceSt->IdleSt	163	Covered	T7,T44,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T21,T45
IdleSt->DebounceSt	148	Covered	T7,T21,T45
StableSt->IdleSt	206	Covered	T7,T21,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T21,T45
0	1	Covered	T7,T21,T45
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T21,T45
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T21,T45
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T21,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T21,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T21,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T21,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T21,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	117	0	0
CntIncr_A	8913551	197135	0	0
CntNoWrap_A	8913551	8219808	0	0
DetectStDropOut_A	8913551	0	0	0
DetectedOut_A	8913551	64578	0	0
DetectedPulseOut_A	8913551	57	0	0
DisabledIdleSt_A	8913551	7455108	0	0
DisabledNoDetection_A	8913551	7457495	0	0
EnterDebounceSt_A	8913551	60	0	0
EnterDetectSt_A	8913551	57	0	0
EnterStableSt_A	8913551	57	0	0
PulseIsPulse_A	8913551	57	0	0
StayInStableSt	8913551	64490	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	117	0	0
T7	209575	7	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	6	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	2	0	0
T47	0	4	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	2	0	0
T153	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	197135	0	0
T7	209575	58536	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	139	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	140	0	0
T41	0	79	0	0
T42	0	25	0	0
T45	0	10	0	0
T47	0	38	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	32	0	0
T153	0	90	0	0
T169	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219808	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	64578	0	0
T7	209575	191	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	262	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	167	0	0
T41	0	59	0	0
T42	0	19	0	0
T45	0	49	0	0
T47	0	54	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	38	0	0
T153	0	113	0	0
T169	0	186	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	57	0	0
T7	209575	3	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7455108	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7457495	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	60	0	0
T7	209575	4	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	57	0	0
T7	209575	3	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	57	0	0
T7	209575	3	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	57	0	0
T7	209575	3	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	64490	0	0
T7	209575	187	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	257	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	165	0	0
T41	0	57	0	0
T42	0	18	0	0
T45	0	47	0	0
T47	0	51	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T150	0	36	0	0
T153	0	111	0	0
T169	0	184	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	25	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T137	0	1	0	0
T143	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T170	0	1	0	0
T171	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T13
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T13
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T40,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T40,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T40,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T45
1	0	Covered	T5,T1,T13
1	1	Covered	T40,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T42,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T42,T43
0	1	Covered	T43,T170,T144
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T42,T43
1	-	Covered	T43,T170,T144

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T42,T43
DetectSt	168	Covered	T40,T42,T43
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T40,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T42,T43
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T42,T43
IdleSt->DebounceSt	148	Covered	T40,T42,T43
StableSt->IdleSt	206	Covered	T40,T42,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T42,T43
0	1	Covered	T40,T42,T43
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T42,T43
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T42,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T42,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T43,T170
StableSt	-	-	-	-	-	-	0	Covered	T40,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	55	0	0
CntIncr_A	8913551	63775	0	0
CntNoWrap_A	8913551	8219870	0	0
DetectStDropOut_A	8913551	0	0	0
DetectedOut_A	8913551	2052	0	0
DetectedPulseOut_A	8913551	27	0	0
DisabledIdleSt_A	8913551	7654507	0	0
DisabledNoDetection_A	8913551	7656898	0	0
EnterDebounceSt_A	8913551	28	0	0
EnterDetectSt_A	8913551	27	0	0
EnterStableSt_A	8913551	27	0	0
PulseIsPulse_A	8913551	27	0	0
StayInStableSt	8913551	2012	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	6609	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	55	0	0
T40	3631	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	2	0	0
T122	0	2	0	0
T144	0	2	0	0
T150	10777	0	0	0
T156	0	2	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	2	0	0
T172	0	2	0	0
T173	800	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	63775	0	0
T40	3631	140	0	0
T42	0	25	0	0
T43	0	26	0	0
T44	0	39	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	58	0	0
T122	0	86	0	0
T144	0	89	0	0
T150	10777	0	0	0
T156	0	33	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	14	0	0
T172	0	23	0	0
T173	800	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219870	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	2052	0	0
T40	3631	319	0	0
T42	0	18	0	0
T43	0	44	0	0
T44	0	44	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	39	0	0
T122	0	364	0	0
T144	0	210	0	0
T150	10777	0	0	0
T156	0	42	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	43	0	0
T172	0	38	0	0
T173	800	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	27	0	0
T40	3631	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T144	0	1	0	0
T150	10777	0	0	0
T156	0	1	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T173	800	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7654507	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7656898	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	28	0	0
T40	3631	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T144	0	1	0	0
T150	10777	0	0	0
T156	0	1	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T173	800	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	27	0	0
T40	3631	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T144	0	1	0	0
T150	10777	0	0	0
T156	0	1	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T173	800	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	27	0	0
T40	3631	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T144	0	1	0	0
T150	10777	0	0	0
T156	0	1	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T173	800	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	27	0	0
T40	3631	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T144	0	1	0	0
T150	10777	0	0	0
T156	0	1	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	1	0	0
T172	0	1	0	0
T173	800	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	2012	0	0
T40	3631	315	0	0
T42	0	17	0	0
T43	0	43	0	0
T44	0	42	0	0
T46	1154	0	0	0
T74	591	0	0	0
T121	0	38	0	0
T122	0	362	0	0
T144	0	209	0	0
T150	10777	0	0	0
T156	0	41	0	0
T160	426	0	0	0
T161	1376	0	0	0
T162	632	0	0	0
T163	34057	0	0	0
T164	422	0	0	0
T170	0	42	0	0
T172	0	36	0	0
T173	800	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6609	0	0
T1	1047	10	0	0
T3	0	25	0	0
T5	426	3	0	0
T6	688	0	0	0
T7	0	63	0	0
T13	489	5	0	0
T14	2715	8	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	3	0	0
T18	410	0	0	0
T19	407	0	0	0
T58	0	1	0	0
T59	0	6	0	0
T60	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	13	0	0
T43	2590	1	0	0
T85	0	1	0	0
T121	0	1	0	0
T123	0	1	0	0
T144	0	1	0	0
T147	0	1	0	0
T154	6949	0	0	0
T156	0	1	0	0
T170	0	1	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	8466	0	0	0
T177	422	0	0	0
T178	5168	0	0	0
T179	17855	0	0	0
T180	502	0	0	0
T181	42401	0	0	0
T182	425	0	0	0
T183	10727	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T4,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T4,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T13,T14
1	1	Covered	T2,T4,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T21,T88,T40
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T7
1	-	Covered	T21,T88,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T7
DetectSt	168	Covered	T2,T4,T7
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T7
DebounceSt->IdleSt	163	Covered	T4,T21,T184
DetectSt->IdleSt	186	Covered	T86
DetectSt->StableSt	191	Covered	T2,T4,T7
IdleSt->DebounceSt	148	Covered	T2,T4,T7
StableSt->IdleSt	206	Covered	T7,T21,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T7
IdleSt	0	-	-	-	-	-	-	Covered	T5,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T21,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	1	-	-	Covered	T86
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T88,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	144	0	0
CntIncr_A	8913551	265671	0	0
CntNoWrap_A	8913551	8219781	0	0
DetectStDropOut_A	8913551	1	0	0
DetectedOut_A	8913551	355982	0	0
DetectedPulseOut_A	8913551	65	0	0
DisabledIdleSt_A	8913551	7454083	0	0
DisabledNoDetection_A	8913551	7456459	0	0
EnterDebounceSt_A	8913551	79	0	0
EnterDetectSt_A	8913551	66	0	0
EnterStableSt_A	8913551	65	0	0
PulseIsPulse_A	8913551	65	0	0
StayInStableSt	8913551	355882	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	144	0	0
T2	646	2	0	0
T3	11372	0	0	0
T4	167460	3	0	0
T7	209575	2	0	0
T21	0	7	0	0
T26	503	0	0	0
T40	0	6	0	0
T42	0	2	0	0
T45	0	2	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	6	0	0
T141	0	2	0	0
T184	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	265671	0	0
T2	646	74	0	0
T3	11372	0	0	0
T4	167460	102270	0	0
T7	209575	29212	0	0
T21	0	136	0	0
T26	503	0	0	0
T40	0	212	0	0
T42	0	25	0	0
T45	0	10	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	198	0	0
T141	0	19	0	0
T184	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219781	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1	0	0
T86	31731	1	0	0
T185	637	0	0	0
T186	1029	0	0	0
T187	1326	0	0	0
T188	535	0	0	0
T189	422	0	0	0
T190	530	0	0	0
T191	138640	0	0	0
T192	1007	0	0	0
T193	1330	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	355982	0	0
T2	646	163	0	0
T3	11372	0	0	0
T4	167460	42	0	0
T7	209575	160896	0	0
T21	0	100	0	0
T26	503	0	0	0
T40	0	350	0	0
T42	0	18	0	0
T45	0	49	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	129	0	0
T116	0	43	0	0
T141	0	68	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	65	0	0
T2	646	1	0	0
T3	11372	0	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T21	0	3	0	0
T26	503	0	0	0
T40	0	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	3	0	0
T116	0	1	0	0
T141	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7454083	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7456459	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	79	0	0
T2	646	1	0	0
T3	11372	0	0	0
T4	167460	2	0	0
T7	209575	1	0	0
T21	0	4	0	0
T26	503	0	0	0
T40	0	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	3	0	0
T141	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	66	0	0
T2	646	1	0	0
T3	11372	0	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T21	0	3	0	0
T26	503	0	0	0
T40	0	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	3	0	0
T116	0	1	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	65	0	0
T2	646	1	0	0
T3	11372	0	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T21	0	3	0	0
T26	503	0	0	0
T40	0	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	3	0	0
T116	0	1	0	0
T141	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	65	0	0
T2	646	1	0	0
T3	11372	0	0	0
T4	167460	1	0	0
T7	209575	1	0	0
T21	0	3	0	0
T26	503	0	0	0
T40	0	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	3	0	0
T116	0	1	0	0
T141	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	355882	0	0
T2	646	161	0	0
T3	11372	0	0	0
T4	167460	40	0	0
T7	209575	160894	0	0
T21	0	96	0	0
T26	503	0	0	0
T40	0	345	0	0
T42	0	17	0	0
T45	0	47	0	0
T48	660	0	0	0
T57	402	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T88	0	125	0	0
T116	0	41	0	0
T141	0	66	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	29	0	0
T21	72090	2	0	0
T37	23992	0	0	0
T40	0	1	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T88	0	2	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T131	0	1	0	0
T137	0	1	0	0
T154	0	1	0	0
T170	0	2	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T13,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T40,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T40,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T5,T13,T14
1	1	Covered	T4,T40,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T40,T41
0	1	Covered	T142
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T40,T41
0	1	Covered	T4,T40,T41
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T40,T41
1	-	Covered	T4,T40,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T40,T41
DetectSt	168	Covered	T4,T40,T41
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T40,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T40,T41
DebounceSt->IdleSt	163	Covered	T78
DetectSt->IdleSt	186	Covered	T142
DetectSt->StableSt	191	Covered	T4,T40,T41
IdleSt->DebounceSt	148	Covered	T4,T40,T41
StableSt->IdleSt	206	Covered	T4,T40,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T40,T41
0	1	Covered	T4,T40,T41
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T40,T41
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T40,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T40,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T40,T41
DetectSt	-	-	-	-	1	-	-	Covered	T142
DetectSt	-	-	-	-	0	1	-	Covered	T4,T40,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T40,T41
StableSt	-	-	-	-	-	-	0	Covered	T4,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	83	0	0
CntIncr_A	8913551	115795	0	0
CntNoWrap_A	8913551	8219842	0	0
DetectStDropOut_A	8913551	1	0	0
DetectedOut_A	8913551	56667	0	0
DetectedPulseOut_A	8913551	40	0	0
DisabledIdleSt_A	8913551	7454062	0	0
DisabledNoDetection_A	8913551	7456440	0	0
EnterDebounceSt_A	8913551	42	0	0
EnterDetectSt_A	8913551	41	0	0
EnterStableSt_A	8913551	40	0	0
PulseIsPulse_A	8913551	40	0	0
StayInStableSt	8913551	56607	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	6353	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	83	0	0
T4	167460	2	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	2	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	2	0	0
T142	0	4	0	0
T154	0	2	0	0
T170	0	4	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	115795	0	0
T4	167460	51135	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	72	0	0
T41	0	158	0	0
T42	0	25	0	0
T47	0	19	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	88	0	0
T142	0	128	0	0
T154	0	39	0	0
T170	0	28	0	0
T184	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219842	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1	0	0
T142	6871	1	0	0
T195	1362	0	0	0
T196	522	0	0	0
T197	2332	0	0	0
T198	18987	0	0	0
T199	125818	0	0	0
T200	506	0	0	0
T201	526	0	0	0
T202	532	0	0	0
T203	11777	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	56667	0	0
T4	167460	51179	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	164	0	0
T41	0	159	0	0
T42	0	18	0	0
T47	0	119	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	131	0	0
T142	0	104	0	0
T154	0	91	0	0
T170	0	96	0	0
T184	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	40	0	0
T4	167460	1	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	1	0	0
T142	0	1	0	0
T154	0	1	0	0
T170	0	2	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7454062	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7456440	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	42	0	0
T4	167460	1	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	1	0	0
T142	0	2	0	0
T154	0	1	0	0
T170	0	2	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	41	0	0
T4	167460	1	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	1	0	0
T142	0	2	0	0
T154	0	1	0	0
T170	0	2	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	40	0	0
T4	167460	1	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	1	0	0
T142	0	1	0	0
T154	0	1	0	0
T170	0	2	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	40	0	0
T4	167460	1	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	1	0	0
T142	0	1	0	0
T154	0	1	0	0
T170	0	2	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	56607	0	0
T4	167460	51178	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	163	0	0
T41	0	156	0	0
T42	0	17	0	0
T47	0	117	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	130	0	0
T142	0	103	0	0
T154	0	90	0	0
T170	0	93	0	0
T184	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6353	0	0
T1	1047	0	0	0
T3	0	33	0	0
T4	0	1	0	0
T5	426	3	0	0
T6	688	0	0	0
T7	0	53	0	0
T13	489	6	0	0
T14	2715	8	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	3	0	0
T18	410	0	0	0
T19	407	0	0	0
T58	0	3	0	0
T59	0	8	0	0
T60	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	19	0	0
T4	167460	1	0	0
T7	209575	0	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T123	0	1	0	0
T131	0	1	0	0
T142	0	1	0	0
T147	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T170	0	1	0	0