Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T13,T14
1	1	Covered	T4,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T8
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T8
0	1	Covered	T7,T21,T45
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T8
1	-	Covered	T7,T21,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T8
DetectSt	168	Covered	T4,T7,T8
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T8
DebounceSt->IdleSt	163	Covered	T4,T116,T144
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T7,T8
IdleSt->DebounceSt	148	Covered	T4,T7,T8
StableSt->IdleSt	206	Covered	T7,T9,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T8
0	1	Covered	T4,T7,T8
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T116,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T8
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T21,T45
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	155	0	0
CntIncr_A	8913551	202666	0	0
CntNoWrap_A	8913551	8219770	0	0
DetectStDropOut_A	8913551	0	0	0
DetectedOut_A	8913551	117558	0	0
DetectedPulseOut_A	8913551	75	0	0
DisabledIdleSt_A	8913551	7668667	0	0
DisabledNoDetection_A	8913551	7671041	0	0
EnterDebounceSt_A	8913551	81	0	0
EnterDetectSt_A	8913551	75	0	0
EnterStableSt_A	8913551	75	0	0
PulseIsPulse_A	8913551	75	0	0
StayInStableSt	8913551	117443	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	155	0	0
T4	167460	3	0	0
T7	209575	8	0	0
T8	587	2	0	0
T9	0	2	0	0
T12	0	2	0	0
T21	0	8	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	6	0	0
T45	0	4	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	2	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	202666	0	0
T4	167460	102270	0	0
T7	209575	58536	0	0
T8	587	52	0	0
T9	0	68	0	0
T12	0	54	0	0
T21	0	155	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	212	0	0
T45	0	20	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	26	0	0
T88	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219770	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	117558	0	0
T4	167460	51177	0	0
T7	209575	60786	0	0
T8	587	42	0	0
T9	0	37	0	0
T12	0	40	0	0
T21	0	401	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	324	0	0
T45	0	46	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	93	0	0
T88	0	416	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	75	0	0
T4	167460	1	0	0
T7	209575	4	0	0
T8	587	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	3	0	0
T45	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7668667	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7671041	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	81	0	0
T4	167460	2	0	0
T7	209575	4	0	0
T8	587	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	3	0	0
T45	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	75	0	0
T4	167460	1	0	0
T7	209575	4	0	0
T8	587	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	3	0	0
T45	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	75	0	0
T4	167460	1	0	0
T7	209575	4	0	0
T8	587	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	3	0	0
T45	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	75	0	0
T4	167460	1	0	0
T7	209575	4	0	0
T8	587	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	3	0	0
T45	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	1	0	0
T88	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	117443	0	0
T4	167460	51175	0	0
T7	209575	60780	0	0
T8	587	40	0	0
T9	0	35	0	0
T12	0	38	0	0
T21	0	395	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	320	0	0
T45	0	43	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T73	0	91	0	0
T88	0	414	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	34	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	1	0	0
T131	0	1	0	0
T142	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T13,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T21,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T21,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T21,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T5,T13,T14
1	1	Covered	T7,T21,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T40
0	1	Covered	T7,T21,T116
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T21,T40
1	-	Covered	T7,T21,T116

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T21,T40
DetectSt	168	Covered	T7,T21,T40
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T21,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T21,T40
DebounceSt->IdleSt	163	Covered	T122,T204,T174
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T21,T40
IdleSt->DebounceSt	148	Covered	T7,T21,T40
StableSt->IdleSt	206	Covered	T7,T21,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T21,T40
0	1	Covered	T7,T21,T40
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T21,T40
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T21,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T21,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T122,T204,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T21,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T21,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T21,T42
StableSt	-	-	-	-	-	-	0	Covered	T7,T21,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	64	0	0
CntIncr_A	8913551	64206	0	0
CntNoWrap_A	8913551	8219861	0	0
DetectStDropOut_A	8913551	0	0	0
DetectedOut_A	8913551	2695	0	0
DetectedPulseOut_A	8913551	30	0	0
DisabledIdleSt_A	8913551	7824375	0	0
DisabledNoDetection_A	8913551	7826758	0	0
EnterDebounceSt_A	8913551	34	0	0
EnterDetectSt_A	8913551	30	0	0
EnterStableSt_A	8913551	30	0	0
PulseIsPulse_A	8913551	30	0	0
StayInStableSt	8913551	2649	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	6237	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	64	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	4	0	0
T131	0	2	0	0
T132	0	2	0	0
T137	0	2	0	0
T142	0	2	0	0
T144	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	64206	0	0
T7	209575	56	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	51	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	68	0	0
T42	0	25	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	80	0	0
T131	0	88	0	0
T132	0	98	0	0
T137	0	84	0	0
T142	0	33	0	0
T144	0	178	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219861	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	2695	0	0
T7	209575	99	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	94	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	41	0	0
T42	0	18	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	81	0	0
T131	0	129	0	0
T132	0	43	0	0
T137	0	252	0	0
T142	0	37	0	0
T144	0	383	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	30	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T137	0	1	0	0
T142	0	1	0	0
T144	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7824375	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7826758	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	34	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T137	0	1	0	0
T142	0	1	0	0
T144	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	30	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T137	0	1	0	0
T142	0	1	0	0
T144	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	30	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T137	0	1	0	0
T142	0	1	0	0
T144	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	30	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T137	0	1	0	0
T142	0	1	0	0
T144	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	2649	0	0
T7	209575	98	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	91	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	39	0	0
T42	0	17	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	78	0	0
T131	0	127	0	0
T132	0	41	0	0
T137	0	251	0	0
T142	0	35	0	0
T144	0	380	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6237	0	0
T1	1047	0	0	0
T3	0	24	0	0
T4	0	1	0	0
T5	426	2	0	0
T6	688	0	0	0
T7	0	49	0	0
T13	489	7	0	0
T14	2715	8	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	1	0	0
T18	410	0	0	0
T19	407	0	0	0
T58	0	2	0	0
T59	0	8	0	0
T60	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	13	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T116	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T137	0	1	0	0
T144	0	1	0	0
T148	0	1	0	0
T205	0	2	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T7,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T5,T13,T14
1	1	Covered	T4,T7,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T40
0	1	Covered	T85,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T40
0	1	Covered	T7,T40,T46
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T40
1	-	Covered	T7,T40,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T40
DetectSt	168	Covered	T4,T7,T40
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T7,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T40
DebounceSt->IdleSt	163	Covered	T7,T184,T118
DetectSt->IdleSt	186	Covered	T85,T87
DetectSt->StableSt	191	Covered	T4,T7,T40
IdleSt->DebounceSt	148	Covered	T4,T7,T40
StableSt->IdleSt	206	Covered	T7,T40,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T40
0	1	Covered	T4,T7,T40
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T40
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T184,T131
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T40
DetectSt	-	-	-	-	1	-	-	Covered	T85,T87
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T40,T46
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	124	0	0
CntIncr_A	8913551	347060	0	0
CntNoWrap_A	8913551	8219801	0	0
DetectStDropOut_A	8913551	2	0	0
DetectedOut_A	8913551	69610	0	0
DetectedPulseOut_A	8913551	57	0	0
DisabledIdleSt_A	8913551	7285801	0	0
DisabledNoDetection_A	8913551	7288187	0	0
EnterDebounceSt_A	8913551	68	0	0
EnterDetectSt_A	8913551	59	0	0
EnterStableSt_A	8913551	57	0	0
PulseIsPulse_A	8913551	57	0	0
StayInStableSt	8913551	69530	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	124	0	0
T4	167460	2	0	0
T7	209575	7	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	4	0	0
T42	0	2	0	0
T46	0	6	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	2	0	0
T153	0	2	0	0
T154	0	4	0	0
T169	0	4	0	0
T184	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	347060	0	0
T4	167460	51135	0	0
T7	209575	87692	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	140	0	0
T42	0	25	0	0
T46	0	231	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	19	0	0
T153	0	90	0	0
T154	0	78	0	0
T169	0	148	0	0
T184	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219801	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	2	0	0
T85	1063	1	0	0
T87	0	1	0	0
T207	509	0	0	0
T208	1206	0	0	0
T209	9594	0	0	0
T210	446	0	0	0
T211	899	0	0	0
T212	2632	0	0	0
T213	489	0	0	0
T214	526	0	0	0
T215	14279	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	69610	0	0
T4	167460	41	0	0
T7	209575	184	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	160	0	0
T42	0	19	0	0
T46	0	223	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	42	0	0
T142	0	313	0	0
T153	0	41	0	0
T154	0	215	0	0
T169	0	218	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	57	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T46	0	3	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	1	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T169	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7285801	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7288187	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	68	0	0
T4	167460	1	0	0
T7	209575	4	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T46	0	3	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T169	0	2	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	59	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T46	0	3	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	1	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T169	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	57	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T46	0	3	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	1	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T169	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	57	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T46	0	3	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	1	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T169	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	69530	0	0
T4	167460	39	0	0
T7	209575	180	0	0
T8	587	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	157	0	0
T42	0	18	0	0
T46	0	219	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T141	0	40	0	0
T142	0	312	0	0
T153	0	39	0	0
T154	0	212	0	0
T169	0	215	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	33	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T40	0	1	0	0
T46	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	1	0	0
T137	0	2	0	0
T142	0	1	0	0
T144	0	1	0	0
T154	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T13,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T21,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T21,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T21,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T5,T13,T14
1	1	Covered	T7,T21,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T39
0	1	Covered	T156
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T39
0	1	Covered	T21,T88,T41
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T21,T39
1	-	Covered	T21,T88,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T21,T39
DetectSt	168	Covered	T7,T21,T39
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T21,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T21,T39
DebounceSt->IdleSt	163	Covered	T216,T78,T86
DetectSt->IdleSt	186	Covered	T156
DetectSt->StableSt	191	Covered	T7,T21,T39
IdleSt->DebounceSt	148	Covered	T7,T21,T39
StableSt->IdleSt	206	Covered	T7,T21,T88

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T21,T39
0	1	Covered	T7,T21,T39
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T21,T39
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T21,T39
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T21,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T216,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T21,T39
DetectSt	-	-	-	-	1	-	-	Covered	T156
DetectSt	-	-	-	-	0	1	-	Covered	T7,T21,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T88,T41
StableSt	-	-	-	-	-	-	0	Covered	T7,T21,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	93	0	0
CntIncr_A	8913551	127461	0	0
CntNoWrap_A	8913551	8219832	0	0
DetectStDropOut_A	8913551	1	0	0
DetectedOut_A	8913551	6389	0	0
DetectedPulseOut_A	8913551	44	0	0
DisabledIdleSt_A	8913551	7652171	0	0
DisabledNoDetection_A	8913551	7654544	0	0
EnterDebounceSt_A	8913551	48	0	0
EnterDetectSt_A	8913551	45	0	0
EnterStableSt_A	8913551	44	0	0
PulseIsPulse_A	8913551	44	0	0
StayInStableSt	8913551	6321	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	6258	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	93	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T169	0	2	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	127461	0	0
T7	209575	56	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	32	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	38	0	0
T40	0	72	0	0
T41	0	158	0	0
T42	0	25	0	0
T43	0	26	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	66	0	0
T169	0	74	0	0
T184	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219832	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1	0	0
T156	770	1	0	0
T217	402	0	0	0
T218	887	0	0	0
T219	402	0	0	0
T220	425	0	0	0
T221	684	0	0	0
T222	421	0	0	0
T223	762	0	0	0
T224	13303	0	0	0
T225	19600	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6389	0	0
T7	209575	40	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	161	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	195	0	0
T40	0	395	0	0
T41	0	48	0	0
T42	0	18	0	0
T43	0	91	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	111	0	0
T169	0	42	0	0
T184	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	44	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	1	0	0
T169	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7652171	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7654544	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	48	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	1	0	0
T169	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	45	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	1	0	0
T169	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	44	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	1	0	0
T169	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	44	0	0
T7	209575	1	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	1	0	0
T169	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6321	0	0
T7	209575	38	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	158	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	193	0	0
T40	0	393	0	0
T41	0	46	0	0
T42	0	17	0	0
T43	0	90	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	110	0	0
T169	0	41	0	0
T184	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6258	0	0
T1	1047	0	0	0
T3	0	37	0	0
T5	426	2	0	0
T6	688	0	0	0
T7	0	50	0	0
T13	489	8	0	0
T14	2715	11	0	0
T15	663	0	0	0
T16	705	0	0	0
T17	422	3	0	0
T18	410	0	0	0
T19	407	0	0	0
T26	0	8	0	0
T58	0	3	0	0
T59	0	7	0	0
T60	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	19	0	0
T21	72090	1	0	0
T37	23992	0	0	0
T41	0	2	0	0
T43	0	1	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T88	0	1	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T122	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T7,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T21
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T7,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T21
0	1	Covered	T7,T21,T45
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T21
1	-	Covered	T7,T21,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T21
DetectSt	168	Covered	T4,T7,T21
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T21
DebounceSt->IdleSt	163	Covered	T153,T137,T165
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T7,T21
IdleSt->DebounceSt	148	Covered	T4,T7,T21
StableSt->IdleSt	206	Covered	T7,T21,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T21
0	1	Covered	T4,T7,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T21
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T153,T137,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T21,T45
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	108	0	0
CntIncr_A	8913551	254909	0	0
CntNoWrap_A	8913551	8219817	0	0
DetectStDropOut_A	8913551	0	0	0
DetectedOut_A	8913551	264602	0	0
DetectedPulseOut_A	8913551	51	0	0
DisabledIdleSt_A	8913551	7409609	0	0
DisabledNoDetection_A	8913551	7412003	0	0
EnterDebounceSt_A	8913551	57	0	0
EnterDetectSt_A	8913551	51	0	0
EnterStableSt_A	8913551	51	0	0
PulseIsPulse_A	8913551	51	0	0
StayInStableSt	8913551	264528	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	108	0	0
T4	167460	2	0	0
T7	209575	6	0	0
T8	587	0	0	0
T21	0	6	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	2	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	4	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	3	0	0
T167	0	2	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	254909	0	0
T4	167460	51135	0	0
T7	209575	87636	0	0
T8	587	0	0	0
T21	0	67	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	25	0	0
T45	0	20	0	0
T46	0	77	0	0
T47	0	38	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	133	0	0
T167	0	28	0	0
T184	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219817	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	264602	0	0
T4	167460	42	0	0
T7	209575	5600	0	0
T8	587	0	0	0
T21	0	203	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	18	0	0
T45	0	47	0	0
T46	0	41	0	0
T47	0	87	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	123	0	0
T167	0	29	0	0
T184	0	110	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	51	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	1	0	0
T167	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7409609	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7412003	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	57	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	2	0	0
T167	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	51	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	1	0	0
T167	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	51	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	1	0	0
T167	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	51	0	0
T4	167460	1	0	0
T7	209575	3	0	0
T8	587	0	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	1	0	0
T167	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	264528	0	0
T4	167460	40	0	0
T7	209575	5596	0	0
T8	587	0	0	0
T21	0	198	0	0
T26	503	0	0	0
T27	525	0	0	0
T42	0	17	0	0
T45	0	44	0	0
T46	0	39	0	0
T47	0	85	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T153	0	121	0	0
T167	0	27	0	0
T184	0	108	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	27	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T131	0	1	0	0
T137	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T21,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T21,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T21,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T5,T1,T6
1	1	Covered	T7,T21,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T39
0	1	Covered	T7,T45,T88
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T21,T39
1	-	Covered	T7,T45,T88

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T21,T39
DetectSt	168	Covered	T7,T21,T39
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T21,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T21,T39
DebounceSt->IdleSt	163	Covered	T116,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T21,T39
IdleSt->DebounceSt	148	Covered	T7,T21,T39
StableSt->IdleSt	206	Covered	T7,T45,T88

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T21,T39
0	1	Covered	T7,T21,T39
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T21,T39
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T21,T39
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T21,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T116
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T21,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T21,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T88
StableSt	-	-	-	-	-	-	0	Covered	T7,T21,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	78	0	0
CntIncr_A	8913551	111428	0	0
CntNoWrap_A	8913551	8219847	0	0
DetectStDropOut_A	8913551	0	0	0
DetectedOut_A	8913551	46560	0	0
DetectedPulseOut_A	8913551	38	0	0
DisabledIdleSt_A	8913551	7788278	0	0
DisabledNoDetection_A	8913551	7790657	0	0
EnterDebounceSt_A	8913551	40	0	0
EnterDetectSt_A	8913551	38	0	0
EnterStableSt_A	8913551	38	0	0
PulseIsPulse_A	8913551	38	0	0
StayInStableSt	8913551	46499	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8913551	6953	0	0
gen_low_level_sva.LowLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	78	0	0
T7	209575	4	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	4	0	0
T116	0	3	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	111428	0	0
T7	209575	58424	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	69	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	38	0	0
T40	0	72	0	0
T42	0	25	0	0
T44	0	39	0	0
T45	0	10	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	132	0	0
T116	0	80	0	0
T153	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219847	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	46560	0	0
T7	209575	43916	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	46	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	115	0	0
T40	0	278	0	0
T42	0	18	0	0
T44	0	44	0	0
T45	0	51	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	152	0	0
T116	0	53	0	0
T153	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	38	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T116	0	1	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7788278	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7790657	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	40	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T116	0	2	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	38	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T116	0	1	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	38	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T116	0	1	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	38	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	2	0	0
T116	0	1	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	46499	0	0
T7	209575	43914	0	0
T8	587	0	0	0
T9	5748	0	0	0
T21	0	44	0	0
T26	503	0	0	0
T27	525	0	0	0
T39	0	113	0	0
T40	0	276	0	0
T42	0	17	0	0
T44	0	42	0	0
T45	0	50	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T88	0	149	0	0
T116	0	51	0	0
T153	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	6953	0	0
T1	1047	10	0	0
T3	0	26	0	0
T5	426	2	0	0
T6	688	3	0	0
T7	0	67	0	0
T13	489	5	0	0
T14	2715	8	0	0
T15	663	3	0	0
T16	705	3	0	0
T17	422	1	0	0
T18	410	0	0	0
T19	407	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	14	0	0
T7	209575	2	0	0
T8	587	0	0	0
T9	5748	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T45	0	1	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T85	0	1	0	0
T88	0	1	0	0
T122	0	2	0	0
T123	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T157	0	1	0	0
T216	0	1	0	0