Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T54,T55,T56
1	0	Covered	T33,T227,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
1	0	Covered	T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T11
1	-	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T11
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T42,T228,T176
DetectSt->IdleSt	186	Covered	T54,T55,T56
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T10,T11
StableSt->IdleSt	206	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T3,T10,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T228,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T54,T55,T56
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	3295	0	0
CntIncr_A	8913551	120710	0	0
CntNoWrap_A	8913551	8216630	0	0
DetectStDropOut_A	8913551	458	0	0
DetectedOut_A	8913551	95380	0	0
DetectedPulseOut_A	8913551	1019	0	0
DisabledIdleSt_A	8913551	7715936	0	0
DisabledNoDetection_A	8913551	7718180	0	0
EnterDebounceSt_A	8913551	1655	0	0
EnterDetectSt_A	8913551	1640	0	0
EnterStableSt_A	8913551	1019	0	0
PulseIsPulse_A	8913551	1019	0	0
StayInStableSt	8913551	94261	0	0
gen_high_event_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	891	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	3295	0	0
T3	11372	42	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	48	0	0
T11	0	56	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	34	0	0
T34	0	14	0	0
T37	0	14	0	0
T48	660	0	0	0
T53	0	48	0	0
T54	0	8	0	0
T55	0	44	0	0
T56	0	48	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	120710	0	0
T3	11372	1323	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	1176	0	0
T11	0	2212	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1207	0	0
T34	0	525	0	0
T37	0	413	0	0
T48	660	0	0	0
T53	0	1680	0	0
T54	0	182	0	0
T55	0	1103	0	0
T56	0	1012	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8216630	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	458	0	0
T33	0	2	0	0
T34	13020	0	0	0
T39	714	0	0	0
T42	0	1	0	0
T54	4929	4	0	0
T55	0	22	0	0
T56	0	24	0	0
T92	725	0	0	0
T93	0	16	0	0
T95	0	26	0	0
T229	0	14	0	0
T230	0	12	0	0
T231	0	18	0	0
T232	452	0	0	0
T233	501	0	0	0
T234	490	0	0	0
T235	435	0	0	0
T236	491	0	0	0
T237	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	95380	0	0
T3	11372	1014	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	1419	0	0
T11	0	1868	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1154	0	0
T34	0	404	0	0
T37	0	57	0	0
T48	660	0	0	0
T53	0	1542	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T110	0	83	0	0
T111	0	2914	0	0
T112	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1019	0	0
T3	11372	21	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	24	0	0
T11	0	28	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	17	0	0
T34	0	7	0	0
T37	0	7	0	0
T48	660	0	0	0
T53	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T110	0	1	0	0
T111	0	29	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7715936	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7718180	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1655	0	0
T3	11372	21	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	24	0	0
T11	0	28	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	17	0	0
T34	0	7	0	0
T37	0	7	0	0
T48	660	0	0	0
T53	0	24	0	0
T54	0	4	0	0
T55	0	22	0	0
T56	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1640	0	0
T3	11372	21	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	24	0	0
T11	0	28	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	17	0	0
T34	0	7	0	0
T37	0	7	0	0
T48	660	0	0	0
T53	0	24	0	0
T54	0	4	0	0
T55	0	22	0	0
T56	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1019	0	0
T3	11372	21	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	24	0	0
T11	0	28	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	17	0	0
T34	0	7	0	0
T37	0	7	0	0
T48	660	0	0	0
T53	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T110	0	1	0	0
T111	0	29	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1019	0	0
T3	11372	21	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	24	0	0
T11	0	28	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	17	0	0
T34	0	7	0	0
T37	0	7	0	0
T48	660	0	0	0
T53	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T110	0	1	0	0
T111	0	29	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	94261	0	0
T3	11372	992	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	1392	0	0
T11	0	1838	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1136	0	0
T34	0	396	0	0
T37	0	50	0	0
T48	660	0	0	0
T53	0	1518	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T110	0	81	0	0
T111	0	2882	0	0
T112	0	77	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	891	0	0
T3	11372	20	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	21	0	0
T11	0	26	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	16	0	0
T34	0	6	0	0
T37	0	7	0	0
T42	0	5	0	0
T48	660	0	0	0
T53	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	26	0	0
T115	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T9
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T3,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T14,T3,T7
1	1	Covered	T3,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T21,T94,T96
1	0	Covered	T42,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T3,T7,T9
1	0	Covered	T42,T79,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T9
1	-	Covered	T3,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T9
DetectSt	168	Covered	T3,T7,T9
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T3,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T9
DebounceSt->IdleSt	163	Covered	T7,T49,T52
DetectSt->IdleSt	186	Covered	T21,T94,T42
DetectSt->StableSt	191	Covered	T3,T7,T9
IdleSt->DebounceSt	148	Covered	T3,T7,T9
StableSt->IdleSt	206	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T9
0	1	Covered	T3,T7,T9
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T9
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T49,T52
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T21,T94,T42
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	987	0	0
CntIncr_A	8913551	50649	0	0
CntNoWrap_A	8913551	8218938	0	0
DetectStDropOut_A	8913551	74	0	0
DetectedOut_A	8913551	15038	0	0
DetectedPulseOut_A	8913551	370	0	0
DisabledIdleSt_A	8913551	7858519	0	0
DisabledNoDetection_A	8913551	7860194	0	0
EnterDebounceSt_A	8913551	544	0	0
EnterDetectSt_A	8913551	449	0	0
EnterStableSt_A	8913551	370	0	0
PulseIsPulse_A	8913551	370	0	0
StayInStableSt	8913551	14629	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	326	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	987	0	0
T3	11372	2	0	0
T4	167460	0	0	0
T7	209575	4	0	0
T9	0	4	0	0
T10	0	6	0	0
T11	0	4	0	0
T21	0	8	0	0
T26	503	0	0	0
T27	525	0	0	0
T34	0	2	0	0
T48	660	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	8	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	50649	0	0
T3	11372	73	0	0
T4	167460	0	0	0
T7	209575	65	0	0
T9	0	50	0	0
T10	0	117	0	0
T11	0	180	0	0
T21	0	183	0	0
T26	503	0	0	0
T27	525	0	0	0
T34	0	81	0	0
T48	660	0	0	0
T49	0	20	0	0
T52	0	20	0	0
T53	0	236	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8218938	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	74	0	0
T21	72090	3	0	0
T37	23992	0	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T94	0	5	0	0
T96	0	2	0	0
T97	0	13	0	0
T98	0	9	0	0
T100	0	12	0	0
T101	0	5	0	0
T102	0	2	0	0
T103	0	11	0	0
T104	0	8	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	15038	0	0
T3	11372	68	0	0
T4	167460	0	0	0
T7	209575	3	0	0
T9	0	6	0	0
T10	0	218	0	0
T11	0	98	0	0
T21	0	3	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	73	0	0
T34	0	40	0	0
T38	0	72	0	0
T48	660	0	0	0
T53	0	294	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	370	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	3	0	0
T48	660	0	0	0
T53	0	4	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7858519	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7860194	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	544	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	3	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T34	0	1	0	0
T48	660	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	4	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	449	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T21	0	4	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	3	0	0
T48	660	0	0	0
T53	0	4	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	370	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	3	0	0
T48	660	0	0	0
T53	0	4	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	370	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	3	0	0
T48	660	0	0	0
T53	0	4	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	14629	0	0
T3	11372	67	0	0
T4	167460	0	0	0
T7	209575	2	0	0
T9	0	4	0	0
T10	0	215	0	0
T11	0	96	0	0
T21	0	2	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	72	0	0
T34	0	39	0	0
T38	0	69	0	0
T48	660	0	0	0
T53	0	290	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	326	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T21	0	1	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	3	0	0
T48	660	0	0	0
T53	0	4	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T54,T55,T56
1	0	Covered	T53,T42,T238

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
1	0	Covered	T78,T239

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T11
1	-	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T11
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T42,T228,T176
DetectSt->IdleSt	186	Covered	T53,T54,T55
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T10,T11
StableSt->IdleSt	206	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T3,T10,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T228,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T53,T54,T55
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	2924	0	0
CntIncr_A	8913551	116247	0	0
CntNoWrap_A	8913551	8217001	0	0
DetectStDropOut_A	8913551	362	0	0
DetectedOut_A	8913551	90697	0	0
DetectedPulseOut_A	8913551	918	0	0
DisabledIdleSt_A	8913551	7718601	0	0
DisabledNoDetection_A	8913551	7720852	0	0
EnterDebounceSt_A	8913551	1471	0	0
EnterDetectSt_A	8913551	1454	0	0
EnterStableSt_A	8913551	918	0	0
PulseIsPulse_A	8913551	918	0	0
StayInStableSt	8913551	89686	0	0
gen_high_event_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	814	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	2924	0	0
T3	11372	26	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	10	0	0
T11	0	24	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	28	0	0
T34	0	48	0	0
T37	0	52	0	0
T48	660	0	0	0
T53	0	26	0	0
T54	0	46	0	0
T55	0	28	0	0
T56	0	10	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	116247	0	0
T3	11372	1092	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	140	0	0
T11	0	648	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1302	0	0
T34	0	1296	0	0
T37	0	1534	0	0
T48	660	0	0	0
T53	0	981	0	0
T54	0	1056	0	0
T55	0	692	0	0
T56	0	206	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8217001	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	362	0	0
T34	13020	0	0	0
T39	714	0	0	0
T42	0	1	0	0
T54	4929	23	0	0
T55	0	14	0	0
T56	0	5	0	0
T92	725	0	0	0
T93	0	5	0	0
T95	0	6	0	0
T178	0	6	0	0
T230	0	5	0	0
T231	0	29	0	0
T232	452	0	0	0
T233	501	0	0	0
T234	490	0	0	0
T235	435	0	0	0
T236	491	0	0	0
T237	407	0	0	0
T238	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	90697	0	0
T3	11372	410	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	130	0	0
T11	0	354	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	829	0	0
T33	0	952	0	0
T34	0	2389	0	0
T37	0	918	0	0
T42	0	471	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	400	0	0
T227	0	970	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	918	0	0
T3	11372	13	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	5	0	0
T11	0	12	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	14	0	0
T33	0	11	0	0
T34	0	24	0	0
T37	0	26	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	8	0	0
T227	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7718601	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7720852	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1471	0	0
T3	11372	13	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	5	0	0
T11	0	12	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	14	0	0
T34	0	24	0	0
T37	0	26	0	0
T48	660	0	0	0
T53	0	13	0	0
T54	0	23	0	0
T55	0	14	0	0
T56	0	5	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1454	0	0
T3	11372	13	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	5	0	0
T11	0	12	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	14	0	0
T34	0	24	0	0
T37	0	26	0	0
T48	660	0	0	0
T53	0	13	0	0
T54	0	23	0	0
T55	0	14	0	0
T56	0	5	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	918	0	0
T3	11372	13	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	5	0	0
T11	0	12	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	14	0	0
T33	0	11	0	0
T34	0	24	0	0
T37	0	26	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	8	0	0
T227	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	918	0	0
T3	11372	13	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	5	0	0
T11	0	12	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	14	0	0
T33	0	11	0	0
T34	0	24	0	0
T37	0	26	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	8	0	0
T227	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	89686	0	0
T3	11372	396	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	125	0	0
T11	0	342	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	813	0	0
T33	0	938	0	0
T34	0	2364	0	0
T37	0	888	0	0
T42	0	466	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	391	0	0
T227	0	947	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	814	0	0
T3	11372	12	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	5	0	0
T11	0	12	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	12	0	0
T33	0	8	0	0
T34	0	23	0	0
T37	0	22	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	7	0	0
T227	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T37,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T3,T37,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T37,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T14,T3,T7
1	1	Covered	T3,T37,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T37,T34
0	1	Covered	T38,T36,T94
1	0	Covered	T42,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T37,T34
0	1	Covered	T3,T37,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T37,T34
1	-	Covered	T3,T37,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T37,T34
DetectSt	168	Covered	T3,T37,T34
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T3,T37,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T37,T34
DebounceSt->IdleSt	163	Covered	T38,T77,T42
DetectSt->IdleSt	186	Covered	T38,T36,T94
DetectSt->StableSt	191	Covered	T3,T37,T34
IdleSt->DebounceSt	148	Covered	T3,T37,T34
StableSt->IdleSt	206	Covered	T3,T37,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T37,T34
0	1	Covered	T3,T37,T34
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T37,T34
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T37,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T37,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T77,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T37,T34
DetectSt	-	-	-	-	1	-	-	Covered	T38,T36,T94
DetectSt	-	-	-	-	0	1	-	Covered	T3,T37,T34
DetectSt	-	-	-	-	0	0	-	Covered	T3,T37,T34
StableSt	-	-	-	-	-	-	1	Covered	T3,T37,T34
StableSt	-	-	-	-	-	-	0	Covered	T3,T37,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	914	0	0
CntIncr_A	8913551	54402	0	0
CntNoWrap_A	8913551	8219011	0	0
DetectStDropOut_A	8913551	76	0	0
DetectedOut_A	8913551	14112	0	0
DetectedPulseOut_A	8913551	352	0	0
DisabledIdleSt_A	8913551	7850234	0	0
DisabledNoDetection_A	8913551	7851966	0	0
EnterDebounceSt_A	8913551	482	0	0
EnterDetectSt_A	8913551	432	0	0
EnterStableSt_A	8913551	352	0	0
PulseIsPulse_A	8913551	352	0	0
StayInStableSt	8913551	13729	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	318	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	914	0	0
T3	11372	2	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T34	0	12	0	0
T37	0	6	0	0
T38	0	25	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	2	0	0
T77	0	7	0	0
T111	0	2	0	0
T113	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	54402	0	0
T3	11372	78	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	194	0	0
T33	0	52	0	0
T34	0	432	0	0
T37	0	168	0	0
T38	0	1937	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	160	0	0
T77	0	524	0	0
T111	0	83	0	0
T113	0	356	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219011	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	76	0	0
T35	23081	0	0	0
T36	0	2	0	0
T38	24896	12	0	0
T56	4716	0	0	0
T93	5227	0	0	0
T94	0	11	0	0
T96	0	11	0	0
T113	14795	0	0	0
T240	0	1	0	0
T241	0	6	0	0
T242	0	7	0	0
T243	0	1	0	0
T244	0	10	0	0
T245	0	2	0	0
T246	521	0	0	0
T247	470	0	0	0
T248	507	0	0	0
T249	489	0	0	0
T250	408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	14112	0	0
T3	11372	63	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	107	0	0
T33	0	77	0	0
T34	0	286	0	0
T37	0	107	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	23	0	0
T77	0	103	0	0
T111	0	48	0	0
T113	0	281	0	0
T227	0	76	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	352	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	6	0	0
T37	0	3	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	1	0	0
T77	0	3	0	0
T111	0	1	0	0
T113	0	4	0	0
T227	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7850234	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7851966	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	482	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	6	0	0
T37	0	3	0	0
T38	0	13	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	1	0	0
T77	0	4	0	0
T111	0	1	0	0
T113	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	432	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	6	0	0
T37	0	3	0	0
T38	0	12	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	1	0	0
T77	0	3	0	0
T111	0	1	0	0
T113	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	352	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	6	0	0
T37	0	3	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	1	0	0
T77	0	3	0	0
T111	0	1	0	0
T113	0	4	0	0
T227	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	352	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	6	0	0
T37	0	3	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	1	0	0
T77	0	3	0	0
T111	0	1	0	0
T113	0	4	0	0
T227	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	13729	0	0
T3	11372	62	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	105	0	0
T33	0	76	0	0
T34	0	280	0	0
T37	0	102	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	22	0	0
T77	0	100	0	0
T111	0	46	0	0
T113	0	277	0	0
T227	0	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	318	0	0
T3	11372	1	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	4	0	0
T37	0	1	0	0
T41	0	9	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T65	0	1	0	0
T77	0	3	0	0
T113	0	4	0	0
T163	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T10,T11,T53
1	0	Covered	T10,T11,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T37,T34
0	1	Covered	T3,T37,T34
1	0	Covered	T42,T80,T251

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T37,T34
1	-	Covered	T3,T37,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T11
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T3,T37,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T42,T228,T176
DetectSt->IdleSt	186	Covered	T10,T11,T53
DetectSt->StableSt	191	Covered	T3,T37,T34
IdleSt->DebounceSt	148	Covered	T3,T10,T11
StableSt->IdleSt	206	Covered	T3,T37,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T3,T10,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T228,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T10,T11,T53
DetectSt	-	-	-	-	0	1	-	Covered	T3,T37,T34
DetectSt	-	-	-	-	0	0	-	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	1	Covered	T3,T37,T34
StableSt	-	-	-	-	-	-	0	Covered	T3,T37,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	3027	0	0
CntIncr_A	8913551	116774	0	0
CntNoWrap_A	8913551	8216898	0	0
DetectStDropOut_A	8913551	477	0	0
DetectedOut_A	8913551	69573	0	0
DetectedPulseOut_A	8913551	857	0	0
DisabledIdleSt_A	8913551	7725940	0	0
DisabledNoDetection_A	8913551	7728191	0	0
EnterDebounceSt_A	8913551	1523	0	0
EnterDetectSt_A	8913551	1505	0	0
EnterStableSt_A	8913551	857	0	0
PulseIsPulse_A	8913551	857	0	0
StayInStableSt	8913551	68623	0	0
gen_high_event_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	747	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	3027	0	0
T3	11372	32	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	26	0	0
T11	0	50	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	64	0	0
T34	0	66	0	0
T37	0	56	0	0
T48	660	0	0	0
T53	0	46	0	0
T54	0	6	0	0
T55	0	44	0	0
T56	0	48	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	116774	0	0
T3	11372	832	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	682	0	0
T11	0	2043	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	2432	0	0
T34	0	2409	0	0
T37	0	1232	0	0
T48	660	0	0	0
T53	0	1734	0	0
T54	0	136	0	0
T55	0	1103	0	0
T56	0	1012	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8216898	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	477	0	0
T10	12917	2	0	0
T11	12597	5	0	0
T12	558	0	0	0
T31	1124	0	0	0
T33	0	5	0	0
T42	0	1	0	0
T49	448	0	0	0
T50	705	0	0	0
T53	0	12	0	0
T54	0	3	0	0
T55	0	22	0	0
T56	0	24	0	0
T69	524	0	0	0
T93	0	12	0	0
T95	0	8	0	0
T151	427	0	0	0
T252	568	0	0	0
T253	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	69573	0	0
T3	11372	976	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	3727	0	0
T34	0	1539	0	0
T37	0	1655	0	0
T42	0	463	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T80	0	7	0	0
T111	0	2247	0	0
T115	0	1183	0	0
T227	0	1033	0	0
T229	0	473	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	857	0	0
T3	11372	16	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	32	0	0
T34	0	33	0	0
T37	0	28	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T80	0	7	0	0
T111	0	29	0	0
T115	0	19	0	0
T227	0	21	0	0
T229	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7725940	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7728191	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1523	0	0
T3	11372	16	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	13	0	0
T11	0	25	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	32	0	0
T34	0	33	0	0
T37	0	28	0	0
T48	660	0	0	0
T53	0	23	0	0
T54	0	3	0	0
T55	0	22	0	0
T56	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1505	0	0
T3	11372	16	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	13	0	0
T11	0	25	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	32	0	0
T34	0	33	0	0
T37	0	28	0	0
T48	660	0	0	0
T53	0	23	0	0
T54	0	3	0	0
T55	0	22	0	0
T56	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	857	0	0
T3	11372	16	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	32	0	0
T34	0	33	0	0
T37	0	28	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T80	0	7	0	0
T111	0	29	0	0
T115	0	19	0	0
T227	0	21	0	0
T229	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	857	0	0
T3	11372	16	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	32	0	0
T34	0	33	0	0
T37	0	28	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T80	0	7	0	0
T111	0	29	0	0
T115	0	19	0	0
T227	0	21	0	0
T229	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	68623	0	0
T3	11372	959	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	3692	0	0
T34	0	1505	0	0
T37	0	1621	0	0
T42	0	458	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	2215	0	0
T115	0	1162	0	0
T227	0	1010	0	0
T229	0	468	0	0
T254	0	2211	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	747	0	0
T3	11372	15	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	29	0	0
T34	0	32	0	0
T37	0	22	0	0
T42	0	4	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	26	0	0
T115	0	17	0	0
T227	0	19	0	0
T229	0	5	0	0
T254	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T21,T37,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T21,T37,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T21,T37,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T21
1	0	Covered	T14,T3,T7
1	1	Covered	T21,T37,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T37,T34
0	1	Covered	T38,T77,T41
1	0	Covered	T42,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T37,T34
0	1	Covered	T21,T37,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T37,T34
1	-	Covered	T21,T37,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T37,T34
DetectSt	168	Covered	T21,T37,T34
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T21,T37,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T37,T34
DebounceSt->IdleSt	163	Covered	T111,T77,T163
DetectSt->IdleSt	186	Covered	T38,T77,T41
DetectSt->StableSt	191	Covered	T21,T37,T34
IdleSt->DebounceSt	148	Covered	T21,T37,T34
StableSt->IdleSt	206	Covered	T21,T37,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T37,T34
0	1	Covered	T21,T37,T34
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T37,T34
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T37,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T37,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T111,T77,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T37,T34
DetectSt	-	-	-	-	1	-	-	Covered	T38,T77,T41
DetectSt	-	-	-	-	0	1	-	Covered	T21,T37,T34
DetectSt	-	-	-	-	0	0	-	Covered	T21,T37,T34
StableSt	-	-	-	-	-	-	1	Covered	T21,T37,T34
StableSt	-	-	-	-	-	-	0	Covered	T21,T37,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	829	0	0
CntIncr_A	8913551	46362	0	0
CntNoWrap_A	8913551	8219096	0	0
DetectStDropOut_A	8913551	54	0	0
DetectedOut_A	8913551	13561	0	0
DetectedPulseOut_A	8913551	328	0	0
DisabledIdleSt_A	8913551	7872762	0	0
DisabledNoDetection_A	8913551	7874496	0	0
EnterDebounceSt_A	8913551	443	0	0
EnterDetectSt_A	8913551	386	0	0
EnterStableSt_A	8913551	328	0	0
PulseIsPulse_A	8913551	328	0	0
StayInStableSt	8913551	13207	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	301	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	829	0	0
T21	72090	8	0	0
T32	0	6	0	0
T34	0	2	0	0
T35	0	12	0	0
T36	0	8	0	0
T37	23992	10	0	0
T38	0	14	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T77	0	9	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	6	0	0
T113	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	46362	0	0
T21	72090	176	0	0
T32	0	240	0	0
T34	0	66	0	0
T35	0	522	0	0
T36	0	324	0	0
T37	23992	265	0	0
T38	0	1074	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T77	0	802	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	220	0	0
T113	0	123	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8219096	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	54	0	0
T35	23081	0	0	0
T38	24896	7	0	0
T41	0	5	0	0
T56	4716	0	0	0
T77	0	4	0	0
T93	5227	0	0	0
T96	0	1	0	0
T97	0	6	0	0
T98	0	1	0	0
T113	14795	0	0	0
T240	0	2	0	0
T246	521	0	0	0
T247	470	0	0	0
T248	507	0	0	0
T249	489	0	0	0
T250	408	0	0	0
T255	0	5	0	0
T256	0	2	0	0
T257	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	13561	0	0
T21	72090	37	0	0
T32	0	207	0	0
T34	0	53	0	0
T35	0	466	0	0
T36	0	21	0	0
T37	23992	203	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	142	0	0
T113	0	36	0	0
T163	0	157	0	0
T227	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	328	0	0
T21	72090	4	0	0
T32	0	3	0	0
T34	0	1	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	23992	5	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	2	0	0
T113	0	1	0	0
T163	0	9	0	0
T227	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7872762	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7874496	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	443	0	0
T21	72090	4	0	0
T32	0	3	0	0
T34	0	1	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	23992	5	0	0
T38	0	7	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T77	0	5	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	4	0	0
T113	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	386	0	0
T21	72090	4	0	0
T32	0	3	0	0
T34	0	1	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	23992	5	0	0
T38	0	7	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T77	0	4	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	2	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	328	0	0
T21	72090	4	0	0
T32	0	3	0	0
T34	0	1	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	23992	5	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	2	0	0
T113	0	1	0	0
T163	0	9	0	0
T227	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	328	0	0
T21	72090	4	0	0
T32	0	3	0	0
T34	0	1	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	23992	5	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	2	0	0
T113	0	1	0	0
T163	0	9	0	0
T227	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	13207	0	0
T21	72090	33	0	0
T32	0	202	0	0
T34	0	52	0	0
T35	0	460	0	0
T36	0	17	0	0
T37	23992	198	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T111	0	138	0	0
T113	0	35	0	0
T163	0	148	0	0
T227	0	75	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	301	0	0
T21	72090	4	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	6	0	0
T36	0	4	0	0
T37	23992	5	0	0
T42	0	1	0	0
T52	8117	0	0	0
T64	1294	0	0	0
T71	505	0	0	0
T72	503	0	0	0
T94	0	3	0	0
T105	489	0	0	0
T106	424	0	0	0
T107	423	0	0	0
T108	422	0	0	0
T113	0	1	0	0
T163	0	9	0	0