Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T53,T54,T55
1	0	Covered	T53,T42,T258

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
1	0	Covered	T251

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T11
1	-	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T11
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T42,T228,T176
DetectSt->IdleSt	186	Covered	T53,T54,T55
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T10,T11
StableSt->IdleSt	206	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T3,T10,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T228,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T53,T54,T55
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	3446	0	0
CntIncr_A	8913551	127951	0	0
CntNoWrap_A	8913551	8216479	0	0
DetectStDropOut_A	8913551	517	0	0
DetectedOut_A	8913551	88341	0	0
DetectedPulseOut_A	8913551	999	0	0
DisabledIdleSt_A	8913551	7723452	0	0
DisabledNoDetection_A	8913551	7725691	0	0
EnterDebounceSt_A	8913551	1732	0	0
EnterDetectSt_A	8913551	1714	0	0
EnterStableSt_A	8913551	999	0	0
PulseIsPulse_A	8913551	999	0	0
StayInStableSt	8913551	87237	0	0
gen_high_event_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	876	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	3446	0	0
T3	11372	30	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	32	0	0
T11	0	22	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	54	0	0
T34	0	26	0	0
T37	0	58	0	0
T48	660	0	0	0
T53	0	50	0	0
T54	0	50	0	0
T55	0	14	0	0
T56	0	24	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	127951	0	0
T3	11372	1230	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	720	0	0
T11	0	605	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	2322	0	0
T34	0	741	0	0
T37	0	1363	0	0
T48	660	0	0	0
T53	0	1883	0	0
T54	0	1151	0	0
T55	0	349	0	0
T56	0	500	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8216479	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	517	0	0
T34	13020	0	0	0
T39	714	0	0	0
T42	0	1	0	0
T53	7799	12	0	0
T54	4929	25	0	0
T55	0	7	0	0
T56	0	12	0	0
T92	725	0	0	0
T93	0	29	0	0
T95	0	9	0	0
T228	0	9	0	0
T230	0	15	0	0
T231	0	28	0	0
T232	452	0	0	0
T233	501	0	0	0
T234	490	0	0	0
T235	435	0	0	0
T236	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	88341	0	0
T3	11372	1905	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	500	0	0
T11	0	313	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1509	0	0
T33	0	2303	0	0
T34	0	904	0	0
T37	0	2014	0	0
T42	0	359	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	473	0	0
T227	0	2035	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	999	0	0
T3	11372	15	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	16	0	0
T11	0	11	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	27	0	0
T33	0	24	0	0
T34	0	13	0	0
T37	0	29	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	13	0	0
T227	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7723452	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7725691	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1732	0	0
T3	11372	15	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	16	0	0
T11	0	11	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	27	0	0
T34	0	13	0	0
T37	0	29	0	0
T48	660	0	0	0
T53	0	25	0	0
T54	0	25	0	0
T55	0	7	0	0
T56	0	12	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	1714	0	0
T3	11372	15	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	16	0	0
T11	0	11	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	27	0	0
T34	0	13	0	0
T37	0	29	0	0
T48	660	0	0	0
T53	0	25	0	0
T54	0	25	0	0
T55	0	7	0	0
T56	0	12	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	999	0	0
T3	11372	15	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	16	0	0
T11	0	11	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	27	0	0
T33	0	24	0	0
T34	0	13	0	0
T37	0	29	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	13	0	0
T227	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	999	0	0
T3	11372	15	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	16	0	0
T11	0	11	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	27	0	0
T33	0	24	0	0
T34	0	13	0	0
T37	0	29	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	13	0	0
T227	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	87237	0	0
T3	11372	1889	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	483	0	0
T11	0	302	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	1480	0	0
T33	0	2273	0	0
T34	0	889	0	0
T37	0	1978	0	0
T42	0	354	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	459	0	0
T227	0	2003	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	876	0	0
T3	11372	14	0	0
T4	167460	0	0	0
T7	209575	0	0	0
T10	0	15	0	0
T11	0	11	0	0
T26	503	0	0	0
T27	525	0	0	0
T32	0	25	0	0
T33	0	18	0	0
T34	0	11	0	0
T37	0	22	0	0
T42	0	5	0	0
T48	660	0	0	0
T58	428	0	0	0
T59	497	0	0	0
T60	496	0	0	0
T61	499	0	0	0
T111	0	12	0	0
T227	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T37,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T10,T37,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T37,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T14,T3,T7
1	1	Covered	T10,T37,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T37,T34
0	1	Covered	T113,T36,T241
1	0	Covered	T42,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T37,T34
0	1	Covered	T10,T37,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T37,T34
1	-	Covered	T10,T37,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T37,T34
DetectSt	168	Covered	T10,T37,T34
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T37,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T37,T34
DebounceSt->IdleSt	163	Covered	T38,T113,T36
DetectSt->IdleSt	186	Covered	T113,T36,T42
DetectSt->StableSt	191	Covered	T10,T37,T34
IdleSt->DebounceSt	148	Covered	T10,T37,T34
StableSt->IdleSt	206	Covered	T10,T37,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T37,T34
0	1	Covered	T10,T37,T34
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T37,T34
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T37,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T37,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T113,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T37,T34
DetectSt	-	-	-	-	1	-	-	Covered	T113,T36,T42
DetectSt	-	-	-	-	0	1	-	Covered	T10,T37,T34
DetectSt	-	-	-	-	0	0	-	Covered	T10,T37,T34
StableSt	-	-	-	-	-	-	1	Covered	T10,T37,T34
StableSt	-	-	-	-	-	-	0	Covered	T10,T37,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8913551	940	0	0
CntIncr_A	8913551	53687	0	0
CntNoWrap_A	8913551	8218985	0	0
DetectStDropOut_A	8913551	39	0	0
DetectedOut_A	8913551	15423	0	0
DetectedPulseOut_A	8913551	402	0	0
DisabledIdleSt_A	8913551	7863967	0	0
DisabledNoDetection_A	8913551	7865711	0	0
EnterDebounceSt_A	8913551	496	0	0
EnterDetectSt_A	8913551	444	0	0
EnterStableSt_A	8913551	402	0	0
PulseIsPulse_A	8913551	402	0	0
StayInStableSt	8913551	14997	0	0
gen_high_level_sva.HighLevelEvent_A	8913551	8222361	0	0
gen_not_sticky_sva.StableStDropOut_A	8913551	377	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	940	0	0
T10	12917	2	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	4	0	0
T33	0	12	0	0
T34	0	4	0	0
T35	0	4	0	0
T37	0	18	0	0
T38	0	17	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	2	0	0
T111	0	2	0	0
T113	0	18	0	0
T151	427	0	0	0
T252	568	0	0	0
T253	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	53687	0	0
T10	12917	67	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	166	0	0
T33	0	294	0	0
T34	0	110	0	0
T35	0	316	0	0
T37	0	549	0	0
T38	0	1251	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	114	0	0
T111	0	80	0	0
T113	0	1437	0	0
T151	427	0	0	0
T252	568	0	0	0
T253	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8218985	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	39	0	0
T33	19943	0	0	0
T36	0	1	0	0
T93	5227	0	0	0
T96	0	6	0	0
T110	508	0	0	0
T111	15841	0	0	0
T113	14795	8	0	0
T114	8147	0	0	0
T198	0	1	0	0
T215	0	10	0	0
T241	0	10	0	0
T249	489	0	0	0
T250	408	0	0	0
T259	0	1	0	0
T260	0	2	0	0
T261	506	0	0	0
T262	435	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	15423	0	0
T10	12917	46	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	134	0	0
T33	0	478	0	0
T34	0	130	0	0
T35	0	13	0	0
T37	0	288	0	0
T38	0	66	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	66	0	0
T111	0	52	0	0
T151	427	0	0	0
T227	0	273	0	0
T252	568	0	0	0
T253	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	402	0	0
T10	12917	1	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	9	0	0
T38	0	8	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	1	0	0
T111	0	1	0	0
T151	427	0	0	0
T227	0	4	0	0
T252	568	0	0	0
T253	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7863967	0	0
T1	1047	646	0	0
T5	426	25	0	0
T6	688	287	0	0
T13	489	88	0	0
T14	2715	711	0	0
T15	663	262	0	0
T16	705	304	0	0
T17	422	21	0	0
T18	410	9	0	0
T19	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	7865711	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	496	0	0
T10	12917	1	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	9	0	0
T38	0	9	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	1	0	0
T111	0	1	0	0
T113	0	10	0	0
T151	427	0	0	0
T252	568	0	0	0
T253	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	444	0	0
T10	12917	1	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	9	0	0
T38	0	8	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	1	0	0
T111	0	1	0	0
T113	0	8	0	0
T151	427	0	0	0
T252	568	0	0	0
T253	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	402	0	0
T10	12917	1	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	9	0	0
T38	0	8	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	1	0	0
T111	0	1	0	0
T151	427	0	0	0
T227	0	4	0	0
T252	568	0	0	0
T253	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	402	0	0
T10	12917	1	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	9	0	0
T38	0	8	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	1	0	0
T111	0	1	0	0
T151	427	0	0	0
T227	0	4	0	0
T252	568	0	0	0
T253	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	14997	0	0
T10	12917	45	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	132	0	0
T33	0	467	0	0
T34	0	128	0	0
T35	0	11	0	0
T37	0	279	0	0
T38	0	58	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	65	0	0
T111	0	50	0	0
T151	427	0	0	0
T227	0	265	0	0
T252	568	0	0	0
T253	424	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	8222361	0	0
T1	1047	647	0	0
T5	426	26	0	0
T6	688	288	0	0
T13	489	89	0	0
T14	2715	715	0	0
T15	663	263	0	0
T16	705	305	0	0
T17	422	22	0	0
T18	410	10	0	0
T19	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8913551	377	0	0
T10	12917	1	0	0
T11	12597	0	0	0
T12	558	0	0	0
T31	1124	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	9	0	0
T38	0	8	0	0
T49	448	0	0	0
T50	705	0	0	0
T69	524	0	0	0
T77	0	1	0	0
T94	0	12	0	0
T151	427	0	0	0
T163	0	6	0	0
T252	568	0	0	0
T253	424	0	0	0