Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1208801894	11202	0	0
auto_block_debounce_ctl_rd_A	1208801894	1752	0	0
auto_block_out_ctl_rd_A	1208801894	2411	0	0
com_det_ctl_0_rd_A	1208801894	3844	0	0
com_det_ctl_1_rd_A	1208801894	3861	0	0
com_det_ctl_2_rd_A	1208801894	3748	0	0
com_det_ctl_3_rd_A	1208801894	3723	0	0
com_out_ctl_0_rd_A	1208801894	4398	0	0
com_out_ctl_1_rd_A	1208801894	4236	0	0
com_out_ctl_2_rd_A	1208801894	4389	0	0
com_out_ctl_3_rd_A	1208801894	4255	0	0
com_pre_det_ctl_0_rd_A	1208801894	1115	0	0
com_pre_det_ctl_1_rd_A	1208801894	1246	0	0
com_pre_det_ctl_2_rd_A	1208801894	1094	0	0
com_pre_det_ctl_3_rd_A	1208801894	1254	0	0
com_pre_sel_ctl_0_rd_A	1208801894	4603	0	0
com_pre_sel_ctl_1_rd_A	1208801894	4393	0	0
com_pre_sel_ctl_2_rd_A	1208801894	4501	0	0
com_pre_sel_ctl_3_rd_A	1208801894	4277	0	0
com_sel_ctl_0_rd_A	1208801894	4630	0	0
com_sel_ctl_1_rd_A	1208801894	4618	0	0
com_sel_ctl_2_rd_A	1208801894	4406	0	0
com_sel_ctl_3_rd_A	1208801894	4590	0	0
ec_rst_ctl_rd_A	1208801894	2416	0	0
intr_enable_rd_A	1208801894	1894	0	0
key_intr_ctl_rd_A	1208801894	4255	0	0
key_intr_debounce_ctl_rd_A	1208801894	1260	0	0
key_invert_ctl_rd_A	1208801894	5577	0	0
pin_allowed_ctl_rd_A	1208801894	5706	0	0
pin_out_ctl_rd_A	1208801894	4565	0	0
pin_out_value_rd_A	1208801894	4342	0	0
regwen_rd_A	1208801894	1317	0	0
ulp_ac_debounce_ctl_rd_A	1208801894	1267	0	0
ulp_ctl_rd_A	1208801894	1376	0	0
ulp_lid_debounce_ctl_rd_A	1208801894	1380	0	0
ulp_pwrb_debounce_ctl_rd_A	1208801894	1507	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	11202	0	0
T7	422842	9	0	0
T8	215906	0	0	0
T9	275918	5	0	0
T21	0	12	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T41	0	3	0	0
T45	0	6	0	0
T47	0	6	0	0
T48	313953	0	0	0
T52	0	5	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T65	0	11	0	0
T150	0	12	0	0
T291	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1752	0	0
T2	50941	0	0	0
T3	545853	0	0	0
T4	227129	0	0	0
T7	0	47	0	0
T9	0	21	0	0
T15	315133	3	0	0
T16	169289	8	0	0
T17	211177	0	0	0
T18	51365	0	0	0
T19	50933	0	0	0
T20	314709	0	0	0
T57	158888	0	0	0
T116	0	16	0	0
T150	0	21	0	0
T167	0	57	0	0
T179	0	16	0	0
T296	0	12	0	0
T297	0	82	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	2411	0	0
T2	50941	0	0	0
T3	545853	0	0	0
T4	227129	0	0	0
T7	0	35	0	0
T9	0	41	0	0
T15	315133	13	0	0
T16	169289	7	0	0
T17	211177	0	0	0
T18	51365	0	0	0
T19	50933	0	0	0
T20	314709	0	0	0
T57	158888	0	0	0
T116	0	20	0	0
T150	0	14	0	0
T167	0	48	0	0
T179	0	16	0	0
T296	0	18	0	0
T297	0	77	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	3844	0	0
T7	422842	14	0	0
T8	215906	0	0	0
T9	275918	20	0	0
T10	0	19	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	46	0	0
T33	0	70	0	0
T34	0	34	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	71	0	0
T111	0	52	0	0
T113	0	53	0	0
T163	0	83	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	3861	0	0
T7	422842	10	0	0
T8	215906	0	0	0
T9	275918	12	0	0
T10	0	26	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	42	0	0
T33	0	62	0	0
T34	0	44	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	77	0	0
T111	0	62	0	0
T113	0	59	0	0
T163	0	90	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	3748	0	0
T7	422842	21	0	0
T8	215906	0	0	0
T9	275918	8	0	0
T10	0	24	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	29	0	0
T33	0	62	0	0
T34	0	48	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	79	0	0
T111	0	61	0	0
T113	0	60	0	0
T163	0	65	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	3723	0	0
T7	422842	35	0	0
T8	215906	0	0	0
T9	275918	24	0	0
T10	0	26	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	47	0	0
T33	0	94	0	0
T34	0	42	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	62	0	0
T111	0	58	0	0
T113	0	52	0	0
T163	0	79	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4398	0	0
T7	422842	23	0	0
T8	215906	0	0	0
T9	275918	12	0	0
T10	0	42	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	35	0	0
T33	0	68	0	0
T34	0	47	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	56	0	0
T111	0	47	0	0
T113	0	74	0	0
T163	0	65	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4236	0	0
T7	422842	12	0	0
T8	215906	0	0	0
T9	275918	18	0	0
T10	0	27	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	31	0	0
T33	0	73	0	0
T34	0	60	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	50	0	0
T111	0	63	0	0
T113	0	61	0	0
T163	0	78	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4389	0	0
T7	422842	29	0	0
T8	215906	0	0	0
T9	275918	7	0	0
T10	0	7	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	21	0	0
T33	0	74	0	0
T34	0	41	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	65	0	0
T111	0	60	0	0
T113	0	78	0	0
T163	0	41	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4255	0	0
T7	422842	15	0	0
T8	215906	0	0	0
T9	275918	15	0	0
T10	0	26	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	39	0	0
T33	0	57	0	0
T34	0	57	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	66	0	0
T111	0	38	0	0
T113	0	89	0	0
T163	0	64	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1115	0	0
T7	422842	21	0	0
T8	215906	0	0	0
T9	275918	21	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T116	0	10	0	0
T150	0	17	0	0
T166	0	3	0	0
T167	0	19	0	0
T179	0	14	0	0
T297	0	30	0	0
T298	0	10	0	0
T299	0	8	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1246	0	0
T7	422842	33	0	0
T8	215906	0	0	0
T9	275918	15	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T116	0	21	0	0
T150	0	28	0	0
T166	0	24	0	0
T167	0	32	0	0
T179	0	13	0	0
T297	0	23	0	0
T298	0	19	0	0
T299	0	2	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1094	0	0
T7	422842	17	0	0
T8	215906	0	0	0
T9	275918	13	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T84	0	39	0	0
T116	0	15	0	0
T150	0	24	0	0
T166	0	9	0	0
T167	0	21	0	0
T179	0	12	0	0
T297	0	28	0	0
T298	0	2	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1254	0	0
T7	422842	11	0	0
T8	215906	0	0	0
T9	275918	12	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T116	0	14	0	0
T150	0	25	0	0
T166	0	23	0	0
T167	0	11	0	0
T179	0	18	0	0
T297	0	37	0	0
T298	0	15	0	0
T299	0	11	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4603	0	0
T7	422842	15	0	0
T8	215906	0	0	0
T9	275918	16	0	0
T10	0	36	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	53	0	0
T33	0	68	0	0
T34	0	39	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	66	0	0
T111	0	66	0	0
T113	0	62	0	0
T163	0	63	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4393	0	0
T7	422842	24	0	0
T8	215906	0	0	0
T9	275918	16	0	0
T10	0	37	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	56	0	0
T33	0	60	0	0
T34	0	46	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	64	0	0
T111	0	59	0	0
T113	0	61	0	0
T163	0	67	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4501	0	0
T7	422842	34	0	0
T8	215906	0	0	0
T9	275918	6	0	0
T10	0	8	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	31	0	0
T33	0	56	0	0
T34	0	54	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	53	0	0
T111	0	67	0	0
T113	0	72	0	0
T163	0	70	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4277	0	0
T7	422842	29	0	0
T8	215906	0	0	0
T9	275918	9	0	0
T10	0	21	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	40	0	0
T33	0	62	0	0
T34	0	54	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	64	0	0
T111	0	55	0	0
T113	0	73	0	0
T163	0	53	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4630	0	0
T7	422842	11	0	0
T8	215906	0	0	0
T9	275918	19	0	0
T10	0	30	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	30	0	0
T33	0	47	0	0
T34	0	38	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	59	0	0
T111	0	48	0	0
T113	0	63	0	0
T163	0	61	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4618	0	0
T7	422842	33	0	0
T8	215906	0	0	0
T9	275918	6	0	0
T10	0	26	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	35	0	0
T33	0	71	0	0
T34	0	50	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	86	0	0
T111	0	53	0	0
T113	0	78	0	0
T163	0	96	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4406	0	0
T7	422842	14	0	0
T8	215906	0	0	0
T9	275918	17	0	0
T10	0	29	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	26	0	0
T33	0	70	0	0
T34	0	47	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	69	0	0
T111	0	60	0	0
T113	0	67	0	0
T163	0	57	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4590	0	0
T7	422842	31	0	0
T8	215906	0	0	0
T9	275918	24	0	0
T10	0	12	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	43	0	0
T33	0	67	0	0
T34	0	49	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	54	0	0
T111	0	58	0	0
T113	0	67	0	0
T163	0	60	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	2416	0	0
T7	422842	35	0	0
T8	215906	0	0	0
T9	275918	20	0	0
T10	0	14	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T32	0	16	0	0
T33	0	19	0	0
T34	0	9	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T77	0	14	0	0
T111	0	10	0	0
T113	0	15	0	0
T300	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1894	0	0
T7	422842	29	0	0
T8	215906	0	0	0
T9	275918	38	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T116	0	43	0	0
T150	0	94	0	0
T166	0	34	0	0
T167	0	59	0	0
T179	0	11	0	0
T297	0	52	0	0
T298	0	2	0	0
T299	0	43	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4255	0	0
T2	50941	4	0	0
T3	545853	0	0	0
T4	227129	0	0	0
T7	422842	25	0	0
T9	0	15	0	0
T26	125806	0	0	0
T48	313953	0	0	0
T57	158888	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T88	0	3	0	0
T116	0	29	0	0
T132	0	7	0	0
T137	0	3	0	0
T150	0	38	0	0
T167	0	25	0	0
T179	0	12	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1260	0	0
T7	422842	15	0	0
T8	215906	0	0	0
T9	275918	16	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T116	0	12	0	0
T150	0	48	0	0
T166	0	18	0	0
T167	0	19	0	0
T179	0	15	0	0
T297	0	23	0	0
T298	0	7	0	0
T299	0	6	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	5577	0	0
T2	50941	0	0	0
T7	0	137	0	0
T9	0	25	0	0
T13	232418	64	0	0
T14	120849	0	0	0
T15	315133	0	0	0
T16	169289	0	0	0
T17	211177	0	0	0
T18	51365	0	0	0
T19	50933	0	0	0
T20	314709	0	0	0
T57	158888	0	0	0
T61	0	63	0	0
T105	0	48	0	0
T150	0	86	0	0
T159	0	27	0	0
T236	0	72	0	0
T301	0	68	0	0
T302	0	82	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	5706	0	0
T7	422842	87	0	0
T8	215906	0	0	0
T9	275918	19	0	0
T26	125806	30	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T71	0	67	0	0
T91	0	156	0	0
T150	0	276	0	0
T167	0	23	0	0
T233	0	40	0	0
T248	0	45	0	0
T261	0	64	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4565	0	0
T7	422842	76	0	0
T8	215906	0	0	0
T9	275918	2	0	0
T26	125806	49	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T71	0	88	0	0
T91	0	135	0	0
T150	0	234	0	0
T167	0	9	0	0
T233	0	32	0	0
T248	0	71	0	0
T261	0	86	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	4342	0	0
T7	422842	89	0	0
T8	215906	0	0	0
T9	275918	16	0	0
T26	125806	39	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T71	0	89	0	0
T91	0	155	0	0
T150	0	258	0	0
T167	0	15	0	0
T233	0	54	0	0
T248	0	58	0	0
T261	0	69	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1317	0	0
T7	422842	30	0	0
T8	215906	0	0	0
T9	275918	14	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T84	0	38	0	0
T116	0	12	0	0
T150	0	27	0	0
T166	0	31	0	0
T167	0	26	0	0
T179	0	24	0	0
T297	0	19	0	0
T298	0	1	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1267	0	0
T7	422842	34	0	0
T8	215906	0	0	0
T9	275918	20	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T31	0	2	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T76	0	1	0	0
T89	0	17	0	0
T91	0	4	0	0
T116	0	30	0	0
T150	0	36	0	0
T167	0	19	0	0
T303	0	4	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1376	0	0
T7	422842	34	0	0
T8	215906	0	0	0
T9	275918	12	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T31	0	9	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T76	0	10	0	0
T89	0	15	0	0
T91	0	2	0	0
T116	0	34	0	0
T150	0	22	0	0
T167	0	31	0	0
T303	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1380	0	0
T7	422842	31	0	0
T8	215906	0	0	0
T9	275918	22	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T31	0	6	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T76	0	2	0	0
T89	0	17	0	0
T91	0	8	0	0
T116	0	30	0	0
T150	0	40	0	0
T167	0	20	0	0
T303	0	9	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1208801894	1507	0	0
T7	422842	50	0	0
T8	215906	0	0	0
T9	275918	20	0	0
T26	125806	0	0	0
T27	65645	0	0	0
T31	0	1	0	0
T48	313953	0	0	0
T58	42797	0	0	0
T59	243343	0	0	0
T60	59576	0	0	0
T61	67430	0	0	0
T76	0	9	0	0
T89	0	5	0	0
T91	0	3	0	0
T116	0	27	0	0
T150	0	39	0	0
T167	0	26	0	0
T303	0	10	0	0