Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_pin_in_value_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_pin_in_value_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_pin_in_value_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00

Variables for Group Instance sysrst_ctrl_pin_in_value_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_ec_rst_l	2	0	2	100.00	100	1	1	2
cp_flash_wp_l	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1323

1

T4

11

T14

18

T17

12

auto[1]

1290

1

T4

11

T14

23

T17

18

---

Summary for Variable cp_ec_rst_l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1334

1

T4

11

T14

17

T17

15

auto[1]

1279

1

T4

11

T14

24

T17

15

---

Summary for Variable cp_flash_wp_l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1257

1

T4

13

T14

24

T17

16

auto[1]

1356

1

T4

9

T14

17

T17

14

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1316

1

T4

10

T14

14

T17

13

auto[1]

1297

1

T4

12

T14

27

T17

17

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1312

1

T4

12

T14

20

T17

20

auto[1]

1301

1

T4

10

T14

21

T17

10

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1319

1

T4

12

T14

22

T17

21

auto[1]

1294

1

T4

10

T14

19

T17

9

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1303

1

T4

12

T14

16

T17

13

auto[1]

1310

1

T4

10

T14

25

T17

17

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1300

1

T4

13

T14

20

T17

9

auto[1]

1313

1

T4

9

T14

21

T17

21