Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1856

1

T1

35

T3

34

T9

18

auto[1]

663

1

T1

5

T3

2

T9

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1891

1

T1

40

T3

26

T9

18

auto[1]

628

1

T3

10

T9

6

T45

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1934

1

T1

40

T3

31

T9

23

auto[1]

585

1

T3

5

T9

1

T11

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1827

1

T1

29

T3

36

T9

24

auto[1]

692

1

T1

11

T11

9

T12

13

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2341

1

T1

34

T3

31

T9

23

auto[1]

178

1

T1

6

T3

5

T9

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2282

1

T1

33

T3

34

T9

23

auto[1]

237

1

T1

7

T3

2

T9

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2184

1

T1

35

T3

34

T9

24

auto[1]

335

1

T1

5

T3

2

T12

11

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T1

40

T3

24

T9

18

auto[1]

117

1

T3

12

T9

6

T194

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2359

1

T1

40

T3

31

T9

17

auto[1]

160

1

T3

5

T9

7

T56

28

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1965

1

T1

33

T3

34

T9

24

auto[1]

554

1

T1

7

T3

2

T10

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	*	--	--	4

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	903	1			T45	3		T11	17		T34	22
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	53	1			T1	5		T10	8		T56	10
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	63	1			T56	20		T75	7		T291	7
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	17	1			T56	8		T292	3		T375	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	18	1			T194	4		T376	1		T377	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	23	1			T3	5		T137	1		T107	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	20	1			T3	5		T9	6		T137	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T368	2		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	217	1			T1	4		T12	8		T75	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	21	1			T119	1		T137	7		T378	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	11	1			T285	5		T379	1		T189	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T380	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	75	1			T1	2		T143	4		T368	6
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	21	1			T12	2		T266	2		T285	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	13	1			T119	1		T290	2		T381	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T9	1		T382	2		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	10	1			T368	5		T369	4		T383	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	3	1			T292	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	9	1			T107	4		T384	5		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	34	1			T12	3		T385	1		T373	22
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	6	1			T369	6		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T386	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	11	1			T3	2		T371	2		T270	5

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

176

1

T137

1

T141

7

T40

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

87

1

T1

2

T10

8

T137

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

48

1

T3

2

T75

5

T312

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

170

1

T1

5

T11

9

T12

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

80

1

T1

4

T33

1

T330

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T56

10

T119

1

T143

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T12

3

T385

2

T367

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

114

1

T9

1

T56

10

T35

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T143

2

T103

3

T167

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

58

1

T107

5

T368

6

T318

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T11

2

T297

1

T387

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T12

2

T346

7

T290

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

42

1

T119

1

T144

3

T388

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

30

1

T35

2

T169

5

T367

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T34

4

T151

2

T389

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

123

1

T3

5

T11

6

T40

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

49

1

T9

6

T45

3

T34

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T118

3

T370

5

T303

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T59

2

T346

2

T318

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T75

7

T233

1

T151

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

53

1

T34

7

T56

10

T40

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T378

5

T325

1

T187

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T167

1

T390

1

T304

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

68

1

T3

5

T56

8

T118

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T118

4

T141

4

T122

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T144

5

T346

3

T169

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T301

1

T304

1

T387

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

30

1

T34

3

T137

7

T123

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T141

1

T370

2

T391

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T33

1

T370

1

T391

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T158

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded