Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T5

9

T16

5

T66

13

auto[1]

974

1

T5

11

T16

15

T66

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

455

1

T5

5

T16

5

T66

3

from_0to1

451

1

T5

5

T16

5

T66

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

966

1

T5

11

T16

14

T66

9

auto[1]

966

1

T5

9

T16

6

T66

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

963

1

T5

9

T16

8

T66

9

auto[1]

969

1

T5

11

T16

12

T66

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

48

1

T5

1

T33

1

T40

2

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T5

1

T16

1

T36

3

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T71

2

T72

2

T33

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T66

2

T71

1

T72

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T71

1

T72

1

T178

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T72

1

T178

1

T40

2

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T5

1

T16

1

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T5

1

T72

2

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T16

1

T71

1

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T5

2

T16

2

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T72

1

T33

1

T36

2

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T5

1

T16

1

T66

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T16

1

T66

1

T33

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T5

2

T16

2

T66

1

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T16

1

T71

2

T198

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T5

1

T71

2

T36

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T5

11

T16

10

T66

4

auto[1]

960

1

T5

9

T16

10

T66

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

470

1

T5

4

T16

4

T66

7

from_0to1

471

1

T5

4

T16

4

T66

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

934

1

T5

10

T16

10

T66

4

auto[1]

998

1

T5

10

T16

10

T66

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T5

6

T16

13

T66

9

auto[1]

974

1

T5

14

T16

7

T66

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T16

1

T33

1

T36

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T5

2

T71

1

T72

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T5

1

T16

1

T36

5

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T16

1

T66

2

T71

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T5

1

T72

1

T33

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T5

1

T71

1

T33

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T16

2

T36

2

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T5

2

T66

1

T72

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T16

1

T66

1

T71

1

auto[1]

from_1to0

auto[0]

auto[1]

45

1

T5

1

T71

1

T178

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T66

2

T72

1

T168

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T66

2

T71

1

T33

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T16

1

T66

1

T71

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T71

2

T72

1

T33

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T16

1

T66

3

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T66

1

T36

1

T178

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T5

11

T16

11

T66

9

auto[1]

926

1

T5

9

T16

9

T66

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

461

1

T5

4

T16

5

T66

4

from_0to1

469

1

T5

4

T16

4

T66

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T5

13

T16

9

T66

10

auto[1]

941

1

T5

7

T16

11

T66

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T5

6

T16

12

T66

10

auto[1]

946

1

T5

14

T16

8

T66

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T71

1

T33

1

T36

3

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T5

2

T71

1

T72

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T16

2

T66

1

T33

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T71

1

T33

1

T36

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T5

1

T16

1

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T5

1

T16

2

T66

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T5

1

T71

1

T36

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T16

1

T72

3

T33

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T5

1

T16

1

T66

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T5

1

T72

1

T40

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T16

1

T66

1

T71

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T16

1

T66

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T33

1

T157

1

T233

3

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T71

2

T72

1

T33

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T66

2

T33

1

T36

3

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T5

1

T66

1

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T5

12

T16

10

T66

12

auto[1]

933

1

T5

8

T16

10

T66

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

474

1

T5

5

T16

3

T66

5

from_0to1

473

1

T5

4

T16

3

T66

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T5

12

T16

6

T66

13

auto[1]

925

1

T5

8

T16

14

T66

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

960

1

T5

12

T16

10

T66

9

auto[1]

972

1

T5

8

T16

10

T66

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T66

1

T71

1

T72

1

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T16

1

T66

1

T33

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T5

1

T16

2

T71

4

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T33

1

T36

1

T178

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T5

1

T16

1

T66

2

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T5

2

T66

1

T71

2

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T16

1

T66

1

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T71

1

T33

1

T36

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T5

2

T66

2

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T36

1

T178

1

T198

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T5

1

T36

3

T157

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T5

1

T66

1

T33

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T36

1

T198

1

T35

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T33

1

T36

1

T178

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T178

1

T198

3

T35

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T5

1

T16

1

T66

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

957

1

T5

11

T16

11

T66

10

auto[1]

975

1

T5

9

T16

9

T66

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

450

1

T5

3

T16

4

T66

5

from_0to1

457

1

T5

2

T16

4

T66

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

946

1

T5

10

T16

11

T66

10

auto[1]

986

1

T5

10

T16

9

T66

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

967

1

T5

12

T16

9

T66

13

auto[1]

965

1

T5

8

T16

11

T66

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T5

1

T16

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T72

2

T36

1

T198

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T16

1

T66

2

T198

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T16

1

T71

2

T178

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T5

1

T16

1

T71

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T71

1

T33

1

T36

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T66

1

T71

1

T36

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T71

1

T36

3

T178

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T16

1

T72

1

T33

2

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T66

1

T71

1

T178

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T5

1

T33

1

T36

3

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T5

1

T66

1

T71

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T66

1

T71

1

T72

3

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T71

1

T33

2

T36

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T16

1

T66

2

T36

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T5

1

T16

2

T72

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T5

12

T16

10

T66

9

auto[1]

942

1

T5

8

T16

10

T66

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

473

1

T5

5

T16

5

T66

5

from_0to1

469

1

T5

5

T16

6

T66

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

962

1

T5

10

T16

9

T66

10

auto[1]

970

1

T5

10

T16

11

T66

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

946

1

T5

8

T16

10

T66

9

auto[1]

986

1

T5

12

T16

10

T66

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T5

1

T16

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T5

1

T36

1

T178

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T16

1

T71

1

T33

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T5

1

T66

1

T72

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T5

2

T16

1

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T66

1

T36

1

T178

2

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T66

1

T72

1

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T5

1

T16

1

T33

2

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T5

1

T16

1

T71

2

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T16

2

T66

2

T36

3

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T71

1

T72

2

T36

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T5

1

T66

2

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T16

2

T66

1

T71

2

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T33

2

T36

1

T35

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T66

1

T71

2

T72

2

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T5

2

T16

2

T36

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T5

5

T16

12

T66

12

auto[1]

936

1

T5

15

T16

8

T66

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

454

1

T5

4

T16

6

T66

6

from_0to1

474

1

T5

5

T16

6

T66

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

933

1

T5

10

T16

13

T66

5

auto[1]

999

1

T5

10

T16

7

T66

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985

1

T5

10

T16

12

T66

10

auto[1]

947

1

T5

10

T16

8

T66

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T5

1

T16

2

T71

2

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T71

1

T36

3

T35

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T16

1

T66

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T16

1

T66

1

T36

4

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T5

1

T71

1

T33

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T16

2

T178

1

T40

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T16

1

T66

2

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T66

2

T36

2

T35

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T5

1

T16

1

T66

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T5

1

T16

1

T36

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T5

1

T66

2

T71

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T71

1

T33

2

T36

2

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T5

1

T71

1

T72

2

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T5

1

T16

2

T71

2

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T16

1

T66

2

T33

2

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T5

2

T71

1

T36

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

956

1

T5

13

T16

11

T66

6

auto[1]

976

1

T5

7

T16

9

T66

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

479

1

T5

4

T16

5

T66

5

from_0to1

476

1

T5

3

T16

5

T66

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T5

10

T16

9

T66

7

auto[1]

974

1

T5

10

T16

11

T66

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

967

1

T5

10

T16

14

T66

10

auto[1]

965

1

T5

10

T16

6

T66

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T5

1

T33

1

T36

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T33

2

T178

1

T35

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T16

1

T66

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T5

2

T16

1

T71

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T16

2

T71

1

T72

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T5

1

T71

1

T33

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T66

1

T72

1

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T5

1

T16

1

T66

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T16

1

T66

2

T33

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T66

1

T71

2

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T5

1

T16

2

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T72

1

T33

1

T36

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T71

1

T72

3

T33

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T5

1

T16

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T16

1

T66

2

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T66

1

T36

1

T40

4