Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146180	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113177

1

T1

315

T4

12

T5

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136251	1			T1	307		T4	24		T5	62
values[0x0]	61573	1			T1	326		T5	30		T2	5
values[0x1]	61533	1			T1	357		T4	1		T5	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	118268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141089

1

T1

404

T4

14

T5

57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1141	1			T6	6		T29	3		T11	2
valid_sources[0x01]	1055	1			T5	1		T14	2		T16	1
valid_sources[0x02]	941	1			T5	1		T29	2		T8	2
valid_sources[0x03]	947	1			T29	5		T8	9		T9	4
valid_sources[0x04]	742	1			T6	4		T30	34		T8	3
valid_sources[0x05]	885	1			T6	3		T29	1		T8	1
valid_sources[0x06]	1047	1			T29	3		T8	1		T66	1
valid_sources[0x07]	850	1			T5	1		T14	1		T29	2
valid_sources[0x08]	818	1			T14	2		T29	5		T9	8
valid_sources[0x09]	1487	1			T14	4		T26	1		T29	2
valid_sources[0x0a]	728	1			T5	1		T29	2		T30	12
valid_sources[0x0b]	944	1			T2	1		T14	4		T29	1
valid_sources[0x0c]	2729	1			T16	1		T29	3		T8	4
valid_sources[0x0d]	714	1			T29	2		T71	2		T11	27
valid_sources[0x0e]	880	1			T14	1		T29	1		T8	5
valid_sources[0x0f]	986	1			T14	1		T15	1		T8	6
valid_sources[0x10]	753	1			T14	7		T29	4		T30	1
valid_sources[0x11]	803	1			T5	2		T29	1		T8	1
valid_sources[0x12]	1295	1			T29	3		T12	4		T56	4
valid_sources[0x13]	1010	1			T5	1		T14	2		T54	1
valid_sources[0x14]	773	1			T4	3		T29	3		T8	3
valid_sources[0x15]	723	1			T14	1		T16	1		T29	2
valid_sources[0x16]	1644	1			T5	1		T9	2		T65	1
valid_sources[0x17]	959	1			T29	2		T8	1		T9	20
valid_sources[0x18]	1059	1			T5	1		T29	2		T8	1
valid_sources[0x19]	1141	1			T5	1		T14	4		T16	3
valid_sources[0x1a]	1582	1			T5	1		T29	5		T8	1
valid_sources[0x1b]	1032	1			T29	1		T9	24		T66	1
valid_sources[0x1c]	962	1			T14	6		T29	1		T8	1
valid_sources[0x1d]	851	1			T5	1		T2	2		T15	1
valid_sources[0x1e]	879	1			T5	1		T14	10		T8	2
valid_sources[0x1f]	1363	1			T29	1		T9	13		T66	1
valid_sources[0x20]	709	1			T5	2		T29	4		T9	26
valid_sources[0x21]	1458	1			T5	1		T15	1		T6	2
valid_sources[0x22]	1051	1			T14	2		T9	9		T11	1
valid_sources[0x23]	846	1			T5	1		T29	1		T8	6
valid_sources[0x24]	829	1			T29	2		T9	4		T66	1
valid_sources[0x25]	1279	1			T5	3		T14	2		T54	1
valid_sources[0x26]	692	1			T5	1		T14	2		T29	2
valid_sources[0x27]	1336	1			T5	1		T16	3		T29	1
valid_sources[0x28]	833	1			T14	1		T9	2		T23	6
valid_sources[0x29]	873	1			T5	2		T14	1		T15	1
valid_sources[0x2a]	683	1			T5	1		T14	1		T66	1
valid_sources[0x2b]	838	1			T5	3		T65	1		T66	1
valid_sources[0x2c]	823	1			T6	10		T29	2		T67	2
valid_sources[0x2d]	847	1			T14	3		T16	1		T26	1
valid_sources[0x2e]	875	1			T2	1		T29	8		T8	3
valid_sources[0x2f]	1711	1			T14	5		T71	1		T72	9
valid_sources[0x30]	806	1			T5	2		T29	3		T66	1
valid_sources[0x31]	1050	1			T5	1		T2	3		T16	2
valid_sources[0x32]	1825	1			T14	2		T9	15		T66	1
valid_sources[0x33]	883	1			T5	1		T29	5		T8	1
valid_sources[0x34]	805	1			T5	1		T9	2		T66	1
valid_sources[0x35]	719	1			T5	2		T14	5		T8	1
valid_sources[0x36]	962	1			T14	3		T9	2		T68	1
valid_sources[0x37]	883	1			T14	4		T16	3		T29	1
valid_sources[0x38]	1051	1			T29	3		T8	5		T9	15
valid_sources[0x39]	966	1			T14	3		T16	5		T29	1
valid_sources[0x3a]	1658	1			T29	2		T30	55		T24	1
valid_sources[0x3b]	672	1			T14	3		T15	1		T29	5
valid_sources[0x3c]	835	1			T14	1		T29	1		T66	1
valid_sources[0x3d]	885	1			T5	1		T14	1		T16	4
valid_sources[0x3e]	706	1			T15	1		T29	1		T8	3
valid_sources[0x3f]	889	1			T14	1		T23	4		T71	1
valid_sources[0x40]	832	1			T5	1		T14	4		T29	1
valid_sources[0x41]	856	1			T14	2		T16	2		T66	1
valid_sources[0x42]	1001	1			T14	5		T16	1		T29	1
valid_sources[0x43]	997	1			T14	1		T28	8		T72	6
valid_sources[0x44]	908	1			T16	3		T9	1		T340	1
valid_sources[0x45]	883	1			T5	2		T14	4		T29	2
valid_sources[0x46]	1264	1			T14	4		T16	2		T29	3
valid_sources[0x47]	1005	1			T16	4		T30	7		T8	2
valid_sources[0x48]	2733	1			T14	1		T9	8		T71	2
valid_sources[0x49]	971	1			T16	2		T25	16		T29	1
valid_sources[0x4a]	890	1			T5	1		T14	1		T29	2
valid_sources[0x4b]	854	1			T5	2		T29	1		T9	4
valid_sources[0x4c]	813	1			T14	1		T65	1		T45	3
valid_sources[0x4d]	894	1			T29	3		T8	4		T66	1
valid_sources[0x4e]	986	1			T15	1		T16	6		T29	2
valid_sources[0x4f]	1513	1			T5	1		T14	3		T16	4
valid_sources[0x50]	885	1			T5	1		T14	2		T29	3
valid_sources[0x51]	791	1			T5	2		T29	2		T8	1
valid_sources[0x52]	849	1			T4	1		T14	1		T29	1
valid_sources[0x53]	858	1			T14	4		T16	1		T29	2
valid_sources[0x54]	1011	1			T6	6		T29	2		T30	9
valid_sources[0x55]	988	1			T16	1		T52	1		T29	3
valid_sources[0x56]	823	1			T5	1		T14	7		T16	1
valid_sources[0x57]	900	1			T5	2		T29	1		T8	9
valid_sources[0x58]	2487	1			T14	3		T3	1307		T29	2
valid_sources[0x59]	1247	1			T4	1		T29	2		T9	5
valid_sources[0x5a]	778	1			T14	4		T29	3		T9	12
valid_sources[0x5b]	859	1			T29	2		T8	1		T9	3
valid_sources[0x5c]	963	1			T4	2		T29	1		T65	2
valid_sources[0x5d]	848	1			T5	1		T52	4		T29	2
valid_sources[0x5e]	1269	1			T14	2		T6	1		T29	1
valid_sources[0x5f]	793	1			T5	1		T2	1		T29	2
valid_sources[0x60]	2024	1			T15	1		T29	3		T8	1
valid_sources[0x61]	820	1			T5	1		T29	3		T9	2
valid_sources[0x62]	923	1			T29	1		T70	10		T24	1
valid_sources[0x63]	885	1			T5	1		T14	1		T29	1
valid_sources[0x64]	736	1			T14	5		T29	1		T65	1
valid_sources[0x65]	1055	1			T5	1		T8	1		T71	1
valid_sources[0x66]	757	1			T5	1		T29	2		T9	3
valid_sources[0x67]	800	1			T14	7		T26	5		T66	1
valid_sources[0x68]	846	1			T5	1		T8	7		T9	2
valid_sources[0x69]	1023	1			T14	6		T9	7		T66	1
valid_sources[0x6a]	745	1			T29	4		T12	4		T34	4
valid_sources[0x6b]	816	1			T5	1		T15	1		T29	1
valid_sources[0x6c]	1733	1			T14	1		T29	4		T71	4
valid_sources[0x6d]	906	1			T4	2		T29	4		T8	2
valid_sources[0x6e]	748	1			T14	2		T29	1		T8	12
valid_sources[0x6f]	871	1			T4	3		T16	6		T52	6
valid_sources[0x70]	835	1			T16	1		T29	2		T8	6
valid_sources[0x71]	1059	1			T14	1		T16	1		T9	4
valid_sources[0x72]	871	1			T14	2		T16	3		T26	1
valid_sources[0x73]	835	1			T5	1		T13	2		T29	1
valid_sources[0x74]	832	1			T29	4		T9	5		T71	1
valid_sources[0x75]	807	1			T16	2		T29	3		T8	3
valid_sources[0x76]	856	1			T14	1		T29	1		T30	1
valid_sources[0x77]	885	1			T66	1		T71	2		T24	1
valid_sources[0x78]	948	1			T5	1		T14	1		T16	6
valid_sources[0x79]	989	1			T5	1		T14	5		T16	2
valid_sources[0x7a]	907	1			T16	1		T29	1		T66	1
valid_sources[0x7b]	935	1			T14	3		T6	1		T29	2
valid_sources[0x7c]	1480	1			T5	1		T16	1		T8	2
valid_sources[0x7d]	854	1			T29	2		T65	1		T66	1
valid_sources[0x7e]	1607	1			T14	1		T29	1		T9	1
valid_sources[0x7f]	928	1			T29	5		T8	2		T9	3
valid_sources[0x80]	769	1			T5	2		T29	1		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61833

1

T1

144

T4

12

T5

31

values[0x0]

all_enables

biggest_size

30105

1

T1

105

T5

8

T14

39

values[0x1]

all_enables

biggest_size

21239

1

T1

66

T5

3

T14

22