Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T25,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T25,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T25,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T1,T4,T5
1	1	Covered	T25,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T27
0	1	Covered	T51,T106,T124
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T27
0	1	Covered	T25,T26,T27
1	0	Covered	T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T26,T27
1	-	Covered	T25,T26,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T27
DetectSt	168	Covered	T25,T26,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T25,T26,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T26,T27
DebounceSt->IdleSt	163	Covered	T33,T48,T51
DetectSt->IdleSt	186	Covered	T51,T106,T124
DetectSt->StableSt	191	Covered	T25,T26,T27
IdleSt->DebounceSt	148	Covered	T25,T26,T27
StableSt->IdleSt	206	Covered	T25,T26,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T26,T27
0	1	Covered	T25,T26,T27
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T48,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T51,T106,T124
DetectSt	-	-	-	-	0	1	-	Covered	T25,T26,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T26,T27
StableSt	-	-	-	-	-	-	0	Covered	T25,T26,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	282	0	0
CntIncr_A	6005714	222810	0	0
CntNoWrap_A	6005714	5359541	0	0
DetectStDropOut_A	6005714	5	0	0
DetectedOut_A	6005714	916	0	0
DetectedPulseOut_A	6005714	124	0	0
DisabledIdleSt_A	6005714	5130324	0	0
DisabledNoDetection_A	6005714	5132535	0	0
EnterDebounceSt_A	6005714	155	0	0
EnterDetectSt_A	6005714	129	0	0
EnterStableSt_A	6005714	124	0	0
PulseIsPulse_A	6005714	124	0	0
StayInStableSt	6005714	792	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	6727	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	123	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	282	0	0
T6	1498	0	0	0
T7	670	0	0	0
T25	777	2	0	0
T26	667	2	0	0
T27	0	4	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	15	0	0
T36	0	2	0	0
T47	0	2	0	0
T48	0	5	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	3	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	222810	0	0
T6	1498	0	0	0
T7	670	0	0	0
T25	777	98	0	0
T26	667	15	0	0
T27	0	148	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	493	0	0
T36	0	56	0	0
T47	0	57	0	0
T48	0	73	0	0
T49	0	107	0	0
T50	0	96	0	0
T51	0	126	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359541	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5	0	0
T21	4815	0	0	0
T38	747	0	0	0
T51	722	1	0	0
T106	0	1	0	0
T121	4875	0	0	0
T124	0	1	0	0
T126	0	1	0	0
T132	0	1	0	0
T133	437	0	0	0
T134	421	0	0	0
T135	610	0	0	0
T136	735	0	0	0
T137	31637	0	0	0
T138	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	916	0	0
T6	1498	0	0	0
T7	670	0	0	0
T21	0	6	0	0
T25	777	11	0	0
T26	667	4	0	0
T27	0	21	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	52	0	0
T36	0	10	0	0
T47	0	9	0	0
T48	0	7	0	0
T49	0	15	0	0
T50	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	124	0	0
T6	1498	0	0	0
T7	670	0	0	0
T21	0	1	0	0
T25	777	1	0	0
T26	667	1	0	0
T27	0	2	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	7	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5130324	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5132535	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	155	0	0
T6	1498	0	0	0
T7	670	0	0	0
T25	777	1	0	0
T26	667	1	0	0
T27	0	2	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	8	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	129	0	0
T6	1498	0	0	0
T7	670	0	0	0
T25	777	1	0	0
T26	667	1	0	0
T27	0	2	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	7	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	124	0	0
T6	1498	0	0	0
T7	670	0	0	0
T21	0	1	0	0
T25	777	1	0	0
T26	667	1	0	0
T27	0	2	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	7	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	124	0	0
T6	1498	0	0	0
T7	670	0	0	0
T21	0	1	0	0
T25	777	1	0	0
T26	667	1	0	0
T27	0	2	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	7	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	792	0	0
T6	1498	0	0	0
T7	670	0	0	0
T21	0	5	0	0
T25	777	10	0	0
T26	667	3	0	0
T27	0	19	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	45	0	0
T36	0	9	0	0
T47	0	8	0	0
T48	0	5	0	0
T49	0	13	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T136	0	25	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	6727	0	0
T1	13850	29	0	0
T2	722	0	0	0
T3	27219	26	0	0
T4	431	4	0	0
T5	502	2	0	0
T6	0	6	0	0
T13	8402	0	0	0
T14	4021	12	0	0
T15	403	0	0	0
T16	502	6	0	0
T17	432	2	0	0
T25	0	3	0	0
T26	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	123	0	0
T6	1498	0	0	0
T7	670	0	0	0
T21	0	1	0	0
T25	777	1	0	0
T26	667	1	0	0
T27	0	2	0	0
T28	453	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T33	0	7	0	0
T36	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T22
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T22
0	1	Covered	T6,T116,T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T22
0	1	Unreachable
1	0	Covered	T6,T21,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T21,T22
DetectSt	168	Covered	T6,T21,T22
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T21,T22
DebounceSt->IdleSt	163	Covered	T59,T145,T104
DetectSt->IdleSt	186	Covered	T6,T116,T109
DetectSt->StableSt	191	Covered	T6,T21,T22
IdleSt->DebounceSt	148	Covered	T6,T21,T22
StableSt->IdleSt	206	Covered	T6,T21,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T21,T22
0	1	Covered	T6,T21,T22
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T21,T22
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T21,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T145,T109
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T6,T116,T109
DetectSt	-	-	-	-	0	1	-	Covered	T6,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T21,T22
StableSt	-	-	-	-	-	-	0	Covered	T6,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	199	0	0
CntIncr_A	6005714	132093	0	0
CntNoWrap_A	6005714	5359624	0	0
DetectStDropOut_A	6005714	20	0	0
DetectedOut_A	6005714	482842	0	0
DetectedPulseOut_A	6005714	59	0	0
DisabledIdleSt_A	6005714	3908915	0	0
DisabledNoDetection_A	6005714	3911185	0	0
EnterDebounceSt_A	6005714	120	0	0
EnterDetectSt_A	6005714	79	0	0
EnterStableSt_A	6005714	59	0	0
PulseIsPulse_A	6005714	59	0	0
StayInStableSt	6005714	482783	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	6727	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_sticky_sva.StableStDropOut_A	6005714	610139	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	199	0	0
T6	1498	8	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	2	0	0
T22	0	4	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	2	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	5	0	0
T76	0	2	0	0
T77	0	4	0	0
T78	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	132093	0	0
T6	1498	388	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	81	0	0
T22	0	30	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	10	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	21	0	0
T58	0	49	0	0
T59	0	353	0	0
T76	0	44	0	0
T77	0	128	0	0
T78	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359624	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	20	0	0
T6	1498	3	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T109	0	2	0	0
T110	0	6	0	0
T116	0	1	0	0
T148	0	3	0	0
T149	0	1	0	0
T150	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	482842	0	0
T6	1498	100	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	176	0	0
T22	0	26	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	42	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	89	0	0
T58	0	111	0	0
T76	0	172	0	0
T77	0	261	0	0
T78	0	234	0	0
T146	0	151	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	59	0	0
T6	1498	1	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3908915	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3911185	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	120	0	0
T6	1498	4	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	5	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	79	0	0
T6	1498	4	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	59	0	0
T6	1498	1	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	59	0	0
T6	1498	1	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	482783	0	0
T6	1498	99	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	175	0	0
T22	0	24	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	41	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	88	0	0
T58	0	110	0	0
T76	0	171	0	0
T77	0	259	0	0
T78	0	232	0	0
T146	0	150	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	6727	0	0
T1	13850	29	0	0
T2	722	0	0	0
T3	27219	26	0	0
T4	431	4	0	0
T5	502	2	0	0
T6	0	6	0	0
T13	8402	0	0	0
T14	4021	12	0	0
T15	403	0	0	0
T16	502	6	0	0
T17	432	2	0	0
T25	0	3	0	0
T26	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	610139	0	0
T6	1498	138	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	42	0	0
T22	0	343	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	446	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	238	0	0
T58	0	358	0	0
T76	0	272	0	0
T77	0	102	0	0
T78	0	275	0	0
T146	0	467	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T22,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T22
1	0	Covered	T4,T5,T2
1	1	Covered	T6,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T22,T57
0	1	Covered	T58,T114,T115
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T22,T57
0	1	Unreachable
1	0	Covered	T6,T22,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T21,T22
DetectSt	168	Covered	T6,T22,T57
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T22,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T22,T57
DebounceSt->IdleSt	163	Covered	T21,T59,T146
DetectSt->IdleSt	186	Covered	T58,T114,T115
DetectSt->StableSt	191	Covered	T6,T22,T57
IdleSt->DebounceSt	148	Covered	T6,T21,T22
StableSt->IdleSt	206	Covered	T6,T22,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T21,T22
0	1	Covered	T6,T21,T22
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T22,T57
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T22,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T59,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T58,T114,T115
DetectSt	-	-	-	-	0	1	-	Covered	T6,T22,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T22,T57
StableSt	-	-	-	-	-	-	0	Covered	T6,T22,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	215	0	0
CntIncr_A	6005714	27381	0	0
CntNoWrap_A	6005714	5359608	0	0
DetectStDropOut_A	6005714	16	0	0
DetectedOut_A	6005714	119062	0	0
DetectedPulseOut_A	6005714	48	0	0
DisabledIdleSt_A	6005714	3908915	0	0
DisabledNoDetection_A	6005714	3911185	0	0
EnterDebounceSt_A	6005714	151	0	0
EnterDetectSt_A	6005714	64	0	0
EnterStableSt_A	6005714	48	0	0
PulseIsPulse_A	6005714	48	0	0
StayInStableSt	6005714	119014	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_sticky_sva.StableStDropOut_A	6005714	697418	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	215	0	0
T6	1498	4	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	2	0	0
T22	0	4	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	2	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	2	0	0
T58	0	6	0	0
T59	0	6	0	0
T76	0	2	0	0
T77	0	4	0	0
T78	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	27381	0	0
T6	1498	182	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	96	0	0
T22	0	170	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	35	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	19	0	0
T58	0	300	0	0
T59	0	290	0	0
T76	0	78	0	0
T77	0	26	0	0
T78	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359608	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	16	0	0
T35	30252	0	0	0
T40	54664	0	0	0
T58	3487	3	0	0
T114	0	3	0	0
T115	0	4	0	0
T149	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	591	0	0	0
T155	522	0	0	0
T156	412	0	0	0
T157	508	0	0	0
T158	34123	0	0	0
T159	5317	0	0	0
T160	761	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	119062	0	0
T6	1498	510	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T22	0	135	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	166	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	73	0	0
T59	0	42	0	0
T76	0	367	0	0
T77	0	72	0	0
T78	0	275	0	0
T145	0	156	0	0
T147	0	264	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	48	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T145	0	1	0	0
T147	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3908915	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3911185	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	151	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	5	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	64	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	48	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T145	0	1	0	0
T147	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	48	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T22	0	2	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	1	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T145	0	1	0	0
T147	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	119014	0	0
T6	1498	508	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T22	0	133	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	165	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	72	0	0
T59	0	41	0	0
T76	0	366	0	0
T77	0	70	0	0
T78	0	273	0	0
T145	0	155	0	0
T147	0	263	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	697418	0	0
T6	1498	153	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T22	0	115	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	293	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	264	0	0
T59	0	73	0	0
T76	0	60	0	0
T77	0	384	0	0
T78	0	194	0	0
T145	0	991	0	0
T147	0	281	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T21,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T22
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T57
0	1	Covered	T77,T109,T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T57
0	1	Unreachable
1	0	Covered	T6,T21,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T21,T22
DetectSt	168	Covered	T6,T21,T57
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T21,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T21,T57
DebounceSt->IdleSt	163	Covered	T22,T40,T77
DetectSt->IdleSt	186	Covered	T77,T109,T110
DetectSt->StableSt	191	Covered	T6,T21,T57
IdleSt->DebounceSt	148	Covered	T6,T21,T22
StableSt->IdleSt	206	Covered	T6,T21,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T21,T22
0	1	Covered	T6,T21,T22
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T21,T57
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T21,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T40,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T77,T109,T110
DetectSt	-	-	-	-	0	1	-	Covered	T6,T21,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T21,T57
StableSt	-	-	-	-	-	-	0	Covered	T6,T21,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	191	0	0
CntIncr_A	6005714	141627	0	0
CntNoWrap_A	6005714	5359632	0	0
DetectStDropOut_A	6005714	15	0	0
DetectedOut_A	6005714	564477	0	0
DetectedPulseOut_A	6005714	62	0	0
DisabledIdleSt_A	6005714	3908915	0	0
DisabledNoDetection_A	6005714	3911185	0	0
EnterDebounceSt_A	6005714	114	0	0
EnterDetectSt_A	6005714	77	0	0
EnterStableSt_A	6005714	62	0	0
PulseIsPulse_A	6005714	62	0	0
StayInStableSt	6005714	564415	0	0
gen_high_event_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_sticky_sva.StableStDropOut_A	6005714	212469	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	191	0	0
T6	1498	4	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	2	0	0
T22	0	3	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	3	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	4	0	0
T76	0	2	0	0
T77	0	8	0	0
T78	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	141627	0	0
T6	1498	162	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	19	0	0
T22	0	132	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	255	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	75	0	0
T58	0	81	0	0
T59	0	76	0	0
T76	0	73	0	0
T77	0	290	0	0
T78	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359632	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	15	0	0
T77	981	2	0	0
T109	0	2	0	0
T110	0	4	0	0
T122	19542	0	0	0
T153	0	1	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	1	0	0
T164	522	0	0	0
T165	495	0	0	0
T166	402	0	0	0
T167	9939	0	0	0
T168	507	0	0	0
T169	13857	0	0	0
T170	497	0	0	0
T171	852	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	564477	0	0
T6	1498	632	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	22	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	230	0	0
T58	0	402	0	0
T59	0	226	0	0
T76	0	153	0	0
T77	0	1	0	0
T78	0	168	0	0
T86	0	81	0	0
T145	0	688	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	62	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T86	0	1	0	0
T145	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3908915	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3911185	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	114	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T22	0	3	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T40	0	3	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T76	0	1	0	0
T77	0	5	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	77	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T78	0	2	0	0
T86	0	1	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	62	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T86	0	1	0	0
T145	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	62	0	0
T6	1498	2	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	1	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T86	0	1	0	0
T145	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	564415	0	0
T6	1498	630	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	21	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	229	0	0
T58	0	401	0	0
T59	0	224	0	0
T76	0	152	0	0
T78	0	166	0	0
T86	0	80	0	0
T116	0	197	0	0
T145	0	687	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	212469	0	0
T6	1498	68	0	0
T7	670	0	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T21	0	267	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T52	404	0	0	0
T53	964	0	0	0
T54	623	0	0	0
T57	0	57	0	0
T58	0	42	0	0
T59	0	401	0	0
T76	0	281	0	0
T77	0	50	0	0
T78	0	373	0	0
T86	0	148535	0	0
T145	0	420	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T36,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T37,T38,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T1,T4,T5
1	1	Covered	T36,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T40
0	1	Covered	T113,T172
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T40
0	1	Covered	T38,T40,T42
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T38,T40
1	-	Covered	T38,T40,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T37,T38
DetectSt	168	Covered	T37,T38,T40
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T37,T38,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T38,T40
DebounceSt->IdleSt	163	Covered	T36,T173,T104
DetectSt->IdleSt	186	Covered	T113,T172
DetectSt->StableSt	191	Covered	T37,T38,T40
IdleSt->DebounceSt	148	Covered	T36,T37,T38
StableSt->IdleSt	206	Covered	T38,T40,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T37,T38
0	1	Covered	T36,T37,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T38,T40
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T38,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T173,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T113,T172
DetectSt	-	-	-	-	0	1	-	Covered	T37,T38,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T40,T42
StableSt	-	-	-	-	-	-	0	Covered	T37,T38,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	88	0	0
CntIncr_A	6005714	2834	0	0
CntNoWrap_A	6005714	5359735	0	0
DetectStDropOut_A	6005714	2	0	0
DetectedOut_A	6005714	3127	0	0
DetectedPulseOut_A	6005714	40	0	0
DisabledIdleSt_A	6005714	5339182	0	0
DisabledNoDetection_A	6005714	5341402	0	0
EnterDebounceSt_A	6005714	46	0	0
EnterDetectSt_A	6005714	42	0	0
EnterStableSt_A	6005714	40	0	0
PulseIsPulse_A	6005714	40	0	0
StayInStableSt	6005714	3067	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	88	0	0
T36	9846	1	0	0
T37	936	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T42	0	4	0	0
T44	0	2	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T173	0	3	0	0
T175	0	4	0	0
T176	0	2	0	0
T177	0	2	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2834	0	0
T36	9846	42	0	0
T37	936	90	0	0
T38	0	37	0	0
T40	0	186	0	0
T42	0	52	0	0
T44	0	43	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T173	0	174	0	0
T175	0	140	0	0
T176	0	100	0	0
T177	0	27	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359735	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2	0	0
T113	707	1	0	0
T172	0	1	0	0
T183	1777	0	0	0
T184	422	0	0	0
T185	492	0	0	0
T186	493	0	0	0
T187	21910	0	0	0
T188	502	0	0	0
T189	12702	0	0	0
T190	524	0	0	0
T191	13341	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3127	0	0
T37	936	38	0	0
T38	0	80	0	0
T39	987	0	0	0
T40	0	321	0	0
T42	0	111	0	0
T44	0	86	0	0
T47	676	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T173	0	179	0	0
T175	0	86	0	0
T176	0	42	0	0
T177	0	42	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T192	0	42	0	0
T193	541	0	0	0
T194	14990	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T37	936	1	0	0
T38	0	1	0	0
T39	987	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	676	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T173	0	1	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	1	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T192	0	1	0	0
T193	541	0	0	0
T194	14990	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5339182	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5341402	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	46	0	0
T36	9846	1	0	0
T37	936	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T173	0	2	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	42	0	0
T37	936	1	0	0
T38	0	1	0	0
T39	987	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	676	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T173	0	1	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	1	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T192	0	1	0	0
T193	541	0	0	0
T194	14990	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T37	936	1	0	0
T38	0	1	0	0
T39	987	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	676	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T173	0	1	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	1	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T192	0	1	0	0
T193	541	0	0	0
T194	14990	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T37	936	1	0	0
T38	0	1	0	0
T39	987	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	676	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T173	0	1	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	1	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T192	0	1	0	0
T193	541	0	0	0
T194	14990	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3067	0	0
T37	936	36	0	0
T38	0	79	0	0
T39	987	0	0	0
T40	0	318	0	0
T42	0	108	0	0
T44	0	84	0	0
T47	676	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T173	0	178	0	0
T175	0	83	0	0
T176	0	41	0	0
T177	0	40	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T192	0	41	0	0
T193	541	0	0	0
T194	14990	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	19	0	0
T38	747	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	634	0	0	0
T61	498	0	0	0
T74	618	0	0	0
T109	0	1	0	0
T138	402	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T192	0	1	0	0
T195	0	1	0	0
T196	0	2	0	0
T197	447	0	0	0
T198	505	0	0	0
T199	753	0	0	0
T200	716	0	0	0
T201	450	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T8,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T8,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T8,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T37
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T8,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T37
0	1	Covered	T2,T8,T37
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T37
1	-	Covered	T2,T8,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T37
DetectSt	168	Covered	T2,T8,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T8,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T37
DebounceSt->IdleSt	163	Covered	T39,T38,T104
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T8,T37
IdleSt->DebounceSt	148	Covered	T2,T8,T37
StableSt->IdleSt	206	Covered	T2,T8,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T37
0	1	Covered	T2,T8,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T38,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T37
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	128	0	0
CntIncr_A	6005714	31540	0	0
CntNoWrap_A	6005714	5359695	0	0
DetectStDropOut_A	6005714	0	0	0
DetectedOut_A	6005714	32011	0	0
DetectedPulseOut_A	6005714	60	0	0
DisabledIdleSt_A	6005714	5230527	0	0
DisabledNoDetection_A	6005714	5232741	0	0
EnterDebounceSt_A	6005714	68	0	0
EnterDetectSt_A	6005714	60	0	0
EnterStableSt_A	6005714	60	0	0
PulseIsPulse_A	6005714	60	0	0
StayInStableSt	6005714	31926	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	2461	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	128	0	0
T2	722	4	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	2	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	2	0	0
T38	0	3	0	0
T39	0	5	0	0
T40	0	4	0	0
T52	404	0	0	0
T74	0	2	0	0
T86	0	2	0	0
T177	0	4	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	31540	0	0
T2	722	120	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	56	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	90	0	0
T38	0	74	0	0
T39	0	213	0	0
T40	0	150	0	0
T52	404	0	0	0
T74	0	77	0	0
T86	0	87	0	0
T177	0	158	0	0
T202	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359695	0	0
T1	13850	13425	0	0
T2	722	317	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	32011	0	0
T2	722	141	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	28	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	131	0	0
T38	0	171	0	0
T39	0	205	0	0
T40	0	65	0	0
T52	404	0	0	0
T74	0	132	0	0
T86	0	213	0	0
T177	0	79	0	0
T202	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T52	404	0	0	0
T74	0	1	0	0
T86	0	1	0	0
T177	0	2	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5230527	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5232741	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	68	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	3	0	0
T40	0	2	0	0
T52	404	0	0	0
T74	0	1	0	0
T86	0	1	0	0
T177	0	2	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T52	404	0	0	0
T74	0	1	0	0
T86	0	1	0	0
T177	0	2	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T52	404	0	0	0
T74	0	1	0	0
T86	0	1	0	0
T177	0	2	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T52	404	0	0	0
T74	0	1	0	0
T86	0	1	0	0
T177	0	2	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	31926	0	0
T2	722	138	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	27	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	130	0	0
T38	0	169	0	0
T39	0	202	0	0
T40	0	63	0	0
T52	404	0	0	0
T74	0	130	0	0
T86	0	211	0	0
T177	0	77	0	0
T202	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2461	0	0
T2	722	2	0	0
T3	27219	0	0	0
T4	431	5	0	0
T5	502	5	0	0
T7	0	1	0	0
T8	0	11	0	0
T13	8402	0	0	0
T14	4021	15	0	0
T15	403	0	0	0
T16	502	5	0	0
T17	432	2	0	0
T25	777	0	0	0
T65	0	7	0	0
T66	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	34	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T52	404	0	0	0
T177	0	2	0	0
T195	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0