Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T38
0	1	Covered	T206
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T38
0	1	Covered	T36,T40,T207
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T36,T38
1	-	Covered	T36,T40,T207

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T36,T38
DetectSt	168	Covered	T2,T36,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T36,T38
DebounceSt->IdleSt	163	Covered	T104
DetectSt->IdleSt	186	Covered	T55,T206
DetectSt->StableSt	191	Covered	T2,T36,T38
IdleSt->DebounceSt	148	Covered	T2,T36,T38
StableSt->IdleSt	206	Covered	T36,T40,T208

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T36,T38
0	1	Covered	T2,T36,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T36,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T36,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T36,T38
DetectSt	-	-	-	-	1	-	-	Covered	T55,T206
DetectSt	-	-	-	-	0	1	-	Covered	T2,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T40,T207
StableSt	-	-	-	-	-	-	0	Covered	T2,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	79	0	0
CntIncr_A	6005714	2035	0	0
CntNoWrap_A	6005714	5359744	0	0
DetectStDropOut_A	6005714	1	0	0
DetectedOut_A	6005714	2550	0	0
DetectedPulseOut_A	6005714	37	0	0
DisabledIdleSt_A	6005714	5341576	0	0
DisabledNoDetection_A	6005714	5343792	0	0
EnterDebounceSt_A	6005714	40	0	0
EnterDetectSt_A	6005714	39	0	0
EnterStableSt_A	6005714	37	0	0
PulseIsPulse_A	6005714	37	0	0
StayInStableSt	6005714	2496	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	79	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	4	0	0
T38	0	2	0	0
T40	0	2	0	0
T52	404	0	0	0
T55	0	2	0	0
T104	0	1	0	0
T195	0	2	0	0
T203	0	4	0	0
T207	0	4	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2035	0	0
T2	722	60	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	84	0	0
T38	0	37	0	0
T40	0	75	0	0
T52	404	0	0	0
T55	0	46	0	0
T104	0	30	0	0
T195	0	48	0	0
T203	0	140	0	0
T207	0	32	0	0
T208	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359744	0	0
T1	13850	13425	0	0
T2	722	319	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1	0	0
T206	17049	1	0	0
T209	682	0	0	0
T210	12285	0	0	0
T211	32898	0	0	0
T212	480	0	0	0
T213	12027	0	0	0
T214	2837	0	0	0
T215	406	0	0	0
T216	725	0	0	0
T217	625	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2550	0	0
T2	722	91	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	156	0	0
T38	0	41	0	0
T40	0	29	0	0
T52	404	0	0	0
T195	0	40	0	0
T203	0	295	0	0
T204	0	42	0	0
T207	0	97	0	0
T208	0	43	0	0
T218	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	37	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T52	404	0	0	0
T195	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T207	0	2	0	0
T208	0	1	0	0
T218	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5341576	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5343792	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T52	404	0	0	0
T55	0	1	0	0
T104	0	1	0	0
T195	0	1	0	0
T203	0	2	0	0
T207	0	2	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	39	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T52	404	0	0	0
T55	0	1	0	0
T195	0	1	0	0
T203	0	2	0	0
T207	0	2	0	0
T208	0	1	0	0
T218	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	37	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T52	404	0	0	0
T195	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T207	0	2	0	0
T208	0	1	0	0
T218	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	37	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T52	404	0	0	0
T195	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T207	0	2	0	0
T208	0	1	0	0
T218	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2496	0	0
T2	722	89	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	154	0	0
T38	0	39	0	0
T40	0	28	0	0
T52	404	0	0	0
T195	0	38	0	0
T203	0	292	0	0
T204	0	40	0	0
T207	0	94	0	0
T208	0	41	0	0
T218	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	20	0	0
T36	9846	2	0	0
T37	936	0	0	0
T40	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T113	0	1	0	0
T118	19861	0	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T203	0	1	0	0
T207	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	2	0	0
T221	0	2	0	0
T222	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T7,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T36
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T7,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T36
0	1	Covered	T223,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T36
0	1	Covered	T2,T37,T74
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T36
1	-	Covered	T2,T37,T74

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T36
DetectSt	168	Covered	T2,T7,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T36
DebounceSt->IdleSt	163	Covered	T36,T39,T104
DetectSt->IdleSt	186	Covered	T223,T88
DetectSt->StableSt	191	Covered	T2,T7,T36
IdleSt->DebounceSt	148	Covered	T2,T7,T36
StableSt->IdleSt	206	Covered	T2,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T36
0	1	Covered	T2,T7,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T39,T203
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T36
DetectSt	-	-	-	-	1	-	-	Covered	T223,T88
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T37,T74
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	112	0	0
CntIncr_A	6005714	15366	0	0
CntNoWrap_A	6005714	5359711	0	0
DetectStDropOut_A	6005714	2	0	0
DetectedOut_A	6005714	4616	0	0
DetectedPulseOut_A	6005714	50	0	0
DisabledIdleSt_A	6005714	5332811	0	0
DisabledNoDetection_A	6005714	5335037	0	0
EnterDebounceSt_A	6005714	61	0	0
EnterDetectSt_A	6005714	52	0	0
EnterStableSt_A	6005714	50	0	0
PulseIsPulse_A	6005714	50	0	0
StayInStableSt	6005714	4538	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	2877	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	112	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	2	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T39	0	3	0	0
T40	0	4	0	0
T42	0	4	0	0
T43	0	2	0	0
T44	0	2	0	0
T52	404	0	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	15366	0	0
T2	722	60	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	96	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	126	0	0
T37	0	180	0	0
T39	0	142	0	0
T40	0	150	0	0
T42	0	52	0	0
T43	0	69	0	0
T44	0	43	0	0
T52	404	0	0	0
T74	0	77	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359711	0	0
T1	13850	13425	0	0
T2	722	319	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2	0	0
T88	0	1	0	0
T223	713	1	0	0
T224	533	0	0	0
T225	402	0	0	0
T226	495	0	0	0
T227	431	0	0	0
T228	644	0	0	0
T229	1126	0	0	0
T230	448	0	0	0
T231	1790	0	0	0
T232	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4616	0	0
T2	722	100	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	165	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	41	0	0
T37	0	253	0	0
T39	0	118	0	0
T40	0	333	0	0
T42	0	48	0	0
T43	0	156	0	0
T44	0	17	0	0
T52	404	0	0	0
T74	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	50	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T74	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5332811	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5335037	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	61	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	52	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T74	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	50	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T74	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	50	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T74	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4538	0	0
T2	722	99	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	163	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	39	0	0
T37	0	250	0	0
T39	0	116	0	0
T40	0	330	0	0
T42	0	45	0	0
T43	0	154	0	0
T44	0	16	0	0
T52	404	0	0	0
T74	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2877	0	0
T2	722	1	0	0
T3	27219	0	0	0
T4	431	4	0	0
T5	502	5	0	0
T7	0	1	0	0
T8	0	14	0	0
T13	8402	0	0	0
T14	4021	20	0	0
T15	403	0	0	0
T16	502	4	0	0
T17	432	3	0	0
T25	777	0	0	0
T53	0	4	0	0
T54	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	21	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T74	0	1	0	0
T86	0	1	0	0
T207	0	2	0	0
T208	0	1	0	0
T233	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T36
0	1	Covered	T2,T7,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T36
1	-	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T8
DetectSt	168	Covered	T2,T7,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T8
DebounceSt->IdleSt	163	Covered	T104,T55,T234
DetectSt->IdleSt	186	Covered	T88
DetectSt->StableSt	191	Covered	T2,T7,T8
IdleSt->DebounceSt	148	Covered	T2,T7,T8
StableSt->IdleSt	206	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T235,T236,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T88
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	127	0	0
CntIncr_A	6005714	68054	0	0
CntNoWrap_A	6005714	5359696	0	0
DetectStDropOut_A	6005714	1	0	0
DetectedOut_A	6005714	4647	0	0
DetectedPulseOut_A	6005714	60	0	0
DisabledIdleSt_A	6005714	5223448	0	0
DisabledNoDetection_A	6005714	5225664	0	0
EnterDebounceSt_A	6005714	67	0	0
EnterDetectSt_A	6005714	61	0	0
EnterStableSt_A	6005714	60	0	0
PulseIsPulse_A	6005714	60	0	0
StayInStableSt	6005714	4560	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	127	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T39	0	4	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	4	0	0
T52	404	0	0	0
T173	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	68054	0	0
T2	722	60	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	96	0	0
T8	0	56	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	84	0	0
T37	0	90	0	0
T39	0	142	0	0
T41	0	67	0	0
T42	0	52	0	0
T44	0	86	0	0
T52	404	0	0	0
T173	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359696	0	0
T1	13850	13425	0	0
T2	722	319	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1	0	0
T88	18336	1	0	0
T132	59059	0	0	0
T238	494	0	0	0
T239	493	0	0	0
T240	20420	0	0	0
T241	502	0	0	0
T242	513	0	0	0
T243	584	0	0	0
T244	403	0	0	0
T245	30972	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4647	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	21	0	0
T8	0	29	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	112	0	0
T37	0	260	0	0
T39	0	129	0	0
T41	0	300	0	0
T42	0	148	0	0
T44	0	103	0	0
T52	404	0	0	0
T173	0	159	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T52	404	0	0	0
T173	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5223448	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5225664	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	67	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T52	404	0	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	61	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T52	404	0	0	0
T173	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T52	404	0	0	0
T173	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T52	404	0	0	0
T173	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4560	0	0
T7	670	20	0	0
T8	4858	28	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	110	0	0
T37	0	258	0	0
T39	0	127	0	0
T41	0	298	0	0
T42	0	145	0	0
T44	0	100	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	156	0	0
T175	0	69	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	33	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T233	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T8,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T7,T8,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T8,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T37
1	0	Covered	T1,T4,T5
1	1	Covered	T7,T8,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T39
0	1	Not Covered
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T39
0	1	Covered	T39,T38,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T39
1	-	Covered	T39,T38,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T39
DetectSt	168	Covered	T7,T8,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T8,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T39
DebounceSt->IdleSt	163	Covered	T104,T109,T111
DetectSt->IdleSt	186	Covered	T55
DetectSt->StableSt	191	Covered	T7,T8,T39
IdleSt->DebounceSt	148	Covered	T7,T8,T39
StableSt->IdleSt	206	Covered	T8,T39,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T39
0	1	Covered	T7,T8,T39
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T109,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T39
DetectSt	-	-	-	-	1	-	-	Covered	T55
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T38,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	93	0	0
CntIncr_A	6005714	30125	0	0
CntNoWrap_A	6005714	5359730	0	0
DetectStDropOut_A	6005714	0	0	0
DetectedOut_A	6005714	2751	0	0
DetectedPulseOut_A	6005714	44	0	0
DisabledIdleSt_A	6005714	5230594	0	0
DisabledNoDetection_A	6005714	5232809	0	0
EnterDebounceSt_A	6005714	48	0	0
EnterDetectSt_A	6005714	45	0	0
EnterStableSt_A	6005714	44	0	0
PulseIsPulse_A	6005714	44	0	0
StayInStableSt	6005714	2686	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	6307	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	93	0	0
T7	670	2	0	0
T8	4858	2	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	2	0	0
T175	0	2	0	0
T177	0	4	0	0
T207	0	2	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	30125	0	0
T7	670	96	0	0
T8	4858	56	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	37	0	0
T39	0	142	0	0
T40	0	93	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	26	0	0
T175	0	70	0	0
T177	0	158	0	0
T207	0	16	0	0
T208	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359730	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2751	0	0
T7	670	46	0	0
T8	4858	40	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	39	0	0
T39	0	161	0	0
T40	0	43	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	80	0	0
T175	0	114	0	0
T177	0	286	0	0
T207	0	58	0	0
T208	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	44	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T207	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5230594	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5232809	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	48	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T207	0	1	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	45	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T207	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	44	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T207	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	44	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T177	0	2	0	0
T207	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2686	0	0
T7	670	44	0	0
T8	4858	38	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T38	0	38	0	0
T39	0	158	0	0
T40	0	42	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T173	0	79	0	0
T175	0	113	0	0
T177	0	283	0	0
T207	0	56	0	0
T208	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	6307	0	0
T1	13850	28	0	0
T2	722	1	0	0
T3	27219	27	0	0
T4	431	1	0	0
T5	502	3	0	0
T6	0	6	0	0
T7	0	1	0	0
T13	8402	0	0	0
T14	4021	18	0	0
T15	403	0	0	0
T16	502	5	0	0
T17	432	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	23	0	0
T38	0	1	0	0
T39	987	1	0	0
T40	0	1	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T177	0	1	0	0
T203	0	1	0	0
T218	0	1	0	0
T246	0	2	0	0
T247	0	1	0	0
T248	423	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T8,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T7,T8,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T8,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T36
1	0	Covered	T1,T4,T5
1	1	Covered	T7,T8,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T36
0	1	Covered	T221
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T36
0	1	Covered	T36,T39,T38
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T36
1	-	Covered	T36,T39,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T36
DetectSt	168	Covered	T7,T8,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T8,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T36
DebounceSt->IdleSt	163	Covered	T233,T104,T113
DetectSt->IdleSt	186	Covered	T221
DetectSt->StableSt	191	Covered	T7,T8,T36
IdleSt->DebounceSt	148	Covered	T7,T8,T36
StableSt->IdleSt	206	Covered	T8,T36,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T36
0	1	Covered	T7,T8,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T233,T113
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T36
DetectSt	-	-	-	-	1	-	-	Covered	T221
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T39,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	125	0	0
CntIncr_A	6005714	3124	0	0
CntNoWrap_A	6005714	5359698	0	0
DetectStDropOut_A	6005714	1	0	0
DetectedOut_A	6005714	4288	0	0
DetectedPulseOut_A	6005714	60	0	0
DisabledIdleSt_A	6005714	5345294	0	0
DisabledNoDetection_A	6005714	5347518	0	0
EnterDebounceSt_A	6005714	64	0	0
EnterDetectSt_A	6005714	61	0	0
EnterStableSt_A	6005714	60	0	0
PulseIsPulse_A	6005714	60	0	0
StayInStableSt	6005714	4203	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	125	0	0
T7	670	2	0	0
T8	4858	2	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	4	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	6	0	0
T42	0	4	0	0
T43	0	2	0	0
T44	0	2	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3124	0	0
T7	670	96	0	0
T8	4858	56	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	84	0	0
T38	0	74	0	0
T39	0	142	0	0
T40	0	225	0	0
T42	0	52	0	0
T43	0	69	0	0
T44	0	43	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359698	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1	0	0
T221	726	1	0	0
T249	52102	0	0	0
T250	424	0	0	0
T251	30176	0	0	0
T252	843	0	0	0
T253	401	0	0	0
T254	566	0	0	0
T255	427	0	0	0
T256	899	0	0	0
T257	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4288	0	0
T7	670	165	0	0
T8	4858	126	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	83	0	0
T38	0	43	0	0
T39	0	91	0	0
T40	0	99	0	0
T42	0	80	0	0
T43	0	47	0	0
T44	0	17	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	226	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5345294	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5347518	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	64	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	61	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	60	0	0
T7	670	1	0	0
T8	4858	1	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4203	0	0
T7	670	163	0	0
T8	4858	124	0	0
T9	21785	0	0	0
T26	667	0	0	0
T29	5216	0	0	0
T30	6066	0	0	0
T36	0	81	0	0
T38	0	40	0	0
T39	0	88	0	0
T40	0	96	0	0
T42	0	78	0	0
T43	0	46	0	0
T44	0	16	0	0
T53	964	0	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T175	0	224	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	34	0	0
T36	9846	2	0	0
T37	936	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T86	0	1	0	0
T118	19861	0	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T233	0	1	0	0
T246	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T39,T38,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T39,T38,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T38,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T37,T39
1	0	Covered	T1,T4,T5
1	1	Covered	T39,T38,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T41,T42
0	1	Not Covered
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T41,T42
0	1	Covered	T38,T42,T173
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T41,T42
1	-	Covered	T38,T42,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T39,T38,T41
DetectSt	168	Covered	T38,T41,T42
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T38,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T41,T42
DebounceSt->IdleSt	163	Covered	T39,T104,T258
DetectSt->IdleSt	186	Covered	T55
DetectSt->StableSt	191	Covered	T38,T41,T42
IdleSt->DebounceSt	148	Covered	T39,T38,T41
StableSt->IdleSt	206	Covered	T38,T42,T173

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T39,T38,T41
0	1	Covered	T39,T38,T41
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T41,T42
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T39,T38,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T258
DebounceSt	-	0	0	-	-	-	-	Covered	T39,T38,T41
DetectSt	-	-	-	-	1	-	-	Covered	T55
DetectSt	-	-	-	-	0	1	-	Covered	T38,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T42,T173
StableSt	-	-	-	-	-	-	0	Covered	T38,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	75	0	0
CntIncr_A	6005714	2065	0	0
CntNoWrap_A	6005714	5359748	0	0
DetectStDropOut_A	6005714	0	0	0
DetectedOut_A	6005714	2649	0	0
DetectedPulseOut_A	6005714	35	0	0
DisabledIdleSt_A	6005714	5341282	0	0
DisabledNoDetection_A	6005714	5343504	0	0
EnterDebounceSt_A	6005714	39	0	0
EnterDetectSt_A	6005714	36	0	0
EnterStableSt_A	6005714	35	0	0
PulseIsPulse_A	6005714	35	0	0
StayInStableSt	6005714	2597	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	5888	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	75	0	0
T38	0	2	0	0
T39	987	1	0	0
T41	0	2	0	0
T42	0	4	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T86	0	2	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	4	0	0
T176	0	2	0	0
T233	0	4	0	0
T246	0	2	0	0
T248	423	0	0	0
T259	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2065	0	0
T38	0	37	0	0
T39	987	71	0	0
T41	0	67	0	0
T42	0	52	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T86	0	32	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	52	0	0
T176	0	100	0	0
T233	0	174	0	0
T246	0	15	0	0
T248	423	0	0	0
T259	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359748	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2649	0	0
T38	747	90	0	0
T41	0	233	0	0
T42	0	117	0	0
T43	634	0	0	0
T61	498	0	0	0
T74	618	0	0	0
T86	0	1	0	0
T138	402	0	0	0
T173	0	79	0	0
T176	0	43	0	0
T192	0	109	0	0
T197	447	0	0	0
T198	505	0	0	0
T199	753	0	0	0
T200	716	0	0	0
T201	450	0	0	0
T233	0	170	0	0
T246	0	61	0	0
T259	0	88	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	35	0	0
T38	747	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	634	0	0	0
T61	498	0	0	0
T74	618	0	0	0
T86	0	1	0	0
T138	402	0	0	0
T173	0	2	0	0
T176	0	1	0	0
T192	0	2	0	0
T197	447	0	0	0
T198	505	0	0	0
T199	753	0	0	0
T200	716	0	0	0
T201	450	0	0	0
T233	0	2	0	0
T246	0	1	0	0
T259	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5341282	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5343504	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	39	0	0
T38	0	1	0	0
T39	987	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T86	0	1	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	2	0	0
T176	0	1	0	0
T233	0	2	0	0
T246	0	1	0	0
T248	423	0	0	0
T259	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	36	0	0
T38	747	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	634	0	0	0
T61	498	0	0	0
T74	618	0	0	0
T86	0	1	0	0
T138	402	0	0	0
T173	0	2	0	0
T176	0	1	0	0
T192	0	2	0	0
T197	447	0	0	0
T198	505	0	0	0
T199	753	0	0	0
T200	716	0	0	0
T201	450	0	0	0
T233	0	2	0	0
T246	0	1	0	0
T259	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	35	0	0
T38	747	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	634	0	0	0
T61	498	0	0	0
T74	618	0	0	0
T86	0	1	0	0
T138	402	0	0	0
T173	0	2	0	0
T176	0	1	0	0
T192	0	2	0	0
T197	447	0	0	0
T198	505	0	0	0
T199	753	0	0	0
T200	716	0	0	0
T201	450	0	0	0
T233	0	2	0	0
T246	0	1	0	0
T259	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	35	0	0
T38	747	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	634	0	0	0
T61	498	0	0	0
T74	618	0	0	0
T86	0	1	0	0
T138	402	0	0	0
T173	0	2	0	0
T176	0	1	0	0
T192	0	2	0	0
T197	447	0	0	0
T198	505	0	0	0
T199	753	0	0	0
T200	716	0	0	0
T201	450	0	0	0
T233	0	2	0	0
T246	0	1	0	0
T259	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2597	0	0
T38	747	89	0	0
T41	0	231	0	0
T42	0	114	0	0
T43	634	0	0	0
T61	498	0	0	0
T74	618	0	0	0
T109	0	77	0	0
T138	402	0	0	0
T173	0	76	0	0
T176	0	42	0	0
T192	0	105	0	0
T197	447	0	0	0
T198	505	0	0	0
T199	753	0	0	0
T200	716	0	0	0
T201	450	0	0	0
T233	0	167	0	0
T246	0	60	0	0
T259	0	86	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5888	0	0
T1	13850	28	0	0
T2	722	1	0	0
T3	27219	30	0	0
T4	431	2	0	0
T5	502	6	0	0
T13	8402	0	0	0
T14	4021	17	0	0
T15	403	0	0	0
T16	502	6	0	0
T17	432	2	0	0
T29	0	27	0	0
T30	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	18	0	0
T38	747	1	0	0
T42	0	1	0	0
T43	634	0	0	0
T61	498	0	0	0
T74	618	0	0	0
T86	0	1	0	0
T109	0	1	0	0
T138	402	0	0	0
T173	0	1	0	0
T176	0	1	0	0
T197	447	0	0	0
T198	505	0	0	0
T199	753	0	0	0
T200	716	0	0	0
T201	450	0	0	0
T222	0	1	0	0
T233	0	1	0	0
T246	0	1	0	0
T260	0	1	0	0