Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T37,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T37,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T37,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T37
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T37,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T37,T39
0	1	Covered	T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T37,T39
0	1	Covered	T2,T37,T39
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T37,T39
1	-	Covered	T2,T37,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T37,T39
DetectSt	168	Covered	T2,T37,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T37,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T37,T39
DebounceSt->IdleSt	163	Covered	T104,T88,T261
DetectSt->IdleSt	186	Covered	T88
DetectSt->StableSt	191	Covered	T2,T37,T39
IdleSt->DebounceSt	148	Covered	T2,T37,T39
StableSt->IdleSt	206	Covered	T2,T37,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T37,T39
0	1	Covered	T2,T37,T39
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T37,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T37,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T37,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T261
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T37,T39
DetectSt	-	-	-	-	1	-	-	Covered	T88
DetectSt	-	-	-	-	0	1	-	Covered	T2,T37,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T37,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T37,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	99	0	0
CntIncr_A	6005714	2701	0	0
CntNoWrap_A	6005714	5359724	0	0
DetectStDropOut_A	6005714	1	0	0
DetectedOut_A	6005714	5191	0	0
DetectedPulseOut_A	6005714	47	0	0
DisabledIdleSt_A	6005714	5332836	0	0
DisabledNoDetection_A	6005714	5335060	0	0
EnterDebounceSt_A	6005714	51	0	0
EnterDetectSt_A	6005714	48	0	0
EnterStableSt_A	6005714	47	0	0
PulseIsPulse_A	6005714	47	0	0
StayInStableSt	6005714	5125	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	99	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	4	0	0
T52	404	0	0	0
T173	0	2	0	0
T175	0	2	0	0
T202	0	2	0	0
T259	0	4	0	0
T262	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2701	0	0
T2	722	60	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	180	0	0
T39	0	71	0	0
T40	0	93	0	0
T42	0	52	0	0
T52	404	0	0	0
T173	0	87	0	0
T175	0	70	0	0
T202	0	90	0	0
T259	0	54	0	0
T262	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359724	0	0
T1	13850	13425	0	0
T2	722	319	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1	0	0
T88	18336	1	0	0
T132	59059	0	0	0
T238	494	0	0	0
T239	493	0	0	0
T240	20420	0	0	0
T241	502	0	0	0
T242	513	0	0	0
T243	584	0	0	0
T244	403	0	0	0
T245	30972	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5191	0	0
T2	722	41	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	255	0	0
T39	0	43	0	0
T40	0	498	0	0
T42	0	186	0	0
T52	404	0	0	0
T173	0	121	0	0
T175	0	144	0	0
T202	0	38	0	0
T259	0	78	0	0
T262	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	47	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T52	404	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T202	0	1	0	0
T259	0	2	0	0
T262	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5332836	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5335060	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	51	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T52	404	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T202	0	1	0	0
T259	0	2	0	0
T262	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	48	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T52	404	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T202	0	1	0	0
T259	0	2	0	0
T262	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	47	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T52	404	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T202	0	1	0	0
T259	0	2	0	0
T262	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	47	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T52	404	0	0	0
T173	0	1	0	0
T175	0	1	0	0
T202	0	1	0	0
T259	0	2	0	0
T262	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5125	0	0
T2	722	40	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	252	0	0
T39	0	42	0	0
T40	0	496	0	0
T42	0	183	0	0
T52	404	0	0	0
T173	0	119	0	0
T175	0	143	0	0
T202	0	36	0	0
T259	0	75	0	0
T262	0	56	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	27	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T52	404	0	0	0
T86	0	1	0	0
T175	0	1	0	0
T203	0	1	0	0
T207	0	1	0	0
T259	0	1	0	0
T262	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T36
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T38
0	1	Covered	T36,T38,T41
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T36,T38
1	-	Covered	T36,T38,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T36,T38
DetectSt	168	Covered	T2,T36,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T36,T38
DebounceSt->IdleSt	163	Covered	T86,T104,T234
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T36,T38
IdleSt->DebounceSt	148	Covered	T2,T36,T38
StableSt->IdleSt	206	Covered	T36,T38,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T36,T38
0	1	Covered	T2,T36,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T36,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T36,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T86
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T36,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T41
StableSt	-	-	-	-	-	-	0	Covered	T2,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	82	0	0
CntIncr_A	6005714	29684	0	0
CntNoWrap_A	6005714	5359741	0	0
DetectStDropOut_A	6005714	0	0	0
DetectedOut_A	6005714	2882	0	0
DetectedPulseOut_A	6005714	40	0	0
DisabledIdleSt_A	6005714	5232610	0	0
DisabledNoDetection_A	6005714	5234829	0	0
EnterDebounceSt_A	6005714	43	0	0
EnterDetectSt_A	6005714	40	0	0
EnterStableSt_A	6005714	40	0	0
PulseIsPulse_A	6005714	40	0	0
StayInStableSt	6005714	2821	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	5924	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	82	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	4	0	0
T38	0	4	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T52	404	0	0	0
T233	0	2	0	0
T259	0	2	0	0
T263	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	29684	0	0
T2	722	60	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	84	0	0
T38	0	74	0	0
T40	0	75	0	0
T41	0	67	0	0
T42	0	26	0	0
T43	0	69	0	0
T52	404	0	0	0
T233	0	87	0	0
T259	0	27	0	0
T263	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359741	0	0
T1	13850	13425	0	0
T2	722	319	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2882	0	0
T2	722	90	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	82	0	0
T38	0	93	0	0
T40	0	172	0	0
T41	0	127	0	0
T42	0	3	0	0
T43	0	39	0	0
T52	404	0	0	0
T233	0	42	0	0
T259	0	22	0	0
T263	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T52	404	0	0	0
T233	0	1	0	0
T259	0	1	0	0
T263	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5232610	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5234829	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	43	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T52	404	0	0	0
T233	0	1	0	0
T259	0	1	0	0
T263	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T52	404	0	0	0
T233	0	1	0	0
T259	0	1	0	0
T263	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T52	404	0	0	0
T233	0	1	0	0
T259	0	1	0	0
T263	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T52	404	0	0	0
T233	0	1	0	0
T259	0	1	0	0
T263	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2821	0	0
T2	722	88	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	79	0	0
T38	0	91	0	0
T40	0	170	0	0
T41	0	126	0	0
T42	0	2	0	0
T43	0	37	0	0
T52	404	0	0	0
T233	0	41	0	0
T259	0	21	0	0
T263	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5924	0	0
T1	13850	28	0	0
T2	722	1	0	0
T3	27219	30	0	0
T4	431	2	0	0
T5	502	6	0	0
T13	8402	0	0	0
T14	4021	12	0	0
T15	403	0	0	0
T16	502	3	0	0
T17	432	5	0	0
T29	0	22	0	0
T30	0	33	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	18	0	0
T36	9846	1	0	0
T37	936	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T205	0	1	0	0
T218	0	1	0	0
T233	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T259	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T7,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T36
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T7,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T36
0	1	Not Covered
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T36
0	1	Covered	T36,T41,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T36
1	-	Covered	T36,T41,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T36
DetectSt	168	Covered	T2,T7,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T36
DebounceSt->IdleSt	163	Covered	T38,T104,T196
DetectSt->IdleSt	186	Covered	T55
DetectSt->StableSt	191	Covered	T2,T7,T36
IdleSt->DebounceSt	148	Covered	T2,T7,T36
StableSt->IdleSt	206	Covered	T36,T41,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T36
0	1	Covered	T2,T7,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T196,T261
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T36
DetectSt	-	-	-	-	1	-	-	Covered	T55
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T41,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	109	0	0
CntIncr_A	6005714	3263	0	0
CntNoWrap_A	6005714	5359714	0	0
DetectStDropOut_A	6005714	0	0	0
DetectedOut_A	6005714	5120	0	0
DetectedPulseOut_A	6005714	51	0	0
DisabledIdleSt_A	6005714	5342940	0	0
DisabledNoDetection_A	6005714	5345166	0	0
EnterDebounceSt_A	6005714	57	0	0
EnterDetectSt_A	6005714	52	0	0
EnterStableSt_A	6005714	51	0	0
PulseIsPulse_A	6005714	51	0	0
StayInStableSt	6005714	5041	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	109	0	0
T2	722	2	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	2	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	4	0	0
T38	0	4	0	0
T40	0	4	0	0
T41	0	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T52	404	0	0	0
T173	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3263	0	0
T2	722	60	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	96	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	84	0	0
T38	0	111	0	0
T40	0	186	0	0
T41	0	134	0	0
T42	0	26	0	0
T43	0	69	0	0
T44	0	43	0	0
T52	404	0	0	0
T173	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359714	0	0
T1	13850	13425	0	0
T2	722	319	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5120	0	0
T2	722	191	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	46	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	208	0	0
T38	0	93	0	0
T40	0	300	0	0
T41	0	147	0	0
T42	0	108	0	0
T43	0	155	0	0
T44	0	233	0	0
T52	404	0	0	0
T173	0	120	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	51	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T173	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5342940	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5345166	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	57	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	3	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	52	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T173	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	51	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T173	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	51	0	0
T2	722	1	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	1	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	404	0	0	0
T173	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5041	0	0
T2	722	189	0	0
T3	27219	0	0	0
T6	1498	0	0	0
T7	0	44	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T28	453	0	0	0
T36	0	205	0	0
T38	0	91	0	0
T40	0	297	0	0
T41	0	144	0	0
T42	0	107	0	0
T43	0	153	0	0
T44	0	231	0	0
T52	404	0	0	0
T173	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	23	0	0
T36	9846	1	0	0
T37	936	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T109	0	1	0	0
T112	0	1	0	0
T118	19861	0	0	0
T173	0	1	0	0
T177	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T196	0	1	0	0
T264	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T39,T38,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T39,T38,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T39,T38,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T37,T39
1	0	Covered	T1,T4,T5
1	1	Covered	T39,T38,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T38,T40
0	1	Covered	T39,T223
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T38,T40
0	1	Covered	T39,T38,T259
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T39,T38,T40
1	-	Covered	T39,T38,T259

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T39,T38,T40
DetectSt	168	Covered	T39,T38,T40
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T39,T38,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T39,T38,T40
DebounceSt->IdleSt	163	Covered	T104,T234,T206
DetectSt->IdleSt	186	Covered	T39,T223
DetectSt->StableSt	191	Covered	T39,T38,T40
IdleSt->DebounceSt	148	Covered	T39,T38,T40
StableSt->IdleSt	206	Covered	T39,T38,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T39,T38,T40
0	1	Covered	T39,T38,T40
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T38,T40
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T39,T38,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T38,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T206
DebounceSt	-	0	0	-	-	-	-	Covered	T39,T38,T40
DetectSt	-	-	-	-	1	-	-	Covered	T39,T223
DetectSt	-	-	-	-	0	1	-	Covered	T39,T38,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T38,T259
StableSt	-	-	-	-	-	-	0	Covered	T39,T38,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	76	0	0
CntIncr_A	6005714	2187	0	0
CntNoWrap_A	6005714	5359747	0	0
DetectStDropOut_A	6005714	2	0	0
DetectedOut_A	6005714	2722	0	0
DetectedPulseOut_A	6005714	35	0	0
DisabledIdleSt_A	6005714	5330845	0	0
DisabledNoDetection_A	6005714	5333062	0	0
EnterDebounceSt_A	6005714	40	0	0
EnterDetectSt_A	6005714	37	0	0
EnterStableSt_A	6005714	35	0	0
PulseIsPulse_A	6005714	35	0	0
StayInStableSt	6005714	2670	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	5908	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	76	0	0
T38	0	4	0	0
T39	987	4	0	0
T40	0	2	0	0
T42	0	2	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T55	0	2	0	0
T104	0	1	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	2	0	0
T218	0	2	0	0
T247	0	2	0	0
T248	423	0	0	0
T259	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2187	0	0
T38	0	74	0	0
T39	987	142	0	0
T40	0	75	0	0
T42	0	26	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T55	0	46	0	0
T104	0	29	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	87	0	0
T218	0	19	0	0
T247	0	50	0	0
T248	423	0	0	0
T259	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359747	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2	0	0
T39	987	1	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T223	0	1	0	0
T248	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2722	0	0
T38	0	84	0	0
T39	987	155	0	0
T40	0	171	0	0
T42	0	41	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T55	0	1	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	389	0	0
T205	0	132	0	0
T218	0	43	0	0
T247	0	23	0	0
T248	423	0	0	0
T259	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	35	0	0
T38	0	2	0	0
T39	987	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T55	0	1	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	1	0	0
T205	0	1	0	0
T218	0	1	0	0
T247	0	1	0	0
T248	423	0	0	0
T259	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5330845	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5333062	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T38	0	2	0	0
T39	987	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T55	0	1	0	0
T104	0	1	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	1	0	0
T218	0	1	0	0
T247	0	1	0	0
T248	423	0	0	0
T259	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	37	0	0
T38	0	2	0	0
T39	987	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T55	0	1	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	1	0	0
T205	0	1	0	0
T218	0	1	0	0
T247	0	1	0	0
T248	423	0	0	0
T259	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	35	0	0
T38	0	2	0	0
T39	987	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T55	0	1	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	1	0	0
T205	0	1	0	0
T218	0	1	0	0
T247	0	1	0	0
T248	423	0	0	0
T259	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	35	0	0
T38	0	2	0	0
T39	987	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T55	0	1	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	1	0	0
T205	0	1	0	0
T218	0	1	0	0
T247	0	1	0	0
T248	423	0	0	0
T259	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2670	0	0
T38	0	82	0	0
T39	987	154	0	0
T40	0	169	0	0
T42	0	39	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T173	0	387	0	0
T196	0	169	0	0
T205	0	130	0	0
T218	0	41	0	0
T247	0	21	0	0
T248	423	0	0	0
T259	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5908	0	0
T1	13850	25	0	0
T2	722	0	0	0
T3	27219	27	0	0
T4	431	3	0	0
T5	502	5	0	0
T8	0	13	0	0
T13	8402	0	0	0
T14	4021	17	0	0
T15	403	0	0	0
T16	502	7	0	0
T17	432	1	0	0
T29	0	24	0	0
T30	0	26	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	17	0	0
T38	0	2	0	0
T39	987	1	0	0
T47	676	0	0	0
T48	604	0	0	0
T49	667	0	0	0
T50	730	0	0	0
T51	722	0	0	0
T119	11322	0	0	0
T120	5116	0	0	0
T143	8992	0	0	0
T196	0	1	0	0
T206	0	2	0	0
T219	0	1	0	0
T221	0	2	0	0
T222	0	1	0	0
T236	0	1	0	0
T248	423	0	0	0
T259	0	1	0	0
T265	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T40,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T43,T40,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T40,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T43,T40,T44
1	0	Covered	T1,T4,T5
1	1	Covered	T43,T40,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T40,T44
0	1	Covered	T111,T112
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T40,T44
0	1	Covered	T40,T44,T173
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T40,T44
1	-	Covered	T40,T44,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T43,T40,T44
DetectSt	168	Covered	T43,T40,T44
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T43,T40,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T40,T44
DebounceSt->IdleSt	163	Covered	T176,T104,T223
DetectSt->IdleSt	186	Covered	T111,T112
DetectSt->StableSt	191	Covered	T43,T40,T44
IdleSt->DebounceSt	148	Covered	T43,T40,T44
StableSt->IdleSt	206	Covered	T40,T44,T173

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T43,T40,T44
0	1	Covered	T43,T40,T44
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T40,T44
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T43,T40,T44
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T40,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T176,T223,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T43,T40,T44
DetectSt	-	-	-	-	1	-	-	Covered	T111,T112
DetectSt	-	-	-	-	0	1	-	Covered	T43,T40,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T44,T173
StableSt	-	-	-	-	-	-	0	Covered	T43,T40,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	138	0	0
CntIncr_A	6005714	68970	0	0
CntNoWrap_A	6005714	5359685	0	0
DetectStDropOut_A	6005714	2	0	0
DetectedOut_A	6005714	32342	0	0
DetectedPulseOut_A	6005714	65	0	0
DisabledIdleSt_A	6005714	5220496	0	0
DisabledNoDetection_A	6005714	5222710	0	0
EnterDebounceSt_A	6005714	71	0	0
EnterDetectSt_A	6005714	67	0	0
EnterStableSt_A	6005714	65	0	0
PulseIsPulse_A	6005714	65	0	0
StayInStableSt	6005714	32248	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	138	0	0
T40	0	8	0	0
T41	777	0	0	0
T43	634	2	0	0
T44	0	2	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	8	0	0
T175	0	4	0	0
T176	0	3	0	0
T177	0	4	0	0
T208	0	2	0	0
T233	0	4	0	0
T259	0	2	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	68970	0	0
T40	0	336	0	0
T41	777	0	0	0
T43	634	69	0	0
T44	0	43	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	226	0	0
T175	0	140	0	0
T176	0	200	0	0
T177	0	106	0	0
T208	0	33	0	0
T233	0	174	0	0
T259	0	27	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359685	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2	0	0
T111	111275	1	0	0
T112	0	1	0	0
T247	4910	0	0	0
T269	522	0	0	0
T270	20118	0	0	0
T271	2286	0	0	0
T272	502	0	0	0
T273	729	0	0	0
T274	422	0	0	0
T275	526	0	0	0
T276	6759	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	32342	0	0
T40	0	357	0	0
T41	777	0	0	0
T43	634	39	0	0
T44	0	104	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	400	0	0
T175	0	72	0	0
T176	0	39	0	0
T177	0	283	0	0
T208	0	44	0	0
T233	0	184	0	0
T259	0	203	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	65	0	0
T40	0	4	0	0
T41	777	0	0	0
T43	634	1	0	0
T44	0	1	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	4	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	2	0	0
T208	0	1	0	0
T233	0	2	0	0
T259	0	1	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5220496	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5222710	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	71	0	0
T40	0	4	0	0
T41	777	0	0	0
T43	634	1	0	0
T44	0	1	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	4	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	0	2	0	0
T208	0	1	0	0
T233	0	2	0	0
T259	0	1	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	67	0	0
T40	0	4	0	0
T41	777	0	0	0
T43	634	1	0	0
T44	0	1	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	4	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	2	0	0
T208	0	1	0	0
T233	0	2	0	0
T259	0	1	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	65	0	0
T40	0	4	0	0
T41	777	0	0	0
T43	634	1	0	0
T44	0	1	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	4	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	2	0	0
T208	0	1	0	0
T233	0	2	0	0
T259	0	1	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	65	0	0
T40	0	4	0	0
T41	777	0	0	0
T43	634	1	0	0
T44	0	1	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	4	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	2	0	0
T208	0	1	0	0
T233	0	2	0	0
T259	0	1	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	32248	0	0
T40	0	352	0	0
T41	777	0	0	0
T43	634	37	0	0
T44	0	103	0	0
T103	15890	0	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T144	21768	0	0	0
T173	0	395	0	0
T175	0	69	0	0
T176	0	37	0	0
T177	0	280	0	0
T208	0	42	0	0
T233	0	181	0	0
T259	0	201	0	0
T266	10754	0	0	0
T267	524	0	0	0
T268	408	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	35	0	0
T40	54664	3	0	0
T44	0	1	0	0
T63	491	0	0	0
T86	0	1	0	0
T154	591	0	0	0
T155	522	0	0	0
T156	412	0	0	0
T157	508	0	0	0
T158	34123	0	0	0
T159	5317	0	0	0
T160	761	0	0	0
T173	0	3	0	0
T175	0	1	0	0
T177	0	1	0	0
T195	0	2	0	0
T203	0	1	0	0
T233	0	1	0	0
T246	0	2	0	0
T277	425	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T36,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T36,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T36,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T36
1	0	Covered	T1,T4,T5
1	1	Covered	T36,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T36,T37,T42
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T37,T38
1	-	Covered	T36,T37,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T37,T38
DetectSt	168	Covered	T36,T37,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T36,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T37,T38
DebounceSt->IdleSt	163	Covered	T104,T113
DetectSt->IdleSt	186	Covered	T109
DetectSt->StableSt	191	Covered	T36,T37,T38
IdleSt->DebounceSt	148	Covered	T36,T37,T38
StableSt->IdleSt	206	Covered	T36,T37,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T37,T38
0	1	Covered	T36,T37,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T113
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T109
DetectSt	-	-	-	-	0	1	-	Covered	T36,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T42
StableSt	-	-	-	-	-	-	0	Covered	T36,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	84	0	0
CntIncr_A	6005714	2231	0	0
CntNoWrap_A	6005714	5359739	0	0
DetectStDropOut_A	6005714	1	0	0
DetectedOut_A	6005714	2934	0	0
DetectedPulseOut_A	6005714	40	0	0
DisabledIdleSt_A	6005714	5338945	0	0
DisabledNoDetection_A	6005714	5341159	0	0
EnterDebounceSt_A	6005714	43	0	0
EnterDetectSt_A	6005714	41	0	0
EnterStableSt_A	6005714	40	0	0
PulseIsPulse_A	6005714	40	0	0
StayInStableSt	6005714	2872	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6005714	6727	0	0
gen_low_level_sva.LowLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	84	0	0
T36	9846	2	0	0
T37	936	4	0	0
T38	0	2	0	0
T42	0	4	0	0
T44	0	2	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	2	0	0
T177	0	2	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	2	0	0
T233	0	2	0	0
T246	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2231	0	0
T36	9846	42	0	0
T37	936	180	0	0
T38	0	37	0	0
T42	0	52	0	0
T44	0	43	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	70	0	0
T177	0	79	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	16	0	0
T233	0	87	0	0
T246	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359739	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1	0	0
T109	164219	1	0	0
T278	427	0	0	0
T279	523	0	0	0
T280	492	0	0	0
T281	23272	0	0	0
T282	738	0	0	0
T283	490	0	0	0
T284	1317	0	0	0
T285	14509	0	0	0
T286	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2934	0	0
T36	9846	113	0	0
T37	936	79	0	0
T38	0	171	0	0
T42	0	45	0	0
T44	0	86	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	113	0	0
T177	0	49	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	89	0	0
T233	0	86	0	0
T246	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T36	9846	1	0	0
T37	936	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	1	0	0
T177	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	1	0	0
T233	0	1	0	0
T246	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5338945	0	0
T1	13850	13425	0	0
T2	722	4	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5341159	0	0
T1	13850	13429	0	0
T2	722	4	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	43	0	0
T36	9846	1	0	0
T37	936	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	1	0	0
T177	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	1	0	0
T233	0	1	0	0
T246	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	41	0	0
T36	9846	1	0	0
T37	936	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	1	0	0
T177	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	1	0	0
T233	0	1	0	0
T246	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T36	9846	1	0	0
T37	936	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	1	0	0
T177	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	1	0	0
T233	0	1	0	0
T246	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40	0	0
T36	9846	1	0	0
T37	936	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	1	0	0
T177	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	1	0	0
T233	0	1	0	0
T246	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2872	0	0
T36	9846	112	0	0
T37	936	76	0	0
T38	0	169	0	0
T42	0	42	0	0
T44	0	84	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T175	0	112	0	0
T177	0	47	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T207	0	87	0	0
T233	0	85	0	0
T246	0	87	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	6727	0	0
T1	13850	29	0	0
T2	722	0	0	0
T3	27219	26	0	0
T4	431	4	0	0
T5	502	2	0	0
T6	0	6	0	0
T13	8402	0	0	0
T14	4021	12	0	0
T15	403	0	0	0
T16	502	6	0	0
T17	432	2	0	0
T25	0	3	0	0
T26	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	17	0	0
T36	9846	1	0	0
T37	936	1	0	0
T42	0	1	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T109	0	1	0	0
T118	19861	0	0	0
T174	0	1	0	0
T175	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T182	407	0	0	0
T195	0	2	0	0
T196	0	1	0	0
T233	0	1	0	0
T246	0	1	0	0