Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T29
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T29
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T28
0	1	Covered	T3,T29,T30
1	0	Covered	T3,T12,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T9
0	1	Covered	T1,T9,T10
1	0	Covered	T104,T55,T287

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T9
1	-	Covered	T1,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T28
DetectSt	168	Covered	T1,T3,T28
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T28,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T28
DebounceSt->IdleSt	163	Covered	T117,T288,T289
DetectSt->IdleSt	186	Covered	T3,T29,T30
DetectSt->StableSt	191	Covered	T1,T28,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T28
StableSt->IdleSt	206	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T28
0	1	Covered	T1,T3,T28
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T28
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T117,T288,T289
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T28
DetectSt	-	-	-	-	1	-	-	Covered	T3,T29,T30
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T28
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	2631	0	0
CntIncr_A	6005714	92155	0	0
CntNoWrap_A	6005714	5357192	0	0
DetectStDropOut_A	6005714	424	0	0
DetectedOut_A	6005714	72393	0	0
DetectedPulseOut_A	6005714	727	0	0
DisabledIdleSt_A	6005714	4906324	0	0
DisabledNoDetection_A	6005714	4908411	0	0
EnterDebounceSt_A	6005714	1334	0	0
EnterDetectSt_A	6005714	1298	0	0
EnterStableSt_A	6005714	727	0	0
PulseIsPulse_A	6005714	727	0	0
StayInStableSt	6005714	71571	0	0
gen_high_event_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	611	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2631	0	0
T1	13850	48	0	0
T2	722	0	0	0
T3	27219	20	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	10	0	0
T10	0	48	0	0
T12	0	6	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	2	0	0
T29	0	50	0	0
T30	0	66	0	0
T46	0	22	0	0
T56	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	92155	0	0
T1	13850	1248	0	0
T2	722	0	0	0
T3	27219	765	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	355	0	0
T10	0	1200	0	0
T12	0	144	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	21	0	0
T29	0	1299	0	0
T30	0	2271	0	0
T46	0	535	0	0
T56	0	546	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5357192	0	0
T1	13850	13377	0	0
T2	722	321	0	0
T3	27219	26749	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	424	0	0
T3	27219	4	0	0
T6	1498	0	0	0
T7	670	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	25	0	0
T30	0	33	0	0
T46	0	11	0	0
T52	404	0	0	0
T53	964	0	0	0
T120	0	7	0	0
T121	0	29	0	0
T159	0	23	0	0
T266	0	10	0	0
T290	0	4	0	0
T291	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	72393	0	0
T1	13850	867	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	577	0	0
T10	0	3306	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	27	0	0
T56	0	989	0	0
T107	0	51	0	0
T117	0	184	0	0
T119	0	1083	0	0
T137	0	8190	0	0
T143	0	1183	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	727	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T10	0	24	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	1	0	0
T56	0	13	0	0
T107	0	8	0	0
T117	0	9	0	0
T119	0	11	0	0
T137	0	26	0	0
T143	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4906324	0	0
T1	13850	9260	0	0
T2	722	321	0	0
T3	27219	22731	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4908411	0	0
T1	13850	9261	0	0
T2	722	322	0	0
T3	27219	22740	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1334	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	10	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T10	0	24	0	0
T12	0	3	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	1	0	0
T29	0	25	0	0
T30	0	33	0	0
T46	0	11	0	0
T56	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1298	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	10	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T10	0	24	0	0
T12	0	3	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	1	0	0
T29	0	25	0	0
T30	0	33	0	0
T46	0	11	0	0
T56	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	727	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T10	0	24	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	1	0	0
T56	0	13	0	0
T107	0	8	0	0
T117	0	9	0	0
T119	0	11	0	0
T137	0	26	0	0
T143	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	727	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T10	0	24	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	1	0	0
T56	0	13	0	0
T107	0	8	0	0
T117	0	9	0	0
T119	0	11	0	0
T137	0	26	0	0
T143	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	71571	0	0
T1	13850	841	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	571	0	0
T10	0	3274	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T28	0	25	0	0
T56	0	973	0	0
T107	0	43	0	0
T117	0	175	0	0
T119	0	1071	0	0
T137	0	8158	0	0
T143	0	1162	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	611	0	0
T1	13850	22	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	4	0	0
T10	0	16	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	10	0	0
T107	0	8	0	0
T117	0	9	0	0
T119	0	10	0	0
T137	0	20	0	0
T143	0	21	0	0
T292	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T28
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T28
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T9
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T10
0	1	Covered	T103,T35,T122
1	0	Covered	T104,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T10
0	1	Covered	T1,T10,T11
1	0	Covered	T104,T55,T105

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T10
1	-	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T10
DetectSt	168	Covered	T1,T9,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T10
DebounceSt->IdleSt	163	Covered	T11,T36,T118
DetectSt->IdleSt	186	Covered	T103,T35,T122
DetectSt->StableSt	191	Covered	T1,T9,T10
IdleSt->DebounceSt	148	Covered	T1,T9,T10
StableSt->IdleSt	206	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T10
0	1	Covered	T1,T9,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T36,T118
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T103,T35,T122
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	929	0	0
CntIncr_A	6005714	47385	0	0
CntNoWrap_A	6005714	5358894	0	0
DetectStDropOut_A	6005714	56	0	0
DetectedOut_A	6005714	16391	0	0
DetectedPulseOut_A	6005714	360	0	0
DisabledIdleSt_A	6005714	4990572	0	0
DisabledNoDetection_A	6005714	4992125	0	0
EnterDebounceSt_A	6005714	511	0	0
EnterDetectSt_A	6005714	420	0	0
EnterStableSt_A	6005714	360	0	0
PulseIsPulse_A	6005714	360	0	0
StayInStableSt	6005714	16022	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	347	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	929	0	0
T1	13850	4	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2	0	0
T10	0	16	0	0
T11	0	14	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	2	0	0
T34	0	6	0	0
T36	0	1	0	0
T56	0	4	0	0
T118	0	9	0	0
T119	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	47385	0	0
T1	13850	120	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	115	0	0
T10	0	496	0	0
T11	0	524	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	111	0	0
T34	0	369	0	0
T36	0	20	0	0
T56	0	112	0	0
T118	0	817	0	0
T119	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5358894	0	0
T1	13850	13421	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	56	0	0
T22	902	0	0	0
T35	30252	2	0	0
T57	792	0	0	0
T58	3487	0	0	0
T62	499	0	0	0
T103	15890	6	0	0
T122	0	8	0	0
T123	0	4	0	0
T125	0	1	0	0
T127	0	2	0	0
T128	0	2	0	0
T129	0	4	0	0
T130	0	9	0	0
T131	0	8	0	0
T139	524	0	0	0
T140	23702	0	0	0
T141	22054	0	0	0
T142	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	16391	0	0
T1	13850	102	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	46	0	0
T10	0	786	0	0
T11	0	265	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	29	0	0
T34	0	25	0	0
T56	0	163	0	0
T118	0	25	0	0
T119	0	81	0	0
T137	0	619	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	360	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	1	0	0
T10	0	8	0	0
T11	0	6	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T56	0	2	0	0
T118	0	4	0	0
T119	0	1	0	0
T137	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4990572	0	0
T1	13850	12560	0	0
T2	722	321	0	0
T3	27219	26769	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4992125	0	0
T1	13850	12562	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	511	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	1	0	0
T10	0	8	0	0
T11	0	8	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T36	0	1	0	0
T56	0	2	0	0
T118	0	5	0	0
T119	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	420	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	1	0	0
T10	0	8	0	0
T11	0	6	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T56	0	2	0	0
T118	0	4	0	0
T119	0	1	0	0
T137	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	360	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	1	0	0
T10	0	8	0	0
T11	0	6	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T56	0	2	0	0
T118	0	4	0	0
T119	0	1	0	0
T137	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	360	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	1	0	0
T10	0	8	0	0
T11	0	6	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T56	0	2	0	0
T118	0	4	0	0
T119	0	1	0	0
T137	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	16022	0	0
T1	13850	100	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	44	0	0
T10	0	778	0	0
T11	0	259	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T56	0	160	0	0
T118	0	21	0	0
T119	0	79	0	0
T137	0	615	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	347	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	0	0	0
T4	431	0	0	0
T5	502	0	0	0
T10	0	8	0	0
T11	0	6	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T40	0	9	0	0
T56	0	1	0	0
T118	0	4	0	0
T141	0	2	0	0
T144	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T29
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T29
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T29
0	1	Covered	T29,T30,T10
1	0	Covered	T10,T194,T119

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Covered	T293,T245

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T29
DetectSt	168	Covered	T1,T3,T29
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T29
DebounceSt->IdleSt	163	Covered	T117,T288,T289
DetectSt->IdleSt	186	Covered	T29,T30,T10
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T29
StableSt->IdleSt	206	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T29
0	1	Covered	T1,T3,T29
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T29
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T117,T288,T289
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T29
DetectSt	-	-	-	-	1	-	-	Covered	T29,T30,T10
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T29
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	2963	0	0
CntIncr_A	6005714	105847	0	0
CntNoWrap_A	6005714	5356860	0	0
DetectStDropOut_A	6005714	508	0	0
DetectedOut_A	6005714	70853	0	0
DetectedPulseOut_A	6005714	739	0	0
DisabledIdleSt_A	6005714	4912289	0	0
DisabledNoDetection_A	6005714	4914396	0	0
EnterDebounceSt_A	6005714	1503	0	0
EnterDetectSt_A	6005714	1461	0	0
EnterStableSt_A	6005714	739	0	0
PulseIsPulse_A	6005714	739	0	0
StayInStableSt	6005714	70039	0	0
gen_high_event_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	645	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	2963	0	0
T1	13850	48	0	0
T2	722	0	0	0
T3	27219	26	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	4	0	0
T10	0	52	0	0
T12	0	40	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	6	0	0
T30	0	34	0	0
T46	0	58	0	0
T56	0	44	0	0
T75	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	105847	0	0
T1	13850	1344	0	0
T2	722	0	0	0
T3	27219	780	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	158	0	0
T10	0	1566	0	0
T12	0	860	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	153	0	0
T30	0	1172	0	0
T46	0	1423	0	0
T56	0	1628	0	0
T75	0	1210	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5356860	0	0
T1	13850	13377	0	0
T2	722	321	0	0
T3	27219	26743	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	508	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T10	0	15	0	0
T23	497	0	0	0
T29	5216	3	0	0
T30	6066	17	0	0
T46	0	29	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T67	425	0	0	0
T68	421	0	0	0
T119	0	8	0	0
T120	0	24	0	0
T121	0	9	0	0
T159	0	27	0	0
T194	0	7	0	0
T290	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	70853	0	0
T1	13850	1003	0	0
T2	722	0	0	0
T3	27219	1578	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	18	0	0
T12	0	1865	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	1964	0	0
T75	0	1520	0	0
T107	0	779	0	0
T137	0	1744	0	0
T143	0	978	0	0
T266	0	4193	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	739	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	13	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2	0	0
T12	0	20	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	22	0	0
T75	0	22	0	0
T107	0	6	0	0
T137	0	12	0	0
T143	0	25	0	0
T266	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4912289	0	0
T1	13850	9027	0	0
T2	722	321	0	0
T3	27219	21367	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4914396	0	0
T1	13850	9027	0	0
T2	722	322	0	0
T3	27219	21371	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1503	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	13	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2	0	0
T10	0	26	0	0
T12	0	20	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	3	0	0
T30	0	17	0	0
T46	0	29	0	0
T56	0	22	0	0
T75	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1461	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	13	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2	0	0
T10	0	26	0	0
T12	0	20	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	3	0	0
T30	0	17	0	0
T46	0	29	0	0
T56	0	22	0	0
T75	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	739	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	13	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2	0	0
T12	0	20	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	22	0	0
T75	0	22	0	0
T107	0	6	0	0
T137	0	12	0	0
T143	0	25	0	0
T266	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	739	0	0
T1	13850	24	0	0
T2	722	0	0	0
T3	27219	13	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2	0	0
T12	0	20	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	22	0	0
T75	0	22	0	0
T107	0	6	0	0
T137	0	12	0	0
T143	0	25	0	0
T266	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	70039	0	0
T1	13850	976	0	0
T2	722	0	0	0
T3	27219	1560	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	16	0	0
T12	0	1838	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	1937	0	0
T75	0	1494	0	0
T107	0	773	0	0
T137	0	1731	0	0
T143	0	952	0	0
T266	0	4181	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	645	0	0
T1	13850	21	0	0
T2	722	0	0	0
T3	27219	8	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2	0	0
T12	0	13	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	17	0	0
T75	0	18	0	0
T107	0	6	0	0
T137	0	11	0	0
T143	0	24	0	0
T266	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T29
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T29
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T33,T103,T35
1	0	Covered	T104,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
1	0	Covered	T104,T55,T294

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T11
1	-	Covered	T1,T3,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T1,T3,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T11
DebounceSt->IdleSt	163	Covered	T11,T56,T118
DetectSt->IdleSt	186	Covered	T33,T103,T35
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T1,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T56,T118
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T33,T103,T35
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	853	0	0
CntIncr_A	6005714	47301	0	0
CntNoWrap_A	6005714	5358970	0	0
DetectStDropOut_A	6005714	68	0	0
DetectedOut_A	6005714	16212	0	0
DetectedPulseOut_A	6005714	332	0	0
DisabledIdleSt_A	6005714	4998800	0	0
DisabledNoDetection_A	6005714	5000440	0	0
EnterDebounceSt_A	6005714	449	0	0
EnterDetectSt_A	6005714	404	0	0
EnterStableSt_A	6005714	332	0	0
PulseIsPulse_A	6005714	332	0	0
StayInStableSt	6005714	15862	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	307	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	853	0	0
T1	13850	6	0	0
T2	722	0	0	0
T3	27219	10	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	21	0	0
T12	0	14	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	4	0	0
T34	0	8	0	0
T56	0	9	0	0
T75	0	6	0	0
T118	0	9	0	0
T143	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	47301	0	0
T1	13850	126	0	0
T2	722	0	0	0
T3	27219	440	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	903	0	0
T12	0	238	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	280	0	0
T34	0	316	0	0
T56	0	246	0	0
T75	0	234	0	0
T118	0	549	0	0
T143	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5358970	0	0
T1	13850	13419	0	0
T2	722	321	0	0
T3	27219	26759	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	68	0	0
T33	16985	2	0	0
T35	0	6	0	0
T36	9846	0	0	0
T37	936	0	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T103	0	3	0	0
T118	19861	0	0	0
T129	0	1	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T295	0	9	0	0
T296	0	2	0	0
T297	0	3	0	0
T298	0	13	0	0
T299	0	2	0	0
T300	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	16212	0	0
T1	13850	208	0	0
T2	722	0	0	0
T3	27219	195	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	281	0	0
T12	0	495	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T34	0	209	0	0
T56	0	341	0	0
T75	0	186	0	0
T118	0	294	0	0
T137	0	347	0	0
T143	0	58	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	332	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	5	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	9	0	0
T12	0	7	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T34	0	4	0	0
T56	0	4	0	0
T75	0	3	0	0
T118	0	4	0	0
T137	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4998800	0	0
T1	13850	12425	0	0
T2	722	321	0	0
T3	27219	25196	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5000440	0	0
T1	13850	12426	0	0
T2	722	322	0	0
T3	27219	25201	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	449	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	5	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	12	0	0
T12	0	7	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T56	0	5	0	0
T75	0	3	0	0
T118	0	5	0	0
T143	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	404	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	5	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	9	0	0
T12	0	7	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T56	0	4	0	0
T75	0	3	0	0
T118	0	4	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	332	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	5	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	9	0	0
T12	0	7	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T34	0	4	0	0
T56	0	4	0	0
T75	0	3	0	0
T118	0	4	0	0
T137	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	332	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	5	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	9	0	0
T12	0	7	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T34	0	4	0	0
T56	0	4	0	0
T75	0	3	0	0
T118	0	4	0	0
T137	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	15862	0	0
T1	13850	205	0	0
T2	722	0	0	0
T3	27219	190	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	272	0	0
T12	0	482	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T34	0	205	0	0
T56	0	337	0	0
T75	0	183	0	0
T118	0	290	0	0
T137	0	346	0	0
T143	0	56	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	307	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	5	0	0
T4	431	0	0	0
T5	502	0	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T34	0	4	0	0
T56	0	4	0	0
T75	0	3	0	0
T118	0	4	0	0
T137	0	1	0	0
T266	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T29
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T29
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T29
0	1	Covered	T29,T30,T9
1	0	Covered	T9,T10,T194

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Covered	T1,T3,T12
1	0	Covered	T107,T108,T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T12
1	-	Covered	T1,T3,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T29
DetectSt	168	Covered	T1,T3,T29
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T29
DebounceSt->IdleSt	163	Covered	T117,T288,T289
DetectSt->IdleSt	186	Covered	T29,T30,T9
DetectSt->StableSt	191	Covered	T1,T3,T12
IdleSt->DebounceSt	148	Covered	T1,T3,T29
StableSt->IdleSt	206	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T29
0	1	Covered	T1,T3,T29
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T29
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T117,T288,T289
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T29
DetectSt	-	-	-	-	1	-	-	Covered	T29,T30,T9
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T29
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	3004	0	0
CntIncr_A	6005714	115432	0	0
CntNoWrap_A	6005714	5356819	0	0
DetectStDropOut_A	6005714	462	0	0
DetectedOut_A	6005714	81931	0	0
DetectedPulseOut_A	6005714	801	0	0
DisabledIdleSt_A	6005714	4898099	0	0
DisabledNoDetection_A	6005714	4900172	0	0
EnterDebounceSt_A	6005714	1520	0	0
EnterDetectSt_A	6005714	1485	0	0
EnterStableSt_A	6005714	801	0	0
PulseIsPulse_A	6005714	801	0	0
StayInStableSt	6005714	81020	0	0
gen_high_event_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	678	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3004	0	0
T1	13850	4	0	0
T2	722	0	0	0
T3	27219	6	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	64	0	0
T10	0	34	0	0
T12	0	8	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	44	0	0
T30	0	20	0	0
T46	0	42	0	0
T56	0	54	0	0
T75	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	115432	0	0
T1	13850	88	0	0
T2	722	0	0	0
T3	27219	168	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2766	0	0
T10	0	1030	0	0
T12	0	120	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	1146	0	0
T30	0	680	0	0
T46	0	1024	0	0
T56	0	1539	0	0
T75	0	1265	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5356819	0	0
T1	13850	13421	0	0
T2	722	321	0	0
T3	27219	26763	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	462	0	0
T8	4858	0	0	0
T9	21785	16	0	0
T10	0	9	0	0
T23	497	0	0	0
T29	5216	22	0	0
T30	6066	10	0	0
T46	0	21	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T67	425	0	0	0
T68	421	0	0	0
T119	0	5	0	0
T120	0	26	0	0
T121	0	12	0	0
T159	0	23	0	0
T266	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	81931	0	0
T1	13850	56	0	0
T2	722	0	0	0
T3	27219	341	0	0
T4	431	0	0	0
T5	502	0	0	0
T12	0	843	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	1895	0	0
T75	0	2511	0	0
T107	0	6	0	0
T117	0	61	0	0
T137	0	5846	0	0
T143	0	178	0	0
T288	0	69	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	801	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	3	0	0
T4	431	0	0	0
T5	502	0	0	0
T12	0	4	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	27	0	0
T75	0	23	0	0
T107	0	6	0	0
T117	0	2	0	0
T137	0	20	0	0
T143	0	7	0	0
T288	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4898099	0	0
T1	13850	9699	0	0
T2	722	321	0	0
T3	27219	22455	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4900172	0	0
T1	13850	9702	0	0
T2	722	322	0	0
T3	27219	22462	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1520	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	3	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	32	0	0
T10	0	17	0	0
T12	0	4	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	22	0	0
T30	0	10	0	0
T46	0	21	0	0
T56	0	27	0	0
T75	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1485	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	3	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	32	0	0
T10	0	17	0	0
T12	0	4	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	22	0	0
T30	0	10	0	0
T46	0	21	0	0
T56	0	27	0	0
T75	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	801	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	3	0	0
T4	431	0	0	0
T5	502	0	0	0
T12	0	4	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	27	0	0
T75	0	23	0	0
T107	0	6	0	0
T117	0	2	0	0
T137	0	20	0	0
T143	0	7	0	0
T288	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	801	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	3	0	0
T4	431	0	0	0
T5	502	0	0	0
T12	0	4	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	27	0	0
T75	0	23	0	0
T107	0	6	0	0
T117	0	2	0	0
T137	0	20	0	0
T143	0	7	0	0
T288	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	81020	0	0
T1	13850	54	0	0
T2	722	0	0	0
T3	27219	336	0	0
T4	431	0	0	0
T5	502	0	0	0
T12	0	837	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	1863	0	0
T75	0	2482	0	0
T117	0	59	0	0
T137	0	5820	0	0
T143	0	171	0	0
T288	0	64	0	0
T292	0	944	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	678	0	0
T1	13850	2	0	0
T2	722	0	0	0
T3	27219	1	0	0
T4	431	0	0	0
T5	502	0	0	0
T12	0	2	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	22	0	0
T75	0	17	0	0
T117	0	2	0	0
T137	0	14	0	0
T143	0	7	0	0
T288	0	5	0	0
T292	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T29
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T29
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T12,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T12,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T34,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T45
1	0	Covered	T1,T14,T3
1	1	Covered	T3,T12,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T33
0	1	Covered	T33,T40,T301
1	0	Covered	T104,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T56
0	1	Covered	T3,T34,T56
1	0	Covered	T104,T55,T302

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T34,T56
1	-	Covered	T3,T34,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T34
DetectSt	168	Covered	T3,T34,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T34,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T34,T33
DebounceSt->IdleSt	163	Covered	T12,T75,T103
DetectSt->IdleSt	186	Covered	T33,T40,T301
DetectSt->StableSt	191	Covered	T3,T34,T56
IdleSt->DebounceSt	148	Covered	T3,T12,T34
StableSt->IdleSt	206	Covered	T3,T34,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T12,T34
0	1	Covered	T3,T12,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T34,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T34,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T75,T103
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T34
DetectSt	-	-	-	-	1	-	-	Covered	T33,T40,T301
DetectSt	-	-	-	-	0	1	-	Covered	T3,T34,T56
DetectSt	-	-	-	-	0	0	-	Covered	T3,T34,T33
StableSt	-	-	-	-	-	-	1	Covered	T3,T34,T56
StableSt	-	-	-	-	-	-	0	Covered	T3,T34,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	741	0	0
CntIncr_A	6005714	40042	0	0
CntNoWrap_A	6005714	5359082	0	0
DetectStDropOut_A	6005714	49	0	0
DetectedOut_A	6005714	16938	0	0
DetectedPulseOut_A	6005714	298	0	0
DisabledIdleSt_A	6005714	4979697	0	0
DisabledNoDetection_A	6005714	4981277	0	0
EnterDebounceSt_A	6005714	390	0	0
EnterDetectSt_A	6005714	351	0	0
EnterStableSt_A	6005714	298	0	0
PulseIsPulse_A	6005714	298	0	0
StayInStableSt	6005714	16613	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	266	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	741	0	0
T3	27219	4	0	0
T6	1498	0	0	0
T7	670	0	0	0
T12	0	1	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T33	0	2	0	0
T34	0	16	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	8	0	0
T75	0	13	0	0
T103	0	9	0	0
T118	0	6	0	0
T137	0	10	0	0
T144	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	40042	0	0
T3	27219	152	0	0
T6	1498	0	0	0
T7	670	0	0	0
T12	0	13	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T33	0	140	0	0
T34	0	904	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	320	0	0
T75	0	508	0	0
T103	0	542	0	0
T118	0	345	0	0
T137	0	305	0	0
T144	0	387	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5359082	0	0
T1	13850	13425	0	0
T2	722	321	0	0
T3	27219	26765	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	49	0	0
T33	16985	1	0	0
T36	9846	0	0	0
T37	936	0	0	0
T40	0	2	0	0
T56	23423	0	0	0
T75	22439	0	0	0
T118	19861	0	0	0
T127	0	2	0	0
T178	504	0	0	0
T179	422	0	0	0
T180	1162	0	0	0
T181	522	0	0	0
T298	0	4	0	0
T301	0	11	0	0
T303	0	1	0	0
T304	0	2	0	0
T305	0	2	0	0
T306	0	2	0	0
T307	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	16938	0	0
T3	27219	103	0	0
T6	1498	0	0	0
T7	670	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T34	0	152	0	0
T35	0	44	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	231	0	0
T75	0	309	0	0
T103	0	54	0	0
T118	0	215	0	0
T137	0	1754	0	0
T141	0	10	0	0
T144	0	222	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	298	0	0
T3	27219	2	0	0
T6	1498	0	0	0
T7	670	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T34	0	8	0	0
T35	0	2	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	4	0	0
T75	0	5	0	0
T103	0	4	0	0
T118	0	3	0	0
T137	0	5	0	0
T141	0	2	0	0
T144	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4979697	0	0
T1	13850	13369	0	0
T2	722	321	0	0
T3	27219	26430	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4981277	0	0
T1	13850	13373	0	0
T2	722	322	0	0
T3	27219	26438	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	390	0	0
T3	27219	2	0	0
T6	1498	0	0	0
T7	670	0	0	0
T12	0	1	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T33	0	1	0	0
T34	0	8	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	4	0	0
T75	0	8	0	0
T103	0	5	0	0
T118	0	3	0	0
T137	0	5	0	0
T144	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	351	0	0
T3	27219	2	0	0
T6	1498	0	0	0
T7	670	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T33	0	1	0	0
T34	0	8	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	4	0	0
T75	0	5	0	0
T103	0	4	0	0
T118	0	3	0	0
T137	0	5	0	0
T141	0	2	0	0
T144	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	298	0	0
T3	27219	2	0	0
T6	1498	0	0	0
T7	670	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T34	0	8	0	0
T35	0	2	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	4	0	0
T75	0	5	0	0
T103	0	4	0	0
T118	0	3	0	0
T137	0	5	0	0
T141	0	2	0	0
T144	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	298	0	0
T3	27219	2	0	0
T6	1498	0	0	0
T7	670	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T34	0	8	0	0
T35	0	2	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	4	0	0
T75	0	5	0	0
T103	0	4	0	0
T118	0	3	0	0
T137	0	5	0	0
T141	0	2	0	0
T144	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	16613	0	0
T3	27219	101	0	0
T6	1498	0	0	0
T7	670	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T34	0	144	0	0
T35	0	42	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	225	0	0
T75	0	300	0	0
T103	0	50	0	0
T118	0	212	0	0
T137	0	1744	0	0
T141	0	8	0	0
T144	0	219	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	266	0	0
T3	27219	2	0	0
T6	1498	0	0	0
T7	670	0	0	0
T17	432	0	0	0
T25	777	0	0	0
T26	667	0	0	0
T28	453	0	0	0
T29	5216	0	0	0
T34	0	8	0	0
T35	0	2	0	0
T52	404	0	0	0
T53	964	0	0	0
T56	0	2	0	0
T75	0	1	0	0
T103	0	4	0	0
T118	0	3	0	0
T141	0	2	0	0
T144	0	3	0	0
T158	0	1	0	0