Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T29
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T29
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T29
0	1	Covered	T29,T30,T46
1	0	Covered	T10,T75,T266

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Covered	T55,T308

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T29
DetectSt	168	Covered	T1,T3,T29
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T29
DebounceSt->IdleSt	163	Covered	T117,T288,T289
DetectSt->IdleSt	186	Covered	T29,T30,T10
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T29
StableSt->IdleSt	206	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T29
0	1	Covered	T1,T3,T29
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T29
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T117,T288,T289
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T29
DetectSt	-	-	-	-	1	-	-	Covered	T29,T30,T10
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T29
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	3017	0	0
CntIncr_A	6005714	104443	0	0
CntNoWrap_A	6005714	5356806	0	0
DetectStDropOut_A	6005714	497	0	0
DetectedOut_A	6005714	82185	0	0
DetectedPulseOut_A	6005714	848	0	0
DisabledIdleSt_A	6005714	4898136	0	0
DisabledNoDetection_A	6005714	4900208	0	0
EnterDebounceSt_A	6005714	1525	0	0
EnterDetectSt_A	6005714	1492	0	0
EnterStableSt_A	6005714	848	0	0
PulseIsPulse_A	6005714	848	0	0
StayInStableSt	6005714	81227	0	0
gen_high_event_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	731	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	3017	0	0
T1	13850	46	0	0
T2	722	0	0	0
T3	27219	30	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	32	0	0
T10	0	16	0	0
T12	0	22	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	26	0	0
T30	0	56	0	0
T46	0	24	0	0
T56	0	54	0	0
T75	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	104443	0	0
T1	13850	1334	0	0
T2	722	0	0	0
T3	27219	1050	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	1312	0	0
T10	0	484	0	0
T12	0	473	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	671	0	0
T30	0	1933	0	0
T46	0	585	0	0
T56	0	1485	0	0
T75	0	627	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5356806	0	0
T1	13850	13379	0	0
T2	722	321	0	0
T3	27219	26739	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	497	0	0
T8	4858	0	0	0
T9	21785	0	0	0
T23	497	0	0	0
T29	5216	13	0	0
T30	6066	28	0	0
T46	0	12	0	0
T54	623	0	0	0
T65	1326	0	0	0
T66	507	0	0	0
T67	425	0	0	0
T68	421	0	0	0
T120	0	3	0	0
T121	0	4	0	0
T159	0	12	0	0
T266	0	24	0	0
T309	0	8	0	0
T310	0	6	0	0
T311	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	82185	0	0
T1	13850	1492	0	0
T2	722	0	0	0
T3	27219	1595	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2442	0	0
T12	0	625	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	1949	0	0
T107	0	1839	0	0
T119	0	1047	0	0
T137	0	3077	0	0
T143	0	653	0	0
T194	0	2025	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	848	0	0
T1	13850	23	0	0
T2	722	0	0	0
T3	27219	15	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	16	0	0
T12	0	11	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	27	0	0
T107	0	17	0	0
T119	0	16	0	0
T137	0	14	0	0
T143	0	25	0	0
T194	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4898136	0	0
T1	13850	8478	0	0
T2	722	321	0	0
T3	27219	21234	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4900208	0	0
T1	13850	8480	0	0
T2	722	322	0	0
T3	27219	21238	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1525	0	0
T1	13850	23	0	0
T2	722	0	0	0
T3	27219	15	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	16	0	0
T10	0	8	0	0
T12	0	11	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	13	0	0
T30	0	28	0	0
T46	0	12	0	0
T56	0	27	0	0
T75	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1492	0	0
T1	13850	23	0	0
T2	722	0	0	0
T3	27219	15	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	16	0	0
T10	0	8	0	0
T12	0	11	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T29	0	13	0	0
T30	0	28	0	0
T46	0	12	0	0
T56	0	27	0	0
T75	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	848	0	0
T1	13850	23	0	0
T2	722	0	0	0
T3	27219	15	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	16	0	0
T12	0	11	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	27	0	0
T107	0	17	0	0
T119	0	16	0	0
T137	0	14	0	0
T143	0	25	0	0
T194	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	848	0	0
T1	13850	23	0	0
T2	722	0	0	0
T3	27219	15	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	16	0	0
T12	0	11	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	27	0	0
T107	0	17	0	0
T119	0	16	0	0
T137	0	14	0	0
T143	0	25	0	0
T194	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	81227	0	0
T1	13850	1468	0	0
T2	722	0	0	0
T3	27219	1575	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	2420	0	0
T12	0	613	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	1917	0	0
T107	0	1822	0	0
T119	0	1030	0	0
T137	0	3062	0	0
T143	0	627	0	0
T194	0	2000	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	731	0	0
T1	13850	22	0	0
T2	722	0	0	0
T3	27219	10	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	10	0	0
T12	0	10	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T56	0	22	0	0
T107	0	17	0	0
T119	0	15	0	0
T137	0	13	0	0
T143	0	24	0	0
T194	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T29
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T29
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T122,T167,T123
1	0	Covered	T104,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T9
DetectSt	168	Covered	T1,T3,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T9
DebounceSt->IdleSt	163	Covered	T45,T144,T103
DetectSt->IdleSt	186	Covered	T122,T167,T123
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T9
StableSt->IdleSt	206	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T104,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T144,T103
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T122,T167,T123
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6005714	1002	0	0
CntIncr_A	6005714	54843	0	0
CntNoWrap_A	6005714	5358821	0	0
DetectStDropOut_A	6005714	59	0	0
DetectedOut_A	6005714	18758	0	0
DetectedPulseOut_A	6005714	406	0	0
DisabledIdleSt_A	6005714	4976560	0	0
DisabledNoDetection_A	6005714	4978139	0	0
EnterDebounceSt_A	6005714	534	0	0
EnterDetectSt_A	6005714	468	0	0
EnterStableSt_A	6005714	406	0	0
PulseIsPulse_A	6005714	406	0	0
StayInStableSt	6005714	18328	0	0
gen_high_level_sva.HighLevelEvent_A	6005714	5362094	0	0
gen_not_sticky_sva.StableStDropOut_A	6005714	380	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	1002	0	0
T1	13850	6	0	0
T2	722	0	0	0
T3	27219	4	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	10	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	2	0	0
T34	0	14	0	0
T45	0	7	0	0
T56	0	4	0	0
T118	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	54843	0	0
T1	13850	189	0	0
T2	722	0	0	0
T3	27219	138	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	450	0	0
T11	0	178	0	0
T12	0	59	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	136	0	0
T34	0	553	0	0
T45	0	478	0	0
T56	0	144	0	0
T118	0	828	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5358821	0	0
T1	13850	13419	0	0
T2	722	321	0	0
T3	27219	26765	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	59	0	0
T78	1212	0	0	0
T104	0	1	0	0
T122	19542	9	0	0
T123	0	9	0	0
T125	0	1	0	0
T131	0	8	0	0
T166	402	0	0	0
T167	9939	1	0	0
T168	507	0	0	0
T169	13857	0	0	0
T170	497	0	0	0
T171	852	0	0	0
T259	639	0	0	0
T300	0	10	0	0
T312	0	6	0	0
T313	0	7	0	0
T314	0	5	0	0
T315	49969	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	18758	0	0
T1	13850	374	0	0
T2	722	0	0	0
T3	27219	114	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	358	0	0
T11	0	44	0	0
T12	0	47	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	4	0	0
T34	0	368	0	0
T45	0	33	0	0
T56	0	132	0	0
T118	0	291	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	406	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	2	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	7	0	0
T45	0	3	0	0
T56	0	2	0	0
T118	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4976560	0	0
T1	13850	11934	0	0
T2	722	321	0	0
T3	27219	25179	0	0
T4	431	30	0	0
T5	502	101	0	0
T13	8402	1	0	0
T14	4021	739	0	0
T15	403	2	0	0
T16	502	101	0	0
T17	432	31	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	4978139	0	0
T1	13850	11937	0	0
T2	722	322	0	0
T3	27219	25184	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	534	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	2	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	7	0	0
T45	0	4	0	0
T56	0	2	0	0
T118	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	468	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	2	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	7	0	0
T45	0	3	0	0
T56	0	2	0	0
T118	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	406	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	2	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	7	0	0
T45	0	3	0	0
T56	0	2	0	0
T118	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	406	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	2	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	7	0	0
T45	0	3	0	0
T56	0	2	0	0
T118	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	18328	0	0
T1	13850	371	0	0
T2	722	0	0	0
T3	27219	112	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	353	0	0
T11	0	42	0	0
T12	0	46	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	3	0	0
T34	0	361	0	0
T45	0	30	0	0
T56	0	129	0	0
T118	0	285	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	5362094	0	0
T1	13850	13429	0	0
T2	722	322	0	0
T3	27219	26779	0	0
T4	431	31	0	0
T5	502	102	0	0
T13	8402	2	0	0
T14	4021	748	0	0
T15	403	3	0	0
T16	502	102	0	0
T17	432	32	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6005714	380	0	0
T1	13850	3	0	0
T2	722	0	0	0
T3	27219	2	0	0
T4	431	0	0	0
T5	502	0	0	0
T9	0	5	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	8402	0	0	0
T14	4021	0	0	0
T15	403	0	0	0
T16	502	0	0	0
T17	432	0	0	0
T33	0	1	0	0
T34	0	7	0	0
T45	0	3	0	0
T56	0	1	0	0
T118	0	6	0	0