Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1124636188 10451 0 0
auto_block_debounce_ctl_rd_A 1124636188 1796 0 0
auto_block_out_ctl_rd_A 1124636188 2846 0 0
com_det_ctl_0_rd_A 1124636188 3558 0 0
com_det_ctl_1_rd_A 1124636188 3560 0 0
com_det_ctl_2_rd_A 1124636188 3517 0 0
com_det_ctl_3_rd_A 1124636188 3628 0 0
com_out_ctl_0_rd_A 1124636188 4337 0 0
com_out_ctl_1_rd_A 1124636188 4231 0 0
com_out_ctl_2_rd_A 1124636188 4171 0 0
com_out_ctl_3_rd_A 1124636188 4196 0 0
com_pre_det_ctl_0_rd_A 1124636188 1500 0 0
com_pre_det_ctl_1_rd_A 1124636188 1319 0 0
com_pre_det_ctl_2_rd_A 1124636188 1454 0 0
com_pre_det_ctl_3_rd_A 1124636188 1445 0 0
com_pre_sel_ctl_0_rd_A 1124636188 4379 0 0
com_pre_sel_ctl_1_rd_A 1124636188 4629 0 0
com_pre_sel_ctl_2_rd_A 1124636188 4498 0 0
com_pre_sel_ctl_3_rd_A 1124636188 4239 0 0
com_sel_ctl_0_rd_A 1124636188 4111 0 0
com_sel_ctl_1_rd_A 1124636188 4475 0 0
com_sel_ctl_2_rd_A 1124636188 4353 0 0
com_sel_ctl_3_rd_A 1124636188 4504 0 0
ec_rst_ctl_rd_A 1124636188 2295 0 0
intr_enable_rd_A 1124636188 1945 0 0
key_intr_ctl_rd_A 1124636188 4151 0 0
key_intr_debounce_ctl_rd_A 1124636188 1568 0 0
key_invert_ctl_rd_A 1124636188 4744 0 0
pin_allowed_ctl_rd_A 1124636188 5934 0 0
pin_out_ctl_rd_A 1124636188 4094 0 0
pin_out_value_rd_A 1124636188 4575 0 0
regwen_rd_A 1124636188 1511 0 0
ulp_ac_debounce_ctl_rd_A 1124636188 1616 0 0
ulp_ctl_rd_A 1124636188 1690 0 0
ulp_lid_debounce_ctl_rd_A 1124636188 1782 0 0
ulp_pwrb_debounce_ctl_rd_A 1124636188 1555 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 10451 0 0
T3 132022 0 0 0
T6 58408 0 0 0
T7 50261 0 0 0
T8 0 7 0 0
T14 100533 17 0 0
T15 173324 0 0 0
T16 250899 0 0 0
T17 209578 0 0 0
T21 0 6 0 0
T25 388528 0 0 0
T27 0 19 0 0
T28 226666 0 0 0
T33 0 12 0 0
T36 0 19 0 0
T40 0 17 0 0
T52 99095 0 0 0
T177 0 12 0 0
T233 0 20 0 0
T262 0 9 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1796 0 0
T47 84521 5 0 0
T48 302559 19 0 0
T49 257000 0 0 0
T50 91279 0 0 0
T51 43361 0 0 0
T119 905796 0 0 0
T120 245580 0 0 0
T133 218460 0 0 0
T143 269778 0 0 0
T200 0 5 0 0
T248 105891 0 0 0
T263 0 20 0 0
T315 0 21 0 0
T318 0 15 0 0
T319 0 3 0 0
T320 0 9 0 0
T321 0 15 0 0
T322 0 39 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 2846 0 0
T6 58408 0 0 0
T7 50261 0 0 0
T25 388528 5 0 0
T26 76777 0 0 0
T28 226666 0 0 0
T29 130411 0 0 0
T30 251766 0 0 0
T47 0 9 0 0
T48 0 19 0 0
T52 99095 0 0 0
T53 240989 0 0 0
T54 308485 0 0 0
T200 0 1 0 0
T263 0 9 0 0
T315 0 12 0 0
T318 0 21 0 0
T319 0 5 0 0
T320 0 5 0 0
T321 0 13 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 3558 0 0
T11 396036 73 0 0
T12 516322 77 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 72 0 0
T73 258793 0 0 0
T103 0 66 0 0
T118 0 69 0 0
T144 0 76 0 0
T167 0 77 0 0
T266 0 49 0 0
T292 0 41 0 0
T318 0 46 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 3560 0 0
T11 396036 64 0 0
T12 516322 76 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 65 0 0
T73 258793 0 0 0
T103 0 76 0 0
T118 0 62 0 0
T144 0 92 0 0
T167 0 75 0 0
T266 0 28 0 0
T292 0 56 0 0
T318 0 54 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 3517 0 0
T11 396036 80 0 0
T12 516322 74 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 88 0 0
T73 258793 0 0 0
T103 0 64 0 0
T118 0 71 0 0
T144 0 61 0 0
T167 0 54 0 0
T266 0 26 0 0
T292 0 48 0 0
T318 0 49 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 3628 0 0
T11 396036 58 0 0
T12 516322 59 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 95 0 0
T73 258793 0 0 0
T103 0 81 0 0
T118 0 69 0 0
T144 0 56 0 0
T167 0 62 0 0
T266 0 51 0 0
T292 0 58 0 0
T318 0 52 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4337 0 0
T11 396036 56 0 0
T12 516322 75 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 78 0 0
T73 258793 0 0 0
T103 0 92 0 0
T118 0 62 0 0
T144 0 51 0 0
T167 0 88 0 0
T266 0 49 0 0
T292 0 49 0 0
T318 0 79 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4231 0 0
T11 396036 68 0 0
T12 516322 75 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 65 0 0
T73 258793 0 0 0
T103 0 74 0 0
T118 0 93 0 0
T144 0 68 0 0
T167 0 63 0 0
T266 0 44 0 0
T292 0 37 0 0
T318 0 49 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4171 0 0
T11 396036 75 0 0
T12 516322 77 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 66 0 0
T73 258793 0 0 0
T103 0 66 0 0
T118 0 96 0 0
T144 0 66 0 0
T167 0 71 0 0
T266 0 26 0 0
T292 0 63 0 0
T318 0 41 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4196 0 0
T11 396036 85 0 0
T12 516322 57 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 35 0 0
T73 258793 0 0 0
T103 0 70 0 0
T118 0 58 0 0
T144 0 77 0 0
T167 0 71 0 0
T266 0 40 0 0
T292 0 59 0 0
T318 0 44 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1500 0 0
T123 216233 0 0 0
T125 0 24 0 0
T150 0 15 0 0
T161 0 2 0 0
T263 0 13 0 0
T307 0 5 0 0
T312 450952 0 0 0
T318 880619 10 0 0
T319 0 9 0 0
T322 0 11 0 0
T325 0 4 0 0
T326 0 9 0 0
T327 333503 0 0 0
T328 55211 0 0 0
T329 193234 0 0 0
T330 991844 0 0 0
T331 100965 0 0 0
T332 59798 0 0 0
T333 253151 0 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1319 0 0
T123 216233 0 0 0
T125 0 18 0 0
T150 0 28 0 0
T161 0 5 0 0
T263 0 12 0 0
T307 0 8 0 0
T312 450952 0 0 0
T318 880619 12 0 0
T319 0 2 0 0
T322 0 9 0 0
T325 0 10 0 0
T326 0 5 0 0
T327 333503 0 0 0
T328 55211 0 0 0
T329 193234 0 0 0
T330 991844 0 0 0
T331 100965 0 0 0
T332 59798 0 0 0
T333 253151 0 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1454 0 0
T123 216233 0 0 0
T125 0 31 0 0
T150 0 15 0 0
T161 0 4 0 0
T263 0 8 0 0
T307 0 7 0 0
T312 450952 0 0 0
T318 880619 16 0 0
T319 0 14 0 0
T322 0 14 0 0
T325 0 10 0 0
T326 0 16 0 0
T327 333503 0 0 0
T328 55211 0 0 0
T329 193234 0 0 0
T330 991844 0 0 0
T331 100965 0 0 0
T332 59798 0 0 0
T333 253151 0 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1445 0 0
T123 216233 0 0 0
T125 0 8 0 0
T150 0 23 0 0
T161 0 12 0 0
T263 0 6 0 0
T307 0 18 0 0
T312 450952 0 0 0
T318 880619 16 0 0
T319 0 2 0 0
T322 0 7 0 0
T325 0 6 0 0
T326 0 18 0 0
T327 333503 0 0 0
T328 55211 0 0 0
T329 193234 0 0 0
T330 991844 0 0 0
T331 100965 0 0 0
T332 59798 0 0 0
T333 253151 0 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4379 0 0
T11 396036 87 0 0
T12 516322 71 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 63 0 0
T73 258793 0 0 0
T103 0 70 0 0
T118 0 64 0 0
T144 0 48 0 0
T167 0 68 0 0
T266 0 50 0 0
T292 0 51 0 0
T318 0 49 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4629 0 0
T11 396036 58 0 0
T12 516322 87 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 74 0 0
T73 258793 0 0 0
T103 0 84 0 0
T118 0 69 0 0
T144 0 71 0 0
T167 0 75 0 0
T266 0 24 0 0
T292 0 41 0 0
T318 0 54 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4498 0 0
T11 396036 69 0 0
T12 516322 58 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 69 0 0
T73 258793 0 0 0
T103 0 53 0 0
T118 0 91 0 0
T144 0 68 0 0
T167 0 77 0 0
T266 0 48 0 0
T292 0 65 0 0
T318 0 42 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4239 0 0
T11 396036 66 0 0
T12 516322 70 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 48 0 0
T73 258793 0 0 0
T103 0 59 0 0
T118 0 82 0 0
T144 0 72 0 0
T167 0 58 0 0
T266 0 39 0 0
T292 0 75 0 0
T318 0 33 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4111 0 0
T11 396036 69 0 0
T12 516322 74 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 62 0 0
T73 258793 0 0 0
T103 0 53 0 0
T118 0 48 0 0
T144 0 71 0 0
T167 0 67 0 0
T266 0 28 0 0
T292 0 65 0 0
T318 0 30 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4475 0 0
T11 396036 59 0 0
T12 516322 70 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 47 0 0
T73 258793 0 0 0
T103 0 61 0 0
T118 0 61 0 0
T144 0 80 0 0
T167 0 67 0 0
T266 0 30 0 0
T292 0 53 0 0
T318 0 33 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4353 0 0
T11 396036 64 0 0
T12 516322 66 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 70 0 0
T73 258793 0 0 0
T103 0 74 0 0
T118 0 61 0 0
T144 0 75 0 0
T167 0 96 0 0
T266 0 35 0 0
T292 0 64 0 0
T318 0 19 0 0
T323 53356 0 0 0
T324 327253 0 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4504 0 0
T11 396036 78 0 0
T12 516322 72 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 69 0 0
T73 258793 0 0 0
T103 0 58 0 0
T118 0 70 0 0
T144 0 70 0 0
T167 0 66 0 0
T266 0 45 0 0
T292 0 81 0 0
T318 0 55 0 0
T323 53356 0 0 0
T324 327253 0 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 2295 0 0
T11 396036 8 0 0
T12 516322 31 0 0
T27 145818 0 0 0
T33 708135 0 0 0
T34 944511 0 0 0
T36 474089 0 0 0
T46 507155 0 0 0
T59 0 34 0 0
T73 258793 0 0 0
T103 0 20 0 0
T118 0 12 0 0
T121 0 4 0 0
T144 0 32 0 0
T167 0 2 0 0
T266 0 5 0 0
T292 0 14 0 0
T323 53356 0 0 0
T324 327253 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1945 0 0
T10 248921 0 0 0
T23 59611 0 0 0
T45 278613 0 0 0
T65 523805 8 0 0
T66 55879 0 0 0
T67 212798 0 0 0
T68 210373 0 0 0
T69 106964 0 0 0
T70 96844 0 0 0
T71 125850 0 0 0
T125 0 77 0 0
T150 0 47 0 0
T161 0 35 0 0
T263 0 36 0 0
T271 0 11 0 0
T318 0 29 0 0
T319 0 12 0 0
T322 0 33 0 0
T325 0 9 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4151 0 0
T2 90351 2 0 0
T3 132022 0 0 0
T6 58408 0 0 0
T7 0 4 0 0
T14 100533 0 0 0
T15 173324 0 0 0
T16 250899 0 0 0
T17 209578 0 0 0
T25 388528 0 0 0
T28 226666 0 0 0
T43 0 3 0 0
T44 0 2 0 0
T52 99095 0 0 0
T259 0 5 0 0
T263 0 16 0 0
T318 0 9 0 0
T319 0 8 0 0
T322 0 15 0 0
T334 0 7 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1568 0 0
T18 0 60 0 0
T123 216233 0 0 0
T125 0 26 0 0
T150 0 15 0 0
T161 0 6 0 0
T263 0 6 0 0
T312 450952 0 0 0
T318 880619 2 0 0
T322 0 12 0 0
T325 0 2 0 0
T326 0 15 0 0
T327 333503 0 0 0
T328 55211 0 0 0
T329 193234 0 0 0
T330 991844 0 0 0
T331 100965 0 0 0
T332 59798 0 0 0
T333 253151 0 0 0
T335 0 12 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4744 0 0
T11 396036 0 0 0
T12 516322 0 0 0
T24 128693 64 0 0
T34 944511 0 0 0
T46 507155 0 0 0
T72 68387 0 0 0
T73 258793 0 0 0
T263 0 92 0 0
T318 0 13 0 0
T319 0 44 0 0
T322 0 79 0 0
T323 53356 0 0 0
T332 0 77 0 0
T336 0 44 0 0
T337 0 53 0 0
T338 0 70 0 0
T339 0 71 0 0
T340 86714 0 0 0
T341 152213 0 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 5934 0 0
T11 396036 0 0 0
T12 516322 0 0 0
T34 944511 0 0 0
T46 507155 0 0 0
T72 68387 51 0 0
T73 258793 0 0 0
T125 0 163 0 0
T198 0 57 0 0
T263 0 9 0 0
T318 0 14 0 0
T322 0 88 0 0
T323 53356 0 0 0
T324 327253 0 0 0
T340 86714 0 0 0
T341 152213 0 0 0
T342 0 50 0 0
T343 0 57 0 0
T344 0 69 0 0
T345 0 84 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4094 0 0
T11 396036 0 0 0
T12 516322 0 0 0
T34 944511 0 0 0
T46 507155 0 0 0
T72 68387 65 0 0
T73 258793 0 0 0
T125 0 221 0 0
T198 0 65 0 0
T263 0 16 0 0
T318 0 6 0 0
T319 0 10 0 0
T322 0 93 0 0
T323 53356 0 0 0
T324 327253 0 0 0
T340 86714 0 0 0
T341 152213 0 0 0
T342 0 40 0 0
T343 0 36 0 0
T344 0 42 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 4575 0 0
T11 396036 0 0 0
T12 516322 0 0 0
T34 944511 0 0 0
T46 507155 0 0 0
T72 68387 84 0 0
T73 258793 0 0 0
T125 0 222 0 0
T198 0 60 0 0
T263 0 4 0 0
T318 0 16 0 0
T319 0 15 0 0
T322 0 80 0 0
T323 53356 0 0 0
T324 327253 0 0 0
T340 86714 0 0 0
T341 152213 0 0 0
T342 0 49 0 0
T343 0 29 0 0
T344 0 66 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1511 0 0
T123 216233 0 0 0
T125 0 25 0 0
T150 0 32 0 0
T161 0 2 0 0
T263 0 15 0 0
T307 0 5 0 0
T312 450952 0 0 0
T318 880619 11 0 0
T319 0 14 0 0
T322 0 9 0 0
T325 0 14 0 0
T326 0 28 0 0
T327 333503 0 0 0
T328 55211 0 0 0
T329 193234 0 0 0
T330 991844 0 0 0
T331 100965 0 0 0
T332 59798 0 0 0
T333 253151 0 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1616 0 0
T42 153739 0 0 0
T44 217721 0 0 0
T59 129224 7 0 0
T60 49866 0 0 0
T64 120503 0 0 0
T78 0 17 0 0
T107 104299 0 0 0
T145 0 5 0 0
T146 0 1 0 0
T167 0 4 0 0
T173 154999 0 0 0
T263 0 11 0 0
T284 0 1 0 0
T290 528855 0 0 0
T318 0 21 0 0
T319 0 11 0 0
T328 0 2 0 0
T346 660122 0 0 0
T347 190895 0 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1690 0 0
T42 153739 0 0 0
T44 217721 0 0 0
T59 129224 7 0 0
T60 49866 0 0 0
T64 120503 0 0 0
T78 0 9 0 0
T107 104299 0 0 0
T145 0 8 0 0
T146 0 3 0 0
T147 0 6 0 0
T167 0 6 0 0
T173 154999 0 0 0
T263 0 13 0 0
T290 528855 0 0 0
T318 0 14 0 0
T319 0 22 0 0
T328 0 6 0 0
T346 660122 0 0 0
T347 190895 0 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1782 0 0
T42 153739 0 0 0
T44 217721 0 0 0
T59 129224 8 0 0
T60 49866 0 0 0
T64 120503 0 0 0
T78 0 18 0 0
T107 104299 0 0 0
T145 0 1 0 0
T146 0 8 0 0
T147 0 16 0 0
T167 0 2 0 0
T173 154999 0 0 0
T263 0 24 0 0
T290 528855 0 0 0
T318 0 23 0 0
T319 0 18 0 0
T328 0 18 0 0
T346 660122 0 0 0
T347 190895 0 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1124636188 1555 0 0
T42 153739 0 0 0
T44 217721 0 0 0
T59 129224 8 0 0
T60 49866 0 0 0
T64 120503 0 0 0
T78 0 9 0 0
T107 104299 0 0 0
T145 0 5 0 0
T146 0 3 0 0
T147 0 13 0 0
T173 154999 0 0 0
T263 0 11 0 0
T284 0 5 0 0
T290 528855 0 0 0
T318 0 6 0 0
T319 0 14 0 0
T328 0 11 0 0
T346 660122 0 0 0
T347 190895 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%