Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T4,T5,T6
1	1	Covered	T32,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T33,T34
1	-	Covered	T32,T33,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T34
DetectSt	168	Covered	T32,T33,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T32,T33,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T34
DebounceSt->IdleSt	163	Covered	T34,T59,T61
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T32,T33,T34
IdleSt->DebounceSt	148	Covered	T32,T33,T34
StableSt->IdleSt	206	Covered	T32,T33,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T34
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T59,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T34
StableSt	-	-	-	-	-	-	0	Covered	T32,T33,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	260	0	0
CntIncr_A	6979152	167343	0	0
CntNoWrap_A	6979152	6334939	0	0
DetectStDropOut_A	6979152	0	0	0
DetectedOut_A	6979152	819	0	0
DetectedPulseOut_A	6979152	123	0	0
DisabledIdleSt_A	6979152	6161612	0	0
DisabledNoDetection_A	6979152	6163897	0	0
EnterDebounceSt_A	6979152	141	0	0
EnterDetectSt_A	6979152	123	0	0
EnterStableSt_A	6979152	123	0	0
PulseIsPulse_A	6979152	123	0	0
StayInStableSt	6979152	696	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	6829	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	122	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	260	0	0
T8	1533	0	0	0
T32	664	4	0	0
T33	766	4	0	0
T34	0	5	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T58	0	4	0	0
T59	0	7	0	0
T60	0	4	0	0
T61	0	3	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	167343	0	0
T8	1533	0	0	0
T32	664	99	0	0
T33	766	142	0	0
T34	0	234	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	55695	0	0
T56	0	108	0	0
T58	0	105	0	0
T59	0	7059	0	0
T60	0	114	0	0
T61	0	30	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6334939	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	819	0	0
T8	1533	0	0	0
T32	664	18	0	0
T33	766	8	0	0
T34	0	24	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	10	0	0
T56	0	10	0	0
T58	0	4	0	0
T59	0	20	0	0
T60	0	10	0	0
T61	0	5	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	123	0	0
T8	1533	0	0	0
T32	664	2	0	0
T33	766	2	0	0
T34	0	2	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	1	0	0
T56	0	2	0	0
T58	0	2	0	0
T59	0	3	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6161612	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6163897	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	141	0	0
T8	1533	0	0	0
T32	664	2	0	0
T33	766	2	0	0
T34	0	3	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	1	0	0
T56	0	2	0	0
T58	0	2	0	0
T59	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	123	0	0
T8	1533	0	0	0
T32	664	2	0	0
T33	766	2	0	0
T34	0	2	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	1	0	0
T56	0	2	0	0
T58	0	2	0	0
T59	0	3	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	123	0	0
T8	1533	0	0	0
T32	664	2	0	0
T33	766	2	0	0
T34	0	2	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	1	0	0
T56	0	2	0	0
T58	0	2	0	0
T59	0	3	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	123	0	0
T8	1533	0	0	0
T32	664	2	0	0
T33	766	2	0	0
T34	0	2	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	1	0	0
T56	0	2	0	0
T58	0	2	0	0
T59	0	3	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	696	0	0
T8	1533	0	0	0
T32	664	16	0	0
T33	766	6	0	0
T34	0	22	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	9	0	0
T56	0	8	0	0
T58	0	2	0	0
T59	0	17	0	0
T60	0	8	0	0
T61	0	4	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6829	0	0
T1	35031	16	0	0
T4	494	12	0	0
T5	435	4	0	0
T6	502	4	0	0
T14	423	3	0	0
T15	32180	26	0	0
T16	736	0	0	0
T19	0	5	0	0
T20	0	5	0	0
T22	0	8	0	0
T23	422	3	0	0
T24	650	0	0	0
T25	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	122	0	0
T8	1533	0	0	0
T32	664	2	0	0
T33	766	2	0	0
T34	0	2	0	0
T41	702	0	0	0
T54	12268	0	0	0
T55	0	1	0	0
T56	0	2	0	0
T58	0	2	0	0
T59	0	3	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T69,T90

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T11,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T69,T90
0	1	Covered	T90,T91,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T69,T90
0	1	Unreachable
1	0	Covered	T8,T69,T90

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T29
DetectSt	168	Covered	T8,T69,T90
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T69,T90

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T69,T90
DebounceSt->IdleSt	163	Covered	T11,T29,T89
DetectSt->IdleSt	186	Covered	T90,T91,T107
DetectSt->StableSt	191	Covered	T8,T69,T90
IdleSt->DebounceSt	148	Covered	T8,T11,T29
StableSt->IdleSt	206	Covered	T8,T69,T90

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T29
0	1	Covered	T8,T11,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T69,T90
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T29
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T69,T90
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T29,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T29
DetectSt	-	-	-	-	1	-	-	Covered	T90,T91,T107
DetectSt	-	-	-	-	0	1	-	Covered	T8,T69,T90
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T69,T90
StableSt	-	-	-	-	-	-	0	Covered	T8,T69,T90
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	158	0	0
CntIncr_A	6979152	177875	0	0
CntNoWrap_A	6979152	6335041	0	0
DetectStDropOut_A	6979152	11	0	0
DetectedOut_A	6979152	644669	0	0
DetectedPulseOut_A	6979152	48	0	0
DisabledIdleSt_A	6979152	4402239	0	0
DisabledNoDetection_A	6979152	4404569	0	0
EnterDebounceSt_A	6979152	100	0	0
EnterDetectSt_A	6979152	59	0	0
EnterStableSt_A	6979152	48	0	0
PulseIsPulse_A	6979152	48	0	0
StayInStableSt	6979152	644621	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	6829	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_sticky_sva.StableStDropOut_A	6979152	1083921	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	158	0	0
T8	1533	4	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T29	0	3	0	0
T68	1991	0	0	0
T69	0	2	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	13	0	0
T91	0	4	0	0
T92	0	5	0	0
T93	0	2	0	0
T94	0	2	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	177875	0	0
T8	1533	160	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	20	0	0
T29	0	48	0	0
T68	1991	0	0	0
T69	0	97	0	0
T81	504	0	0	0
T89	0	86	0	0
T90	0	272	0	0
T91	0	129	0	0
T92	0	270	0	0
T93	0	72	0	0
T94	0	70	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335041	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	11	0	0
T44	29004	0	0	0
T58	18541	0	0	0
T59	46116	0	0	0
T60	684	0	0	0
T80	5141	0	0	0
T90	1631	3	0	0
T91	771	1	0	0
T105	0	3	0	0
T107	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	1814	0	0	0
T139	15295	0	0	0
T140	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	644669	0	0
T8	1533	584	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	86	0	0
T81	504	0	0	0
T90	0	105	0	0
T93	0	435	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T104	0	263	0	0
T107	0	158	0	0
T129	0	3	0	0
T131	0	153591	0	0
T132	0	132	0	0
T134	0	291982	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	48	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T90	0	2	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T104	0	2	0	0
T107	0	2	0	0
T129	0	1	0	0
T131	0	2	0	0
T132	0	3	0	0
T134	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4402239	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4404569	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	100	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T29	0	3	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	8	0	0
T91	0	3	0	0
T92	0	5	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	59	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T90	0	5	0	0
T91	0	1	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T104	0	2	0	0
T129	0	1	0	0
T131	0	2	0	0
T132	0	3	0	0
T134	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	48	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T90	0	2	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T104	0	2	0	0
T107	0	2	0	0
T129	0	1	0	0
T131	0	2	0	0
T132	0	3	0	0
T134	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	48	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T90	0	2	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T104	0	2	0	0
T107	0	2	0	0
T129	0	1	0	0
T131	0	2	0	0
T132	0	3	0	0
T134	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	644621	0	0
T8	1533	582	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	85	0	0
T81	504	0	0	0
T90	0	103	0	0
T93	0	434	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T104	0	261	0	0
T107	0	156	0	0
T129	0	2	0	0
T131	0	153589	0	0
T132	0	129	0	0
T134	0	291981	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6829	0	0
T1	35031	16	0	0
T4	494	12	0	0
T5	435	4	0	0
T6	502	4	0	0
T14	423	3	0	0
T15	32180	26	0	0
T16	736	0	0	0
T19	0	5	0	0
T20	0	5	0	0
T22	0	8	0	0
T23	422	3	0	0
T24	650	0	0	0
T25	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1083921	0	0
T8	1533	143	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	31	0	0
T81	504	0	0	0
T90	0	333	0	0
T93	0	328780	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T104	0	390	0	0
T107	0	483	0	0
T129	0	139	0	0
T131	0	136	0	0
T132	0	704340	0	0
T134	0	108	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T11,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T29
0	1	Covered	T8,T94,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T29
0	1	Unreachable
1	0	Covered	T8,T11,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T29
DetectSt	168	Covered	T8,T11,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T11,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T29
DebounceSt->IdleSt	163	Covered	T8,T94,T131
DetectSt->IdleSt	186	Covered	T8,T94,T104
DetectSt->StableSt	191	Covered	T8,T11,T29
IdleSt->DebounceSt	148	Covered	T8,T11,T29
StableSt->IdleSt	206	Covered	T8,T11,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T29
0	1	Covered	T8,T11,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T29
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T29
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T94,T131
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T29
DetectSt	-	-	-	-	1	-	-	Covered	T8,T94,T104
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T29
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	164	0	0
CntIncr_A	6979152	252499	0	0
CntNoWrap_A	6979152	6335035	0	0
DetectStDropOut_A	6979152	11	0	0
DetectedOut_A	6979152	859427	0	0
DetectedPulseOut_A	6979152	49	0	0
DisabledIdleSt_A	6979152	4402239	0	0
DisabledNoDetection_A	6979152	4404569	0	0
EnterDebounceSt_A	6979152	105	0	0
EnterDetectSt_A	6979152	60	0	0
EnterStableSt_A	6979152	49	0	0
PulseIsPulse_A	6979152	49	0	0
StayInStableSt	6979152	859378	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_sticky_sva.StableStDropOut_A	6979152	350206	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	164	0	0
T8	1533	10	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	2	0	0
T29	0	2	0	0
T68	1991	0	0	0
T69	0	2	0	0
T81	504	0	0	0
T89	0	2	0	0
T90	0	6	0	0
T91	0	2	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	3	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	252499	0	0
T8	1533	264	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	54	0	0
T29	0	27	0	0
T68	1991	0	0	0
T69	0	95	0	0
T81	504	0	0	0
T89	0	44	0	0
T90	0	162	0	0
T91	0	54	0	0
T92	0	95	0	0
T93	0	44027	0	0
T94	0	200	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335035	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	11	0	0
T8	1533	3	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T81	504	0	0	0
T94	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T104	0	1	0	0
T135	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	859427	0	0
T8	1533	1	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	45	0	0
T29	0	111	0	0
T68	1991	0	0	0
T69	0	64	0	0
T81	504	0	0	0
T89	0	29	0	0
T90	0	726	0	0
T91	0	200	0	0
T92	0	693	0	0
T93	0	285157	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	49	0	0
T8	1533	1	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T29	0	1	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4402239	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4404569	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	105	0	0
T8	1533	6	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T29	0	1	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	60	0	0
T8	1533	4	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T29	0	1	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	49	0	0
T8	1533	1	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T29	0	1	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	49	0	0
T8	1533	1	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T29	0	1	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	859378	0	0
T11	565	44	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T29	0	110	0	0
T31	19449	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T42	31493	0	0	0
T69	0	63	0	0
T89	0	28	0	0
T90	0	723	0	0
T91	0	199	0	0
T92	0	692	0	0
T93	0	285156	0	0
T121	510	0	0	0
T122	403	0	0	0
T129	0	17	0	0
T130	0	386	0	0
T144	407	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	350206	0	0
T8	1533	100	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	27	0	0
T29	0	92	0	0
T68	1991	0	0	0
T69	0	36	0	0
T81	504	0	0	0
T89	0	95	0	0
T90	0	219	0	0
T91	0	66	0	0
T92	0	284	0	0
T93	0	106	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	117	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T69

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T11,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T69,T90
0	1	Covered	T11,T104,T105
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T69,T90
0	1	Unreachable
1	0	Covered	T8,T69,T90

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T29
DetectSt	168	Covered	T8,T11,T69
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T69,T90

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T69
DebounceSt->IdleSt	163	Covered	T29,T89,T94
DetectSt->IdleSt	186	Covered	T11,T104,T105
DetectSt->StableSt	191	Covered	T8,T69,T90
IdleSt->DebounceSt	148	Covered	T8,T11,T29
StableSt->IdleSt	206	Covered	T8,T69,T90

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T29
0	1	Covered	T8,T11,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T69
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T29
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T69
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T89,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T29
DetectSt	-	-	-	-	1	-	-	Covered	T11,T104,T105
DetectSt	-	-	-	-	0	1	-	Covered	T8,T69,T90
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T69,T90
StableSt	-	-	-	-	-	-	0	Covered	T8,T69,T90
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	163	0	0
CntIncr_A	6979152	5098	0	0
CntNoWrap_A	6979152	6335036	0	0
DetectStDropOut_A	6979152	13	0	0
DetectedOut_A	6979152	9623	0	0
DetectedPulseOut_A	6979152	45	0	0
DisabledIdleSt_A	6979152	4402239	0	0
DisabledNoDetection_A	6979152	4404569	0	0
EnterDebounceSt_A	6979152	106	0	0
EnterDetectSt_A	6979152	58	0	0
EnterStableSt_A	6979152	45	0	0
PulseIsPulse_A	6979152	45	0	0
StayInStableSt	6979152	9578	0	0
gen_high_event_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_sticky_sva.StableStDropOut_A	6979152	963251	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	163	0	0
T8	1533	4	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	2	0	0
T29	0	3	0	0
T68	1991	0	0	0
T69	0	2	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	6	0	0
T91	0	2	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5098	0	0
T8	1533	174	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	84	0	0
T29	0	48	0	0
T68	1991	0	0	0
T69	0	50	0	0
T81	504	0	0	0
T89	0	66	0	0
T90	0	189	0	0
T91	0	44	0	0
T92	0	99	0	0
T93	0	82	0	0
T94	0	98	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335036	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	13	0	0
T11	565	1	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	19449	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T42	31493	0	0	0
T104	0	1	0	0
T105	0	2	0	0
T121	510	0	0	0
T122	403	0	0	0
T144	407	0	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	9623	0	0
T8	1533	524	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	17	0	0
T81	504	0	0	0
T90	0	789	0	0
T91	0	167	0	0
T92	0	821	0	0
T93	0	520	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	43	0	0
T130	0	427	0	0
T131	0	147	0	0
T133	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4402239	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4404569	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	106	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T29	0	3	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	58	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T11	0	1	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T8	1533	2	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	1	0	0
T81	504	0	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	2	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	9578	0	0
T8	1533	522	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	16	0	0
T81	504	0	0	0
T90	0	786	0	0
T91	0	166	0	0
T92	0	820	0	0
T93	0	519	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	42	0	0
T130	0	426	0	0
T131	0	145	0	0
T133	0	84	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	963251	0	0
T8	1533	200	0	0
T9	15906	0	0	0
T10	678	0	0	0
T68	1991	0	0	0
T69	0	148	0	0
T81	504	0	0	0
T90	0	154	0	0
T91	0	122	0	0
T92	0	155	0	0
T93	0	328692	0	0
T95	424	0	0	0
T96	8407	0	0	0
T97	4414	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T129	0	32	0	0
T130	0	287	0	0
T131	0	218196	0	0
T133	0	114	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T48,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T48,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T48,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T48,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T48,T44
0	1	Covered	T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T48,T44
0	1	Covered	T44,T150,T106
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T48,T44
1	-	Covered	T44,T150,T106

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T48,T44
DetectSt	168	Covered	T3,T48,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T48,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T48,T44
DebounceSt->IdleSt	163	Covered	T150,T102,T100
DetectSt->IdleSt	186	Covered	T102
DetectSt->StableSt	191	Covered	T3,T48,T44
IdleSt->DebounceSt	148	Covered	T3,T48,T44
StableSt->IdleSt	206	Covered	T44,T150,T106

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T48,T44
0	1	Covered	T3,T48,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T48,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T48,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T48,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T48,T44
DetectSt	-	-	-	-	1	-	-	Covered	T102
DetectSt	-	-	-	-	0	1	-	Covered	T3,T48,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T150,T106
StableSt	-	-	-	-	-	-	0	Covered	T3,T48,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	83	0	0
CntIncr_A	6979152	2350	0	0
CntNoWrap_A	6979152	6335116	0	0
DetectStDropOut_A	6979152	1	0	0
DetectedOut_A	6979152	2666	0	0
DetectedPulseOut_A	6979152	39	0	0
DisabledIdleSt_A	6979152	6318290	0	0
DisabledNoDetection_A	6979152	6320574	0	0
EnterDebounceSt_A	6979152	44	0	0
EnterDetectSt_A	6979152	40	0	0
EnterStableSt_A	6979152	39	0	0
PulseIsPulse_A	6979152	39	0	0
StayInStableSt	6979152	2610	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	83	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	4	0	0
T48	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	3	0	0
T106	0	2	0	0
T107	0	2	0	0
T150	0	3	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2350	0	0
T3	740	26	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	114	0	0
T48	0	48	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	184	0	0
T106	0	31	0	0
T107	0	83	0	0
T150	0	196	0	0
T151	0	82	0	0
T152	0	17	0	0
T153	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335116	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1	0	0
T102	1095	1	0	0
T131	229079	0	0	0
T154	527	0	0	0
T155	3759	0	0	0
T156	712	0	0	0
T157	503	0	0	0
T158	11486	0	0	0
T159	423	0	0	0
T160	402	0	0	0
T161	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2666	0	0
T3	740	145	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	91	0	0
T48	0	42	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	94	0	0
T150	0	40	0	0
T151	0	99	0	0
T152	0	15	0	0
T153	0	42	0	0
T162	0	194	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	39	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	2	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T162	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6318290	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6320574	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	44	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	2	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	40	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	2	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	39	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	2	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T162	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	39	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	2	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T162	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2610	0	0
T3	740	143	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	88	0	0
T48	0	40	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	93	0	0
T150	0	39	0	0
T151	0	96	0	0
T152	0	14	0	0
T153	0	41	0	0
T162	0	191	0	0
T163	0	34	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	21	0	0
T44	29004	1	0	0
T60	684	0	0	0
T91	771	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T119	0	2	0	0
T138	1814	0	0	0
T139	15295	0	0	0
T140	503	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T165	424	0	0	0
T166	402	0	0	0
T167	8751	0	0	0
T168	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T45,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T45,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T45,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T45,T47
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T45,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T45,T47
0	1	Covered	T43,T48
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T45,T47
0	1	Covered	T3,T106,T169
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T45,T47
1	-	Covered	T3,T106,T169

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T45,T47
DetectSt	168	Covered	T3,T45,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T45,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T45,T47
DebounceSt->IdleSt	163	Covered	T43,T100,T170
DetectSt->IdleSt	186	Covered	T43,T48
DetectSt->StableSt	191	Covered	T3,T45,T47
IdleSt->DebounceSt	148	Covered	T3,T45,T47
StableSt->IdleSt	206	Covered	T3,T47,T106

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T45,T47
0	1	Covered	T3,T45,T47
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T45,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T45,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T45,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T45,T47
DetectSt	-	-	-	-	1	-	-	Covered	T43,T48
DetectSt	-	-	-	-	0	1	-	Covered	T3,T45,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T106,T169
StableSt	-	-	-	-	-	-	0	Covered	T3,T45,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	121	0	0
CntIncr_A	6979152	3525	0	0
CntNoWrap_A	6979152	6335078	0	0
DetectStDropOut_A	6979152	2	0	0
DetectedOut_A	6979152	4639	0	0
DetectedPulseOut_A	6979152	57	0	0
DisabledIdleSt_A	6979152	6318637	0	0
DisabledNoDetection_A	6979152	6320920	0	0
EnterDebounceSt_A	6979152	62	0	0
EnterDetectSt_A	6979152	59	0	0
EnterStableSt_A	6979152	57	0	0
PulseIsPulse_A	6979152	57	0	0
StayInStableSt	6979152	4553	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	2647	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	121	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T43	0	3	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	4	0	0
T152	0	4	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	3525	0	0
T3	740	26	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T43	0	152	0	0
T45	0	42	0	0
T47	0	88	0	0
T48	0	48	0	0
T49	0	36	0	0
T50	0	58	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	62	0	0
T152	0	34	0	0
T169	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335078	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2	0	0
T43	726	1	0	0
T48	548	1	0	0
T53	6663	0	0	0
T69	1656	0	0	0
T70	1230	0	0	0
T82	665	0	0	0
T85	32692	0	0	0
T171	414	0	0	0
T172	221077	0	0	0
T173	521	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4639	0	0
T3	740	23	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	47	0	0
T47	0	37	0	0
T49	0	168	0	0
T50	0	202	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	193	0	0
T107	0	223	0	0
T152	0	88	0	0
T153	0	232	0	0
T169	0	321	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	57	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	2	0	0
T107	0	2	0	0
T152	0	2	0	0
T153	0	2	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6318637	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6320920	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	62	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	2	0	0
T152	0	2	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	59	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	2	0	0
T152	0	2	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	57	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	2	0	0
T107	0	2	0	0
T152	0	2	0	0
T153	0	2	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	57	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	2	0	0
T107	0	2	0	0
T152	0	2	0	0
T153	0	2	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4553	0	0
T3	740	22	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	45	0	0
T47	0	35	0	0
T49	0	166	0	0
T50	0	200	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	190	0	0
T107	0	220	0	0
T152	0	85	0	0
T153	0	229	0	0
T169	0	320	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2647	0	0
T1	35031	0	0	0
T3	0	1	0	0
T4	494	5	0	0
T5	435	4	0	0
T6	502	5	0	0
T14	423	2	0	0
T15	32180	0	0	0
T16	736	0	0	0
T19	0	5	0	0
T20	0	5	0	0
T22	0	5	0	0
T23	422	3	0	0
T24	650	0	0	0
T25	402	0	0	0
T84	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	27	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T119	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T163	0	1	0	0
T169	0	1	0	0
T174	0	2	0	0
T175	0	1	0	0