Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T31,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T44,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T31,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T44,T50
0	1	Covered	T106,T137
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T44,T50
0	1	Covered	T44,T106,T152
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T44,T50
1	-	Covered	T44,T106,T152

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T43,T44
DetectSt	168	Covered	T31,T44,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T31,T44,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T44,T50
DebounceSt->IdleSt	163	Covered	T43,T107,T162
DetectSt->IdleSt	186	Covered	T106,T137
DetectSt->StableSt	191	Covered	T31,T44,T50
IdleSt->DebounceSt	148	Covered	T31,T43,T44
StableSt->IdleSt	206	Covered	T31,T44,T106

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T43,T44
0	1	Covered	T31,T43,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T44,T50
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T44,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T107,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T43,T44
DetectSt	-	-	-	-	1	-	-	Covered	T106,T137
DetectSt	-	-	-	-	0	1	-	Covered	T31,T44,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T106,T152
StableSt	-	-	-	-	-	-	0	Covered	T31,T44,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	94	0	0
CntIncr_A	6979152	66206	0	0
CntNoWrap_A	6979152	6335105	0	0
DetectStDropOut_A	6979152	2	0	0
DetectedOut_A	6979152	59151	0	0
DetectedPulseOut_A	6979152	43	0	0
DisabledIdleSt_A	6979152	6085561	0	0
DisabledNoDetection_A	6979152	6087837	0	0
EnterDebounceSt_A	6979152	50	0	0
EnterDetectSt_A	6979152	45	0	0
EnterStableSt_A	6979152	43	0	0
PulseIsPulse_A	6979152	43	0	0
StayInStableSt	6979152	59081	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	94	0	0
T31	19449	2	0	0
T36	15901	0	0	0
T43	0	1	0	0
T44	0	4	0	0
T45	542	0	0	0
T50	0	2	0	0
T51	22099	0	0	0
T106	0	4	0	0
T107	0	3	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T174	0	4	0	0
T176	0	2	0	0
T177	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	66206	0	0
T31	19449	84	0	0
T36	15901	0	0	0
T43	0	76	0	0
T44	0	114	0	0
T45	542	0	0	0
T50	0	58	0	0
T51	22099	0	0	0
T106	0	62	0	0
T107	0	166	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	41	0	0
T152	0	17	0	0
T174	0	28	0	0
T176	0	61	0	0
T177	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335105	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2	0	0
T102	1095	0	0	0
T106	753	1	0	0
T113	4568	0	0	0
T131	229079	0	0	0
T137	0	1	0	0
T154	527	0	0	0
T155	3759	0	0	0
T156	712	0	0	0
T157	503	0	0	0
T158	11486	0	0	0
T178	750	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	59151	0	0
T31	19449	251	0	0
T36	15901	0	0	0
T44	0	191	0	0
T45	542	0	0	0
T50	0	203	0	0
T51	22099	0	0	0
T106	0	40	0	0
T107	0	41	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	75	0	0
T152	0	67	0	0
T174	0	101	0	0
T176	0	41	0	0
T177	502	0	0	0
T179	0	255	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	43	0	0
T31	19449	1	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	0	0	0
T50	0	1	0	0
T51	22099	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	502	0	0	0
T179	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6085561	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6087837	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	50	0	0
T31	19449	1	0	0
T36	15901	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	542	0	0	0
T50	0	1	0	0
T51	22099	0	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T31	19449	1	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	0	0	0
T50	0	1	0	0
T51	22099	0	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	502	0	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	43	0	0
T31	19449	1	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	0	0	0
T50	0	1	0	0
T51	22099	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	502	0	0	0
T179	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	43	0	0
T31	19449	1	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	0	0	0
T50	0	1	0	0
T51	22099	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	502	0	0	0
T179	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	59081	0	0
T31	19449	249	0	0
T36	15901	0	0	0
T44	0	188	0	0
T45	542	0	0	0
T50	0	201	0	0
T51	22099	0	0	0
T106	0	39	0	0
T107	0	39	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T151	0	73	0	0
T152	0	66	0	0
T174	0	98	0	0
T176	0	39	0	0
T177	502	0	0	0
T179	0	253	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	15	0	0
T44	29004	1	0	0
T60	684	0	0	0
T91	771	0	0	0
T106	0	1	0	0
T119	0	1	0	0
T138	1814	0	0	0
T139	15295	0	0	0
T140	503	0	0	0
T152	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T165	424	0	0	0
T166	402	0	0	0
T167	8751	0	0	0
T168	405	0	0	0
T174	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T48,T49
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T48,T49
0	1	Covered	T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T48,T49
0	1	Covered	T150,T106,T102
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T48,T49
1	-	Covered	T150,T106,T102

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T48,T49
DetectSt	168	Covered	T3,T48,T49
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T48,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T48,T49
DebounceSt->IdleSt	163	Covered	T102,T100,T183
DetectSt->IdleSt	186	Covered	T102
DetectSt->StableSt	191	Covered	T3,T48,T49
IdleSt->DebounceSt	148	Covered	T3,T48,T49
StableSt->IdleSt	206	Covered	T150,T106,T102

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T48,T49
0	1	Covered	T3,T48,T49
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T48,T49
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T183,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T48,T49
DetectSt	-	-	-	-	1	-	-	Covered	T102
DetectSt	-	-	-	-	0	1	-	Covered	T3,T48,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T150,T106,T102
StableSt	-	-	-	-	-	-	0	Covered	T3,T48,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	130	0	0
CntIncr_A	6979152	86274	0	0
CntNoWrap_A	6979152	6335069	0	0
DetectStDropOut_A	6979152	1	0	0
DetectedOut_A	6979152	59246	0	0
DetectedPulseOut_A	6979152	62	0	0
DisabledIdleSt_A	6979152	5992141	0	0
DisabledNoDetection_A	6979152	5994422	0	0
EnterDebounceSt_A	6979152	68	0	0
EnterDetectSt_A	6979152	63	0	0
EnterStableSt_A	6979152	62	0	0
PulseIsPulse_A	6979152	62	0	0
StayInStableSt	6979152	59157	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	3038	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	130	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	5	0	0
T106	0	6	0	0
T107	0	6	0	0
T131	0	2	0	0
T150	0	4	0	0
T151	0	2	0	0
T185	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	86274	0	0
T3	740	26	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	48	0	0
T49	0	36	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	276	0	0
T106	0	93	0	0
T107	0	213	0	0
T131	0	51	0	0
T150	0	196	0	0
T151	0	41	0	0
T185	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335069	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1	0	0
T102	1095	1	0	0
T131	229079	0	0	0
T154	527	0	0	0
T155	3759	0	0	0
T156	712	0	0	0
T157	503	0	0	0
T158	11486	0	0	0
T159	423	0	0	0
T160	402	0	0	0
T161	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	59246	0	0
T3	740	78	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	42	0	0
T49	0	168	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	145	0	0
T107	0	313	0	0
T131	0	260	0	0
T150	0	85	0	0
T151	0	237	0	0
T185	0	135	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	62	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	3	0	0
T107	0	3	0	0
T131	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T185	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5992141	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5994422	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	68	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	3	0	0
T106	0	3	0	0
T107	0	3	0	0
T131	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T185	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	63	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	2	0	0
T106	0	3	0	0
T107	0	3	0	0
T131	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T185	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	62	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	3	0	0
T107	0	3	0	0
T131	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T185	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	62	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	3	0	0
T107	0	3	0	0
T131	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T185	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	59157	0	0
T3	740	76	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	40	0	0
T49	0	166	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	141	0	0
T107	0	309	0	0
T131	0	258	0	0
T150	0	82	0	0
T151	0	236	0	0
T185	0	132	0	0
T186	0	423	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	3038	0	0
T1	35031	0	0	0
T4	494	5	0	0
T5	435	3	0	0
T6	502	6	0	0
T14	423	2	0	0
T15	32180	0	0	0
T16	736	3	0	0
T17	0	3	0	0
T18	0	4	0	0
T19	0	4	0	0
T23	422	2	0	0
T24	650	3	0	0
T25	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	34	0	0
T50	766	0	0	0
T94	8937	0	0	0
T102	0	1	0	0
T106	0	2	0	0
T107	0	2	0	0
T109	800	0	0	0
T129	50356	0	0	0
T150	1114	1	0	0
T151	0	1	0	0
T162	0	2	0	0
T174	0	2	0	0
T176	0	1	0	0
T180	0	1	0	0
T185	0	1	0	0
T187	895	0	0	0
T188	522	0	0	0
T189	5489	0	0	0
T190	502	0	0	0
T191	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T10,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T31
0	1	Covered	T48
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T31
0	1	Covered	T3,T10,T31
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T31
1	-	Covered	T3,T10,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T31
DetectSt	168	Covered	T3,T10,T31
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T31
DebounceSt->IdleSt	163	Covered	T169,T100,T136
DetectSt->IdleSt	186	Covered	T48
DetectSt->StableSt	191	Covered	T3,T10,T31
IdleSt->DebounceSt	148	Covered	T3,T10,T31
StableSt->IdleSt	206	Covered	T3,T10,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T31
0	1	Covered	T3,T10,T31
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T31
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T169,T136,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T31
DetectSt	-	-	-	-	1	-	-	Covered	T48
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T31
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	137	0	0
CntIncr_A	6979152	55191	0	0
CntNoWrap_A	6979152	6335062	0	0
DetectStDropOut_A	6979152	1	0	0
DetectedOut_A	6979152	44352	0	0
DetectedPulseOut_A	6979152	65	0	0
DisabledIdleSt_A	6979152	6155257	0	0
DisabledNoDetection_A	6979152	6157535	0	0
EnterDebounceSt_A	6979152	71	0	0
EnterDetectSt_A	6979152	66	0	0
EnterStableSt_A	6979152	65	0	0
PulseIsPulse_A	6979152	65	0	0
StayInStableSt	6979152	44254	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	137	0	0
T3	740	4	0	0
T7	22914	0	0	0
T10	0	2	0	0
T30	2861	0	0	0
T31	0	4	0	0
T40	2361	0	0	0
T43	0	4	0	0
T44	0	4	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	2	0	0
T106	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	55191	0	0
T3	740	52	0	0
T7	22914	0	0	0
T10	0	35	0	0
T30	2861	0	0	0
T31	0	168	0	0
T40	2361	0	0	0
T43	0	152	0	0
T44	0	114	0	0
T48	0	48	0	0
T49	0	72	0	0
T50	0	58	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	92	0	0
T106	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335062	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1	0	0
T48	548	1	0	0
T58	18541	0	0	0
T71	1121	0	0	0
T79	496	0	0	0
T85	32692	0	0	0
T86	5667	0	0	0
T87	20776	0	0	0
T89	615	0	0	0
T90	1631	0	0	0
T193	1500	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	44352	0	0
T3	740	61	0	0
T7	22914	0	0	0
T10	0	100	0	0
T30	2861	0	0	0
T31	0	418	0	0
T40	2361	0	0	0
T43	0	84	0	0
T44	0	94	0	0
T49	0	85	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	272	0	0
T106	0	85	0	0
T169	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	65	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	2	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6155257	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6157535	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	71	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	66	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	65	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	2	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	65	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	2	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	44254	0	0
T3	740	58	0	0
T7	22914	0	0	0
T10	0	99	0	0
T30	2861	0	0	0
T31	0	415	0	0
T40	2361	0	0	0
T43	0	81	0	0
T44	0	91	0	0
T49	0	82	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	270	0	0
T106	0	82	0	0
T169	0	34	0	0
T185	0	165	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	31	0	0
T3	740	1	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T31,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T31,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T31,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T47
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T31,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T31,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T31,T47
0	1	Covered	T3,T31,T44
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T31,T47
1	-	Covered	T3,T31,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T31,T47
DetectSt	168	Covered	T3,T31,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T31,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T31,T47
DebounceSt->IdleSt	163	Covered	T43,T100,T194
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T31,T47
IdleSt->DebounceSt	148	Covered	T3,T31,T47
StableSt->IdleSt	206	Covered	T3,T31,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T31,T47
0	1	Covered	T3,T31,T47
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T31,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T31,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T31,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T194,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T31,T47
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T31,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T31,T44
StableSt	-	-	-	-	-	-	0	Covered	T3,T31,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	87	0	0
CntIncr_A	6979152	40944	0	0
CntNoWrap_A	6979152	6335112	0	0
DetectStDropOut_A	6979152	0	0	0
DetectedOut_A	6979152	39179	0	0
DetectedPulseOut_A	6979152	41	0	0
DisabledIdleSt_A	6979152	5944067	0	0
DisabledNoDetection_A	6979152	5946341	0	0
EnterDebounceSt_A	6979152	46	0	0
EnterDetectSt_A	6979152	41	0	0
EnterStableSt_A	6979152	41	0	0
PulseIsPulse_A	6979152	41	0	0
StayInStableSt	6979152	39116	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	6520	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	87	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T50	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	4	0	0
T131	0	2	0	0
T150	0	4	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	40944	0	0
T3	740	26	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	84	0	0
T40	2361	0	0	0
T43	0	76	0	0
T44	0	57	0	0
T47	0	88	0	0
T50	0	58	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	166	0	0
T131	0	51	0	0
T150	0	196	0	0
T179	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335112	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	39179	0	0
T3	740	79	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	39	0	0
T40	2361	0	0	0
T44	0	32	0	0
T47	0	37	0	0
T50	0	41	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	223	0	0
T131	0	19	0	0
T150	0	90	0	0
T179	0	115	0	0
T180	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	41	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	2	0	0
T131	0	1	0	0
T150	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5944067	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5946341	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	46	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	2	0	0
T131	0	1	0	0
T150	0	2	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	41	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	2	0	0
T131	0	1	0	0
T150	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	41	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	2	0	0
T131	0	1	0	0
T150	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	41	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	2	0	0
T131	0	1	0	0
T150	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	39116	0	0
T3	740	78	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	38	0	0
T40	2361	0	0	0
T44	0	31	0	0
T47	0	35	0	0
T50	0	39	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	221	0	0
T131	0	18	0	0
T150	0	87	0	0
T179	0	113	0	0
T180	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6520	0	0
T1	35031	10	0	0
T4	494	5	0	0
T5	435	4	0	0
T6	502	3	0	0
T14	423	2	0	0
T15	32180	30	0	0
T16	736	0	0	0
T19	0	5	0	0
T20	0	6	0	0
T22	0	6	0	0
T23	422	3	0	0
T24	650	0	0	0
T25	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	18	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	2	0	0
T119	0	1	0	0
T131	0	1	0	0
T150	0	1	0	0
T164	0	1	0	0
T175	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T10,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T31
0	1	Covered	T31,T102,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T31
0	1	Covered	T3,T31,T106
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T31
1	-	Covered	T3,T31,T106

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T31
DetectSt	168	Covered	T3,T10,T31
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T31
DebounceSt->IdleSt	163	Covered	T82,T158,T100
DetectSt->IdleSt	186	Covered	T31,T102,T196
DetectSt->StableSt	191	Covered	T3,T10,T31
IdleSt->DebounceSt	148	Covered	T3,T10,T31
StableSt->IdleSt	206	Covered	T3,T31,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T31
0	1	Covered	T3,T10,T31
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T31
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T136,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T31
DetectSt	-	-	-	-	1	-	-	Covered	T31,T102,T196
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T31,T106
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	146	0	0
CntIncr_A	6979152	65123	0	0
CntNoWrap_A	6979152	6335053	0	0
DetectStDropOut_A	6979152	3	0	0
DetectedOut_A	6979152	58805	0	0
DetectedPulseOut_A	6979152	67	0	0
DisabledIdleSt_A	6979152	6195261	0	0
DisabledNoDetection_A	6979152	6197537	0	0
EnterDebounceSt_A	6979152	79	0	0
EnterDetectSt_A	6979152	70	0	0
EnterStableSt_A	6979152	67	0	0
PulseIsPulse_A	6979152	67	0	0
StayInStableSt	6979152	58712	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	146	0	0
T3	740	4	0	0
T7	22914	0	0	0
T10	0	2	0	0
T30	2861	0	0	0
T31	0	4	0	0
T40	2361	0	0	0
T43	0	2	0	0
T47	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	2	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	6	0	0
T106	0	4	0	0
T152	0	4	0	0
T169	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	65123	0	0
T3	740	52	0	0
T7	22914	0	0	0
T10	0	35	0	0
T30	2861	0	0	0
T31	0	168	0	0
T40	2361	0	0	0
T43	0	76	0	0
T47	0	88	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	126	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	276	0	0
T106	0	62	0	0
T158	0	3429	0	0
T169	0	142	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335053	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	3	0	0
T31	19449	1	0	0
T36	15901	0	0	0
T45	542	0	0	0
T51	22099	0	0	0
T102	0	1	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T177	502	0	0	0
T196	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	58805	0	0
T3	740	36	0	0
T7	22914	0	0	0
T10	0	41	0	0
T30	2861	0	0	0
T31	0	41	0	0
T40	2361	0	0	0
T43	0	41	0	0
T47	0	38	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	85	0	0
T106	0	115	0	0
T107	0	166	0	0
T152	0	55	0	0
T169	0	144	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	67	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	2	0	0
T106	0	2	0	0
T107	0	4	0	0
T152	0	2	0	0
T169	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6195261	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6197537	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	79	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	2	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	3	0	0
T106	0	2	0	0
T158	0	1	0	0
T169	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	70	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	3	0	0
T106	0	2	0	0
T107	0	4	0	0
T152	0	2	0	0
T169	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	67	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	2	0	0
T106	0	2	0	0
T107	0	4	0	0
T152	0	2	0	0
T169	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	67	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	2	0	0
T106	0	2	0	0
T107	0	4	0	0
T152	0	2	0	0
T169	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	58712	0	0
T3	740	34	0	0
T7	22914	0	0	0
T10	0	39	0	0
T30	2861	0	0	0
T31	0	40	0	0
T40	2361	0	0	0
T43	0	39	0	0
T47	0	36	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	82	0	0
T106	0	113	0	0
T107	0	161	0	0
T152	0	53	0	0
T169	0	141	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	40	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T106	0	2	0	0
T107	0	3	0	0
T152	0	2	0	0
T162	0	1	0	0
T169	0	1	0	0
T174	0	1	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T31,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T45,T47
1	0	Covered	T4,T5,T6
1	1	Covered	T31,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T45,T46
0	1	Covered	T197,T198
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T45,T46
0	1	Covered	T31,T82,T44
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T45,T46
1	-	Covered	T31,T82,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T45,T46
DetectSt	168	Covered	T31,T45,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T31,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T45,T46
DebounceSt->IdleSt	163	Covered	T185,T107,T100
DetectSt->IdleSt	186	Covered	T197,T198
DetectSt->StableSt	191	Covered	T31,T45,T46
IdleSt->DebounceSt	148	Covered	T31,T45,T46
StableSt->IdleSt	206	Covered	T31,T82,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T45,T46
0	1	Covered	T31,T45,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T45,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T185,T107,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T45,T46
DetectSt	-	-	-	-	1	-	-	Covered	T197,T198
DetectSt	-	-	-	-	0	1	-	Covered	T31,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T82,T44
StableSt	-	-	-	-	-	-	0	Covered	T31,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	115	0	0
CntIncr_A	6979152	33429	0	0
CntNoWrap_A	6979152	6335084	0	0
DetectStDropOut_A	6979152	2	0	0
DetectedOut_A	6979152	3447	0	0
DetectedPulseOut_A	6979152	53	0	0
DisabledIdleSt_A	6979152	5967974	0	0
DisabledNoDetection_A	6979152	5970246	0	0
EnterDebounceSt_A	6979152	61	0	0
EnterDetectSt_A	6979152	55	0	0
EnterStableSt_A	6979152	53	0	0
PulseIsPulse_A	6979152	53	0	0
StayInStableSt	6979152	3364	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	6169	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	115	0	0
T31	19449	4	0	0
T36	15901	0	0	0
T44	0	4	0	0
T45	542	2	0	0
T46	0	2	0	0
T51	22099	0	0	0
T82	0	4	0	0
T106	0	4	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	4	0	0
T151	0	2	0	0
T169	0	2	0	0
T177	502	0	0	0
T185	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	33429	0	0
T31	19449	168	0	0
T36	15901	0	0	0
T44	0	114	0	0
T45	542	42	0	0
T46	0	46	0	0
T51	22099	0	0	0
T82	0	126	0	0
T106	0	62	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	102	0	0
T151	0	41	0	0
T169	0	71	0	0
T177	502	0	0	0
T185	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335084	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2	0	0
T182	30128	0	0	0
T197	931	1	0	0
T198	0	1	0	0
T200	411	0	0	0
T201	522	0	0	0
T202	1414	0	0	0
T203	412	0	0	0
T204	1387	0	0	0
T205	502	0	0	0
T206	406	0	0	0
T207	708	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	3447	0	0
T31	19449	231	0	0
T36	15901	0	0	0
T44	0	191	0	0
T45	542	48	0	0
T46	0	43	0	0
T51	22099	0	0	0
T82	0	81	0	0
T106	0	47	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	77	0	0
T151	0	78	0	0
T169	0	147	0	0
T177	502	0	0	0
T185	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	53	0	0
T31	19449	2	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	1	0	0
T46	0	1	0	0
T51	22099	0	0	0
T82	0	2	0	0
T106	0	2	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T177	502	0	0	0
T185	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5967974	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5970246	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	61	0	0
T31	19449	2	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	1	0	0
T46	0	1	0	0
T51	22099	0	0	0
T82	0	2	0	0
T106	0	2	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T177	502	0	0	0
T185	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	55	0	0
T31	19449	2	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	1	0	0
T46	0	1	0	0
T51	22099	0	0	0
T82	0	2	0	0
T106	0	2	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T177	502	0	0	0
T185	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	53	0	0
T31	19449	2	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	1	0	0
T46	0	1	0	0
T51	22099	0	0	0
T82	0	2	0	0
T106	0	2	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T177	502	0	0	0
T185	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	53	0	0
T31	19449	2	0	0
T36	15901	0	0	0
T44	0	2	0	0
T45	542	1	0	0
T46	0	1	0	0
T51	22099	0	0	0
T82	0	2	0	0
T106	0	2	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T177	502	0	0	0
T185	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	3364	0	0
T31	19449	228	0	0
T36	15901	0	0	0
T44	0	188	0	0
T45	542	46	0	0
T46	0	41	0	0
T51	22099	0	0	0
T82	0	78	0	0
T106	0	44	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	74	0	0
T151	0	77	0	0
T169	0	146	0	0
T177	502	0	0	0
T185	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6169	0	0
T1	35031	12	0	0
T4	494	10	0	0
T5	435	5	0	0
T6	502	6	0	0
T14	423	4	0	0
T15	32180	22	0	0
T16	736	0	0	0
T19	0	5	0	0
T20	0	4	0	0
T22	0	8	0	0
T23	422	2	0	0
T24	650	0	0	0
T25	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	22	0	0
T31	19449	1	0	0
T36	15901	0	0	0
T44	0	1	0	0
T45	542	0	0	0
T51	22099	0	0	0
T82	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	435	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T126	21517	0	0	0
T131	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T169	0	1	0	0
T177	502	0	0	0
T186	0	1	0	0