Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T31,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T31,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T31,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T31,T45
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T31,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T31,T45
0	1	Covered	T162,T208
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T31,T45
0	1	Covered	T10,T31,T169
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T31,T45
1	-	Covered	T10,T31,T169

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T31,T45
DetectSt	168	Covered	T10,T31,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T31,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T31,T45
DebounceSt->IdleSt	163	Covered	T186,T100,T209
DetectSt->IdleSt	186	Covered	T162,T208
DetectSt->StableSt	191	Covered	T10,T31,T45
IdleSt->DebounceSt	148	Covered	T10,T31,T45
StableSt->IdleSt	206	Covered	T10,T31,T169

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T31,T45
0	1	Covered	T10,T31,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T31,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T31,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T31,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T186,T209,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T31,T45
DetectSt	-	-	-	-	1	-	-	Covered	T162,T208
DetectSt	-	-	-	-	0	1	-	Covered	T10,T31,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T31,T169
StableSt	-	-	-	-	-	-	0	Covered	T10,T31,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	118	0	0
CntIncr_A	6979152	128170	0	0
CntNoWrap_A	6979152	6335081	0	0
DetectStDropOut_A	6979152	2	0	0
DetectedOut_A	6979152	45412	0	0
DetectedPulseOut_A	6979152	54	0	0
DisabledIdleSt_A	6979152	5959210	0	0
DisabledNoDetection_A	6979152	5961490	0	0
EnterDebounceSt_A	6979152	62	0	0
EnterDetectSt_A	6979152	56	0	0
EnterStableSt_A	6979152	54	0	0
PulseIsPulse_A	6979152	54	0	0
StayInStableSt	6979152	45333	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	118	0	0
T10	678	2	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	6	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	2	0	0
T49	0	2	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	4	0	0
T169	0	2	0	0
T186	0	3	0	0
T210	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	128170	0	0
T10	678	35	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	252	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	42	0	0
T49	0	36	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	41	0	0
T152	0	17	0	0
T153	0	170	0	0
T169	0	71	0	0
T186	0	192	0	0
T210	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335081	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2	0	0
T162	976	1	0	0
T208	0	1	0	0
T211	424	0	0	0
T212	426	0	0	0
T213	23377	0	0	0
T214	718	0	0	0
T215	422	0	0	0
T216	522	0	0	0
T217	22625	0	0	0
T218	635	0	0	0
T219	8402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45412	0	0
T10	678	99	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	97	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	47	0	0
T49	0	168	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	145	0	0
T152	0	125	0	0
T153	0	68	0	0
T169	0	440	0	0
T186	0	50	0	0
T210	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	54	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	3	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T169	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5959210	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5961490	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	62	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	3	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T169	0	1	0	0
T186	0	2	0	0
T210	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	56	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	3	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T169	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	54	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	3	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T169	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	54	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	3	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T169	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45333	0	0
T10	678	98	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	93	0	0
T34	781	0	0	0
T35	10543	0	0	0
T45	0	45	0	0
T49	0	166	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	144	0	0
T152	0	124	0	0
T153	0	65	0	0
T169	0	439	0	0
T186	0	49	0	0
T210	0	34	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	28	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T31	0	2	0	0
T34	781	0	0	0
T35	10543	0	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T144	407	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T162	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T45,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T43,T44
0	1	Covered	T183
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T43,T44
0	1	Covered	T44,T131,T153
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T43,T44
1	-	Covered	T44,T131,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T43,T44
DetectSt	168	Covered	T10,T43,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T43,T44
DebounceSt->IdleSt	163	Covered	T174,T100,T196
DetectSt->IdleSt	186	Covered	T183
DetectSt->StableSt	191	Covered	T10,T43,T44
IdleSt->DebounceSt	148	Covered	T10,T43,T44
StableSt->IdleSt	206	Covered	T44,T131,T153

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T43,T44
0	1	Covered	T10,T43,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T43,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T174,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T43,T44
DetectSt	-	-	-	-	1	-	-	Covered	T183
DetectSt	-	-	-	-	0	1	-	Covered	T10,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T131,T153
StableSt	-	-	-	-	-	-	0	Covered	T10,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	87	0	0
CntIncr_A	6979152	2311	0	0
CntNoWrap_A	6979152	6335112	0	0
DetectStDropOut_A	6979152	1	0	0
DetectedOut_A	6979152	2734	0	0
DetectedPulseOut_A	6979152	41	0	0
DisabledIdleSt_A	6979152	6287435	0	0
DisabledNoDetection_A	6979152	6289717	0	0
EnterDebounceSt_A	6979152	45	0	0
EnterDetectSt_A	6979152	42	0	0
EnterStableSt_A	6979152	41	0	0
PulseIsPulse_A	6979152	41	0	0
StayInStableSt	6979152	2671	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	6235	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	87	0	0
T10	678	2	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	2	0	0
T44	0	4	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	2	0	0
T131	0	2	0	0
T144	407	0	0	0
T153	0	2	0	0
T169	0	2	0	0
T174	0	3	0	0
T179	0	2	0	0
T210	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2311	0	0
T10	678	35	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	76	0	0
T44	0	114	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	47	0	0
T131	0	51	0	0
T144	407	0	0	0
T153	0	85	0	0
T169	0	71	0	0
T174	0	28	0	0
T179	0	95	0	0
T210	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335112	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1	0	0
T183	993	1	0	0
T196	15031	0	0	0
T220	6175	0	0	0
T221	504	0	0	0
T222	497	0	0	0
T223	502	0	0	0
T224	748	0	0	0
T225	4403	0	0	0
T226	522	0	0	0
T227	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2734	0	0
T10	678	42	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	41	0	0
T44	0	193	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	80	0	0
T131	0	18	0	0
T144	407	0	0	0
T153	0	207	0	0
T169	0	42	0	0
T174	0	59	0	0
T179	0	44	0	0
T210	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	41	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	1	0	0
T131	0	1	0	0
T144	407	0	0	0
T153	0	1	0	0
T169	0	1	0	0
T174	0	1	0	0
T179	0	1	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6287435	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6289717	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	1	0	0
T131	0	1	0	0
T144	407	0	0	0
T153	0	1	0	0
T169	0	1	0	0
T174	0	2	0	0
T179	0	1	0	0
T210	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	42	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	1	0	0
T131	0	1	0	0
T144	407	0	0	0
T153	0	1	0	0
T169	0	1	0	0
T174	0	1	0	0
T179	0	1	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	41	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	1	0	0
T131	0	1	0	0
T144	407	0	0	0
T153	0	1	0	0
T169	0	1	0	0
T174	0	1	0	0
T179	0	1	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	41	0	0
T10	678	1	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	1	0	0
T131	0	1	0	0
T144	407	0	0	0
T153	0	1	0	0
T169	0	1	0	0
T174	0	1	0	0
T179	0	1	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2671	0	0
T10	678	40	0	0
T11	565	0	0	0
T12	33056	0	0	0
T13	16755	0	0	0
T34	781	0	0	0
T35	10543	0	0	0
T43	0	39	0	0
T44	0	190	0	0
T68	1991	0	0	0
T98	455	0	0	0
T99	434	0	0	0
T107	0	78	0	0
T131	0	17	0	0
T144	407	0	0	0
T153	0	206	0	0
T169	0	40	0	0
T174	0	57	0	0
T179	0	43	0	0
T210	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6235	0	0
T1	35031	12	0	0
T4	494	9	0	0
T5	435	4	0	0
T6	502	5	0	0
T14	423	2	0	0
T15	32180	35	0	0
T16	736	0	0	0
T19	0	3	0	0
T20	0	3	0	0
T22	0	7	0	0
T23	422	2	0	0
T24	650	0	0	0
T25	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	18	0	0
T44	29004	1	0	0
T60	684	0	0	0
T91	771	0	0	0
T131	0	1	0	0
T136	0	1	0	0
T138	1814	0	0	0
T139	15295	0	0	0
T140	503	0	0	0
T153	0	1	0	0
T162	0	1	0	0
T165	424	0	0	0
T166	402	0	0	0
T167	8751	0	0	0
T168	405	0	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T195	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T47,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T47,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T47,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T47,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T47,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T47,T48
0	1	Covered	T228,T196,T229
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T48,T150
0	1	Covered	T3,T47,T150
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T48,T150
1	-	Covered	T3,T47,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T47,T48
DetectSt	168	Covered	T3,T47,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T47,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T47,T48
DebounceSt->IdleSt	163	Covered	T230,T163,T100
DetectSt->IdleSt	186	Covered	T228,T196,T229
DetectSt->StableSt	191	Covered	T3,T47,T48
IdleSt->DebounceSt	148	Covered	T3,T47,T48
StableSt->IdleSt	206	Covered	T3,T47,T150

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T47,T48
0	1	Covered	T3,T47,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T47,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T47,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T47,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T230,T163,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T47,T48
DetectSt	-	-	-	-	1	-	-	Covered	T228,T196,T229
DetectSt	-	-	-	-	0	1	-	Covered	T3,T47,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T47,T150
StableSt	-	-	-	-	-	-	0	Covered	T3,T48,T150
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	111	0	0
CntIncr_A	6979152	12613	0	0
CntNoWrap_A	6979152	6335088	0	0
DetectStDropOut_A	6979152	3	0	0
DetectedOut_A	6979152	4752	0	0
DetectedPulseOut_A	6979152	48	0	0
DisabledIdleSt_A	6979152	6302251	0	0
DisabledNoDetection_A	6979152	6304532	0	0
EnterDebounceSt_A	6979152	60	0	0
EnterDetectSt_A	6979152	51	0	0
EnterStableSt_A	6979152	48	0	0
PulseIsPulse_A	6979152	48	0	0
StayInStableSt	6979152	4685	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	111	0	0
T3	740	4	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	2	0	0
T48	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	2	0	0
T107	0	6	0	0
T150	0	4	0	0
T169	0	2	0	0
T186	0	2	0	0
T210	0	2	0	0
T230	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	12613	0	0
T3	740	52	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	88	0	0
T48	0	48	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	92	0	0
T107	0	213	0	0
T150	0	196	0	0
T169	0	71	0	0
T186	0	96	0	0
T210	0	36	0	0
T230	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335088	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	3	0	0
T164	8464	0	0	0
T196	0	1	0	0
T228	9038	1	0	0
T229	0	1	0	0
T231	422	0	0	0
T232	525	0	0	0
T233	402	0	0	0
T234	495	0	0	0
T235	6815	0	0	0
T236	424	0	0	0
T237	9420	0	0	0
T238	19268	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4752	0	0
T3	740	122	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	1	0	0
T48	0	90	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	270	0	0
T107	0	426	0	0
T150	0	226	0	0
T169	0	435	0	0
T174	0	104	0	0
T186	0	54	0	0
T210	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	48	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T107	0	3	0	0
T150	0	2	0	0
T169	0	1	0	0
T174	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6302251	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6304532	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	60	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T107	0	3	0	0
T150	0	2	0	0
T169	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0
T230	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	51	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T107	0	3	0	0
T150	0	2	0	0
T169	0	1	0	0
T174	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	48	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T107	0	3	0	0
T150	0	2	0	0
T169	0	1	0	0
T174	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	48	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T107	0	3	0	0
T150	0	2	0	0
T169	0	1	0	0
T174	0	1	0	0
T186	0	1	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4685	0	0
T3	740	120	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T48	0	88	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	269	0	0
T107	0	422	0	0
T150	0	224	0	0
T162	0	330	0	0
T169	0	433	0	0
T174	0	103	0	0
T186	0	52	0	0
T210	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	28	0	0
T3	740	2	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T107	0	2	0	0
T150	0	2	0	0
T162	0	1	0	0
T174	0	1	0	0
T195	0	1	0	0
T218	0	1	0	0
T239	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T10,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T31
0	1	Covered	T3,T10,T44
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T31
1	-	Covered	T3,T10,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T31
DetectSt	168	Covered	T3,T10,T31
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T31
DebounceSt->IdleSt	163	Covered	T218,T100,T183
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T10,T31
IdleSt->DebounceSt	148	Covered	T3,T10,T31
StableSt->IdleSt	206	Covered	T3,T10,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T31
0	1	Covered	T3,T10,T31
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T31
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T218,T183,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T44
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	91	0	0
CntIncr_A	6979152	2265	0	0
CntNoWrap_A	6979152	6335108	0	0
DetectStDropOut_A	6979152	0	0	0
DetectedOut_A	6979152	2745	0	0
DetectedPulseOut_A	6979152	43	0	0
DisabledIdleSt_A	6979152	6107531	0	0
DisabledNoDetection_A	6979152	6109805	0	0
EnterDebounceSt_A	6979152	48	0	0
EnterDetectSt_A	6979152	43	0	0
EnterStableSt_A	6979152	43	0	0
PulseIsPulse_A	6979152	43	0	0
StayInStableSt	6979152	2672	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	6118	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	91	0	0
T3	740	4	0	0
T7	22914	0	0	0
T10	0	2	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T44	0	2	0	0
T47	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	2	0	0
T107	0	2	0	0
T131	0	2	0	0
T174	0	2	0	0
T230	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2265	0	0
T3	740	52	0	0
T7	22914	0	0	0
T10	0	35	0	0
T30	2861	0	0	0
T31	0	84	0	0
T40	2361	0	0	0
T44	0	57	0	0
T47	0	88	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	31	0	0
T107	0	47	0	0
T131	0	51	0	0
T174	0	14	0	0
T230	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335108	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2745	0	0
T3	740	62	0	0
T7	22914	0	0	0
T10	0	21	0	0
T30	2861	0	0	0
T31	0	252	0	0
T40	2361	0	0	0
T44	0	131	0	0
T47	0	37	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	76	0	0
T107	0	8	0	0
T131	0	111	0	0
T174	0	59	0	0
T230	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	43	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T131	0	1	0	0
T174	0	1	0	0
T230	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6107531	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6109805	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	48	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T131	0	1	0	0
T174	0	1	0	0
T230	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	43	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T131	0	1	0	0
T174	0	1	0	0
T230	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	43	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T131	0	1	0	0
T174	0	1	0	0
T230	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	43	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T131	0	1	0	0
T174	0	1	0	0
T230	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2672	0	0
T3	740	59	0	0
T7	22914	0	0	0
T10	0	20	0	0
T30	2861	0	0	0
T31	0	250	0	0
T40	2361	0	0	0
T44	0	130	0	0
T47	0	35	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	74	0	0
T107	0	6	0	0
T131	0	110	0	0
T174	0	57	0	0
T230	0	50	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6118	0	0
T1	35031	14	0	0
T4	494	8	0	0
T5	435	2	0	0
T6	502	5	0	0
T14	423	5	0	0
T15	32180	31	0	0
T16	736	0	0	0
T19	0	6	0	0
T20	0	5	0	0
T22	0	6	0	0
T23	422	2	0	0
T24	650	0	0	0
T25	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	12	0	0
T3	740	1	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T44	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T131	0	1	0	0
T136	0	1	0	0
T148	0	1	0	0
T196	0	1	0	0
T240	0	1	0	0
T241	0	1	0	0
T242	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T45
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T10,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T45
0	1	Covered	T119,T241,T170
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T150
0	1	Covered	T3,T10,T45
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T150
1	-	Covered	T3,T10,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T45
DetectSt	168	Covered	T3,T10,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T45
DebounceSt->IdleSt	163	Covered	T150,T169,T186
DetectSt->IdleSt	186	Covered	T119,T241,T170
DetectSt->StableSt	191	Covered	T3,T10,T45
IdleSt->DebounceSt	148	Covered	T3,T10,T45
StableSt->IdleSt	206	Covered	T3,T10,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T45
0	1	Covered	T3,T10,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T169,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T45
DetectSt	-	-	-	-	1	-	-	Covered	T119,T241,T170
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T45
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T150
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	150	0	0
CntIncr_A	6979152	61684	0	0
CntNoWrap_A	6979152	6335049	0	0
DetectStDropOut_A	6979152	4	0	0
DetectedOut_A	6979152	5149	0	0
DetectedPulseOut_A	6979152	67	0	0
DisabledIdleSt_A	6979152	6199811	0	0
DisabledNoDetection_A	6979152	6202090	0	0
EnterDebounceSt_A	6979152	79	0	0
EnterDetectSt_A	6979152	71	0	0
EnterStableSt_A	6979152	67	0	0
PulseIsPulse_A	6979152	67	0	0
StayInStableSt	6979152	5059	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	150	0	0
T3	740	4	0	0
T7	22914	0	0	0
T10	0	2	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	2	0	0
T131	0	6	0	0
T150	0	5	0	0
T151	0	2	0	0
T169	0	3	0	0
T185	0	2	0	0
T230	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	61684	0	0
T3	740	52	0	0
T7	22914	0	0	0
T10	0	35	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	42	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	31	0	0
T131	0	153	0	0
T150	0	294	0	0
T151	0	41	0	0
T169	0	142	0	0
T185	0	12	0	0
T230	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335049	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	4	0	0
T119	43485	1	0	0
T146	1493	0	0	0
T170	0	1	0	0
T195	901	0	0	0
T241	0	1	0	0
T243	0	1	0	0
T244	423	0	0	0
T245	553	0	0	0
T246	449	0	0	0
T247	6293	0	0	0
T248	522	0	0	0
T249	32853	0	0	0
T250	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5149	0	0
T3	740	208	0	0
T7	22914	0	0	0
T10	0	100	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	313	0	0
T131	0	51	0	0
T150	0	78	0	0
T151	0	273	0	0
T169	0	43	0	0
T185	0	46	0	0
T230	0	53	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	67	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T131	0	3	0	0
T150	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T185	0	1	0	0
T230	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6199811	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6202090	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	79	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T131	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0
T169	0	2	0	0
T185	0	1	0	0
T230	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	71	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T131	0	3	0	0
T150	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T185	0	1	0	0
T230	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	67	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T131	0	3	0	0
T150	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T185	0	1	0	0
T230	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	67	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	1	0	0
T131	0	3	0	0
T150	0	2	0	0
T151	0	1	0	0
T169	0	1	0	0
T185	0	1	0	0
T230	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5059	0	0
T3	740	205	0	0
T7	22914	0	0	0
T10	0	99	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T106	0	311	0	0
T131	0	47	0	0
T150	0	76	0	0
T151	0	272	0	0
T152	0	139	0	0
T169	0	42	0	0
T185	0	45	0	0
T230	0	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	43	0	0
T3	740	1	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T45	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	1	0	0
T131	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T169	0	1	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T10,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T31
0	1	Covered	T3,T82,T150
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T31
1	-	Covered	T3,T82,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T31
DetectSt	168	Covered	T3,T10,T31
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T31
DebounceSt->IdleSt	163	Covered	T100,T183,T251
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T10,T31
IdleSt->DebounceSt	148	Covered	T3,T10,T31
StableSt->IdleSt	206	Covered	T3,T31,T82

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T31
0	1	Covered	T3,T10,T31
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T31
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T251,T252
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T82,T150
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	94	0	0
CntIncr_A	6979152	85592	0	0
CntNoWrap_A	6979152	6335105	0	0
DetectStDropOut_A	6979152	0	0	0
DetectedOut_A	6979152	57829	0	0
DetectedPulseOut_A	6979152	45	0	0
DisabledIdleSt_A	6979152	5968806	0	0
DisabledNoDetection_A	6979152	5971083	0	0
EnterDebounceSt_A	6979152	49	0	0
EnterDetectSt_A	6979152	45	0	0
EnterStableSt_A	6979152	45	0	0
PulseIsPulse_A	6979152	45	0	0
StayInStableSt	6979152	57759	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6979152	6829	0	0
gen_low_level_sva.LowLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	94	0	0
T3	740	2	0	0
T7	22914	0	0	0
T10	0	2	0	0
T30	2861	0	0	0
T31	0	2	0	0
T40	2361	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	2	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	2	0	0
T131	0	4	0	0
T150	0	6	0	0
T169	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	85592	0	0
T3	740	26	0	0
T7	22914	0	0	0
T10	0	35	0	0
T30	2861	0	0	0
T31	0	84	0	0
T40	2361	0	0	0
T43	0	76	0	0
T44	0	57	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	63	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	92	0	0
T131	0	102	0	0
T150	0	294	0	0
T169	0	142	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6335105	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	57829	0	0
T3	740	42	0	0
T7	22914	0	0	0
T10	0	98	0	0
T30	2861	0	0	0
T31	0	126	0	0
T40	2361	0	0	0
T43	0	163	0	0
T44	0	142	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	79	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	45	0	0
T131	0	151	0	0
T150	0	123	0	0
T169	0	190	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T3	740	1	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	1	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T131	0	2	0	0
T150	0	3	0	0
T169	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5968806	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5971083	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	49	0	0
T3	740	1	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	1	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T131	0	2	0	0
T150	0	3	0	0
T169	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T3	740	1	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	1	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T131	0	2	0	0
T150	0	3	0	0
T169	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T3	740	1	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	1	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T131	0	2	0	0
T150	0	3	0	0
T169	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45	0	0
T3	740	1	0	0
T7	22914	0	0	0
T10	0	1	0	0
T30	2861	0	0	0
T31	0	1	0	0
T40	2361	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	1	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	1	0	0
T131	0	2	0	0
T150	0	3	0	0
T169	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	57759	0	0
T3	740	41	0	0
T7	22914	0	0	0
T10	0	96	0	0
T30	2861	0	0	0
T31	0	124	0	0
T40	2361	0	0	0
T43	0	161	0	0
T44	0	140	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	78	0	0
T83	406	0	0	0
T84	421	0	0	0
T102	0	43	0	0
T131	0	149	0	0
T150	0	119	0	0
T169	0	187	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6829	0	0
T1	35031	16	0	0
T4	494	12	0	0
T5	435	4	0	0
T6	502	4	0	0
T14	423	3	0	0
T15	32180	26	0	0
T16	736	0	0	0
T19	0	5	0	0
T20	0	5	0	0
T22	0	8	0	0
T23	422	3	0	0
T24	650	0	0	0
T25	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	19	0	0
T3	740	1	0	0
T7	22914	0	0	0
T30	2861	0	0	0
T40	2361	0	0	0
T72	412	0	0	0
T73	421	0	0	0
T74	511	0	0	0
T75	446	0	0	0
T82	0	1	0	0
T83	406	0	0	0
T84	421	0	0	0
T107	0	1	0	0
T131	0	2	0	0
T150	0	2	0	0
T152	0	1	0	0
T169	0	1	0	0
T175	0	1	0	0
T218	0	1	0	0
T239	0	1	0	0