Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T36
1	0	Covered	T15,T35,T36
1	1	Covered	T15,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T35,T36
0	1	Covered	T35,T36,T86
1	0	Covered	T15,T35,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T51,T52,T53
0	1	Covered	T51,T52,T53
1	0	Covered	T85,T103,T100

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T51,T52,T53
1	-	Covered	T51,T52,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T35,T36
DetectSt	168	Covered	T15,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T51,T52,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T35,T36
DebounceSt->IdleSt	163	Covered	T88,T253,T100
DetectSt->IdleSt	186	Covered	T15,T35,T36
DetectSt->StableSt	191	Covered	T51,T52,T53
IdleSt->DebounceSt	148	Covered	T15,T35,T36
StableSt->IdleSt	206	Covered	T51,T52,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T35,T36
0	1	Covered	T15,T35,T36
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T35,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T15,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T253,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T15,T35,T36
DetectSt	-	-	-	-	0	1	-	Covered	T51,T52,T53
DetectSt	-	-	-	-	0	0	-	Covered	T15,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T51,T52,T53
StableSt	-	-	-	-	-	-	0	Covered	T51,T52,T53
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	3095	0	0
CntIncr_A	6979152	104014	0	0
CntNoWrap_A	6979152	6332104	0	0
DetectStDropOut_A	6979152	411	0	0
DetectedOut_A	6979152	75340	0	0
DetectedPulseOut_A	6979152	887	0	0
DisabledIdleSt_A	6979152	5901358	0	0
DisabledNoDetection_A	6979152	5903486	0	0
EnterDebounceSt_A	6979152	1569	0	0
EnterDetectSt_A	6979152	1526	0	0
EnterStableSt_A	6979152	887	0	0
PulseIsPulse_A	6979152	887	0	0
StayInStableSt	6979152	74342	0	0
gen_high_event_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	760	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	3095	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	16	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	32	0	0
T36	0	58	0	0
T51	0	42	0	0
T52	0	42	0	0
T53	0	54	0	0
T85	0	46	0	0
T86	0	24	0	0
T87	0	14	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	104014	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	447	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	887	0	0
T36	0	1519	0	0
T51	0	1575	0	0
T52	0	903	0	0
T53	0	1296	0	0
T85	0	1380	0	0
T86	0	727	0	0
T87	0	539	0	0
T88	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6332104	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31685	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	411	0	0
T31	19449	0	0	0
T35	10543	6	0	0
T36	15901	16	0	0
T42	31493	0	0	0
T45	542	0	0	0
T86	0	12	0	0
T103	0	8	0	0
T110	0	7	0	0
T111	0	5	0	0
T112	0	15	0	0
T113	0	15	0	0
T117	0	29	0	0
T118	0	12	0	0
T121	510	0	0	0
T122	403	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	75340	0	0
T51	22099	2186	0	0
T52	0	1501	0	0
T53	0	1497	0	0
T55	56340	0	0	0
T76	509	0	0	0
T77	496	0	0	0
T78	496	0	0	0
T85	0	497	0	0
T87	0	296	0	0
T126	21517	0	0	0
T127	478	0	0	0
T128	10724	0	0	0
T254	0	1331	0	0
T255	0	124	0	0
T256	0	82	0	0
T257	0	674	0	0
T258	0	1795	0	0
T259	823	0	0	0
T260	445	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	887	0	0
T51	22099	21	0	0
T52	0	21	0	0
T53	0	27	0	0
T55	56340	0	0	0
T76	509	0	0	0
T77	496	0	0	0
T78	496	0	0	0
T85	0	23	0	0
T87	0	7	0	0
T126	21517	0	0	0
T127	478	0	0	0
T128	10724	0	0	0
T254	0	11	0	0
T255	0	4	0	0
T256	0	1	0	0
T257	0	11	0	0
T258	0	21	0	0
T259	823	0	0	0
T260	445	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5901358	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	28696	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5903486	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	28708	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1569	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	8	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	16	0	0
T36	0	29	0	0
T51	0	21	0	0
T52	0	21	0	0
T53	0	27	0	0
T85	0	23	0	0
T86	0	12	0	0
T87	0	7	0	0
T88	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1526	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	8	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	16	0	0
T36	0	29	0	0
T51	0	21	0	0
T52	0	21	0	0
T53	0	27	0	0
T85	0	23	0	0
T86	0	12	0	0
T87	0	7	0	0
T110	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	887	0	0
T51	22099	21	0	0
T52	0	21	0	0
T53	0	27	0	0
T55	56340	0	0	0
T76	509	0	0	0
T77	496	0	0	0
T78	496	0	0	0
T85	0	23	0	0
T87	0	7	0	0
T126	21517	0	0	0
T127	478	0	0	0
T128	10724	0	0	0
T254	0	11	0	0
T255	0	4	0	0
T256	0	1	0	0
T257	0	11	0	0
T258	0	21	0	0
T259	823	0	0	0
T260	445	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	887	0	0
T51	22099	21	0	0
T52	0	21	0	0
T53	0	27	0	0
T55	56340	0	0	0
T76	509	0	0	0
T77	496	0	0	0
T78	496	0	0	0
T85	0	23	0	0
T87	0	7	0	0
T126	21517	0	0	0
T127	478	0	0	0
T128	10724	0	0	0
T254	0	11	0	0
T255	0	4	0	0
T256	0	1	0	0
T257	0	11	0	0
T258	0	21	0	0
T259	823	0	0	0
T260	445	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	74342	0	0
T51	22099	2161	0	0
T52	0	1478	0	0
T53	0	1470	0	0
T55	56340	0	0	0
T76	509	0	0	0
T77	496	0	0	0
T78	496	0	0	0
T85	0	474	0	0
T87	0	289	0	0
T126	21517	0	0	0
T127	478	0	0	0
T128	10724	0	0	0
T254	0	1320	0	0
T255	0	120	0	0
T256	0	80	0	0
T257	0	661	0	0
T258	0	1769	0	0
T259	823	0	0	0
T260	445	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	760	0	0
T51	22099	17	0	0
T52	0	19	0	0
T53	0	27	0	0
T55	56340	0	0	0
T76	509	0	0	0
T77	496	0	0	0
T78	496	0	0	0
T85	0	10	0	0
T87	0	7	0	0
T126	21517	0	0	0
T127	478	0	0	0
T128	10724	0	0	0
T254	0	11	0	0
T255	0	4	0	0
T257	0	9	0	0
T258	0	16	0	0
T259	823	0	0	0
T260	445	0	0	0
T261	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T15,T2
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T54,T13,T31
1	0	Covered	T100,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T100,T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T1,T2,T54
DetectSt->IdleSt	186	Covered	T54,T13,T31
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T54,T13,T31
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	975	0	0
CntIncr_A	6979152	45359	0	0
CntNoWrap_A	6979152	6334224	0	0
DetectStDropOut_A	6979152	77	0	0
DetectedOut_A	6979152	16608	0	0
DetectedPulseOut_A	6979152	380	0	0
DisabledIdleSt_A	6979152	5960299	0	0
DisabledNoDetection_A	6979152	5961923	0	0
EnterDebounceSt_A	6979152	517	0	0
EnterDetectSt_A	6979152	460	0	0
EnterStableSt_A	6979152	380	0	0
PulseIsPulse_A	6979152	380	0	0
StayInStableSt	6979152	16190	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	339	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	975	0	0
T1	35031	23	0	0
T2	0	9	0	0
T7	0	2	0	0
T9	0	9	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	24	0	0
T42	0	23	0	0
T54	0	21	0	0
T108	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	45359	0	0
T1	35031	1361	0	0
T2	0	389	0	0
T7	0	159	0	0
T9	0	390	0	0
T12	0	124	0	0
T13	0	326	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	624	0	0
T42	0	1171	0	0
T54	0	454	0	0
T108	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6334224	0	0
T1	35031	34510	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	77	0	0
T8	1533	0	0	0
T13	0	2	0	0
T31	0	12	0	0
T33	766	0	0	0
T41	702	0	0	0
T54	12268	10	0	0
T59	0	8	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T95	424	0	0	0
T100	0	1	0	0
T114	0	6	0	0
T115	0	2	0	0
T116	0	10	0	0
T119	0	2	0	0
T120	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	16608	0	0
T1	35031	56	0	0
T2	0	155	0	0
T7	0	16	0	0
T9	0	24	0	0
T12	0	100	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T42	0	1068	0	0
T51	0	233	0	0
T126	0	155	0	0
T127	0	3	0	0
T128	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	380	0	0
T1	35031	11	0	0
T2	0	4	0	0
T7	0	1	0	0
T9	0	4	0	0
T12	0	2	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T42	0	11	0	0
T51	0	3	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5960299	0	0
T1	35031	30216	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5961923	0	0
T1	35031	30216	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	517	0	0
T1	35031	12	0	0
T2	0	5	0	0
T7	0	1	0	0
T9	0	5	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	12	0	0
T42	0	12	0	0
T54	0	11	0	0
T108	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	460	0	0
T1	35031	11	0	0
T2	0	4	0	0
T7	0	1	0	0
T9	0	4	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	12	0	0
T42	0	11	0	0
T51	0	3	0	0
T54	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	380	0	0
T1	35031	11	0	0
T2	0	4	0	0
T7	0	1	0	0
T9	0	4	0	0
T12	0	2	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T42	0	11	0	0
T51	0	3	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	380	0	0
T1	35031	11	0	0
T2	0	4	0	0
T7	0	1	0	0
T9	0	4	0	0
T12	0	2	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T42	0	11	0	0
T51	0	3	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	16190	0	0
T1	35031	45	0	0
T2	0	151	0	0
T7	0	15	0	0
T9	0	20	0	0
T12	0	98	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T42	0	1057	0	0
T51	0	230	0	0
T126	0	153	0	0
T127	0	2	0	0
T128	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	339	0	0
T1	35031	11	0	0
T2	0	4	0	0
T7	0	1	0	0
T9	0	4	0	0
T12	0	2	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T42	0	11	0	0
T51	0	3	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T36
1	0	Covered	T15,T35,T36
1	1	Covered	T15,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T35,T36
0	1	Covered	T36,T52,T53
1	0	Covered	T35,T36,T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T51,T87
0	1	Covered	T15,T51,T87
1	0	Covered	T35,T67,T238

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T35,T51
1	-	Covered	T15,T51,T87

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T35,T36
DetectSt	168	Covered	T15,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T15,T35,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T35,T36
DebounceSt->IdleSt	163	Covered	T88,T253,T100
DetectSt->IdleSt	186	Covered	T35,T36,T52
DetectSt->StableSt	191	Covered	T15,T35,T51
IdleSt->DebounceSt	148	Covered	T15,T35,T36
StableSt->IdleSt	206	Covered	T15,T35,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T35,T36
0	1	Covered	T15,T35,T36
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T35,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T15,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T253,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T35,T36,T52
DetectSt	-	-	-	-	0	1	-	Covered	T15,T35,T51
DetectSt	-	-	-	-	0	0	-	Covered	T15,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T15,T35,T51
StableSt	-	-	-	-	-	-	0	Covered	T15,T51,T87
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	3177	0	0
CntIncr_A	6979152	102297	0	0
CntNoWrap_A	6979152	6332022	0	0
DetectStDropOut_A	6979152	450	0	0
DetectedOut_A	6979152	71283	0	0
DetectedPulseOut_A	6979152	852	0	0
DisabledIdleSt_A	6979152	5907954	0	0
DisabledNoDetection_A	6979152	5910067	0	0
EnterDebounceSt_A	6979152	1617	0	0
EnterDetectSt_A	6979152	1562	0	0
EnterStableSt_A	6979152	852	0	0
PulseIsPulse_A	6979152	852	0	0
StayInStableSt	6979152	70305	0	0
gen_high_event_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	703	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	3177	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	44	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	30	0	0
T36	0	66	0	0
T51	0	18	0	0
T52	0	32	0	0
T53	0	36	0	0
T85	0	52	0	0
T86	0	18	0	0
T87	0	52	0	0
T88	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	102297	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	616	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	838	0	0
T36	0	1730	0	0
T51	0	666	0	0
T52	0	867	0	0
T53	0	974	0	0
T85	0	2121	0	0
T86	0	546	0	0
T87	0	1534	0	0
T88	0	881	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6332022	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31657	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	450	0	0
T36	15901	16	0	0
T51	22099	0	0	0
T52	0	9	0	0
T53	0	10	0	0
T55	56340	0	0	0
T85	0	13	0	0
T86	0	9	0	0
T88	0	4	0	0
T108	435	0	0	0
T110	0	22	0	0
T111	0	28	0	0
T112	0	3	0	0
T125	427	0	0	0
T126	21517	0	0	0
T127	478	0	0	0
T177	502	0	0	0
T259	823	0	0	0
T260	445	0	0	0
T261	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	71283	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	3127	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	1	0	0
T51	0	1173	0	0
T87	0	3697	0	0
T253	0	121	0	0
T254	0	1104	0	0
T255	0	903	0	0
T257	0	1600	0	0
T258	0	2421	0	0
T262	0	370	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	852	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	1	0	0
T51	0	9	0	0
T87	0	26	0	0
T253	0	1	0	0
T254	0	9	0	0
T255	0	25	0	0
T257	0	24	0	0
T258	0	26	0	0
T262	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5907954	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	26189	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5910067	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	26189	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1617	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	15	0	0
T36	0	33	0	0
T51	0	9	0	0
T52	0	16	0	0
T53	0	18	0	0
T85	0	26	0	0
T86	0	9	0	0
T87	0	26	0	0
T88	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1562	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	15	0	0
T36	0	33	0	0
T51	0	9	0	0
T52	0	16	0	0
T53	0	18	0	0
T85	0	26	0	0
T86	0	9	0	0
T87	0	26	0	0
T88	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	852	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	1	0	0
T51	0	9	0	0
T87	0	26	0	0
T253	0	1	0	0
T254	0	9	0	0
T255	0	25	0	0
T257	0	24	0	0
T258	0	26	0	0
T262	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	852	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	1	0	0
T51	0	9	0	0
T87	0	26	0	0
T253	0	1	0	0
T254	0	9	0	0
T255	0	25	0	0
T257	0	24	0	0
T258	0	26	0	0
T262	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	70305	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	3093	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T51	0	1161	0	0
T87	0	3666	0	0
T253	0	120	0	0
T254	0	1092	0	0
T255	0	876	0	0
T257	0	1572	0	0
T258	0	2389	0	0
T262	0	359	0	0
T263	0	1268	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	703	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	10	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T51	0	6	0	0
T87	0	21	0	0
T253	0	1	0	0
T254	0	6	0	0
T255	0	23	0	0
T257	0	20	0	0
T258	0	20	0	0
T262	0	11	0	0
T263	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T15,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T1,T15,T2
1	1	Covered	T1,T15,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T2
0	1	Covered	T1,T2,T9
1	0	Covered	T100,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T7,T54
0	1	Covered	T7,T54,T12
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T7,T54
1	-	Covered	T7,T54,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T2
DetectSt	168	Covered	T1,T15,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T15,T7,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T2
DebounceSt->IdleSt	163	Covered	T15,T2,T54
DetectSt->IdleSt	186	Covered	T1,T2,T9
DetectSt->StableSt	191	Covered	T15,T7,T54
IdleSt->DebounceSt	148	Covered	T1,T15,T2
StableSt->IdleSt	206	Covered	T15,T7,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T15,T2
0	1	Covered	T1,T15,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T2,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T2
DetectSt	-	-	-	-	1	-	-	Covered	T1,T2,T9
DetectSt	-	-	-	-	0	1	-	Covered	T15,T7,T54
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T2
StableSt	-	-	-	-	-	-	1	Covered	T7,T54,T12
StableSt	-	-	-	-	-	-	0	Covered	T15,T7,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	888	0	0
CntIncr_A	6979152	44436	0	0
CntNoWrap_A	6979152	6334311	0	0
DetectStDropOut_A	6979152	66	0	0
DetectedOut_A	6979152	16356	0	0
DetectedPulseOut_A	6979152	352	0	0
DisabledIdleSt_A	6979152	5965049	0	0
DisabledNoDetection_A	6979152	5966707	0	0
EnterDebounceSt_A	6979152	467	0	0
EnterDetectSt_A	6979152	422	0	0
EnterStableSt_A	6979152	352	0	0
PulseIsPulse_A	6979152	352	0	0
StayInStableSt	6979152	15956	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	300	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	888	0	0
T1	35031	8	0	0
T2	0	3	0	0
T7	0	4	0	0
T9	0	2	0	0
T12	0	26	0	0
T13	0	8	0	0
T14	423	0	0	0
T15	32180	17	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	12	0	0
T42	0	3	0	0
T54	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	44436	0	0
T1	35031	492	0	0
T2	0	172	0	0
T7	0	338	0	0
T9	0	100	0	0
T12	0	1182	0	0
T13	0	340	0	0
T14	423	0	0	0
T15	32180	449	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	276	0	0
T42	0	247	0	0
T54	0	202	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6334311	0	0
T1	35031	34525	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31684	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	66	0	0
T1	35031	4	0	0
T2	0	1	0	0
T9	0	1	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T114	0	4	0	0
T129	0	8	0	0
T264	0	6	0	0
T265	0	2	0	0
T266	0	1	0	0
T267	0	3	0	0
T268	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	16356	0	0
T2	18620	0	0	0
T3	740	0	0	0
T7	0	11	0	0
T12	0	258	0	0
T13	0	314	0	0
T15	32180	443	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	35	0	0
T42	0	30	0	0
T51	0	230	0	0
T54	0	19	0	0
T126	0	562	0	0
T128	0	132	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	352	0	0
T2	18620	0	0	0
T3	740	0	0	0
T7	0	2	0	0
T12	0	12	0	0
T13	0	4	0	0
T15	32180	8	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	6	0	0
T42	0	1	0	0
T51	0	3	0	0
T54	0	4	0	0
T126	0	7	0	0
T128	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5965049	0	0
T1	35031	30216	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	28586	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5966707	0	0
T1	35031	30216	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	28587	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	467	0	0
T1	35031	4	0	0
T2	0	2	0	0
T7	0	2	0	0
T9	0	1	0	0
T12	0	14	0	0
T13	0	4	0	0
T14	423	0	0	0
T15	32180	9	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	6	0	0
T42	0	2	0	0
T54	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	422	0	0
T1	35031	4	0	0
T2	0	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T12	0	12	0	0
T13	0	4	0	0
T14	423	0	0	0
T15	32180	8	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	6	0	0
T42	0	1	0	0
T54	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	352	0	0
T2	18620	0	0	0
T3	740	0	0	0
T7	0	2	0	0
T12	0	12	0	0
T13	0	4	0	0
T15	32180	8	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	6	0	0
T42	0	1	0	0
T51	0	3	0	0
T54	0	4	0	0
T126	0	7	0	0
T128	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	352	0	0
T2	18620	0	0	0
T3	740	0	0	0
T7	0	2	0	0
T12	0	12	0	0
T13	0	4	0	0
T15	32180	8	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	6	0	0
T42	0	1	0	0
T51	0	3	0	0
T54	0	4	0	0
T126	0	7	0	0
T128	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	15956	0	0
T2	18620	0	0	0
T3	740	0	0	0
T7	0	9	0	0
T12	0	246	0	0
T13	0	310	0	0
T15	32180	427	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	29	0	0
T42	0	29	0	0
T51	0	227	0	0
T54	0	15	0	0
T126	0	555	0	0
T128	0	130	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	300	0	0
T7	22914	2	0	0
T12	0	12	0	0
T13	0	4	0	0
T31	0	6	0	0
T32	664	0	0	0
T33	766	0	0	0
T41	702	0	0	0
T42	0	1	0	0
T51	0	3	0	0
T54	12268	4	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T75	446	0	0	0
T126	0	7	0	0
T128	0	2	0	0
T269	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T36
1	0	Covered	T15,T35,T36
1	1	Covered	T15,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T35,T36
0	1	Covered	T36,T53,T86
1	0	Covered	T15,T36,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T51,T52
0	1	Covered	T35,T51,T52
1	0	Covered	T67,T270

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T51,T52
1	-	Covered	T35,T51,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T35,T36
DetectSt	168	Covered	T15,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T51,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T35,T36
DebounceSt->IdleSt	163	Covered	T88,T253,T100
DetectSt->IdleSt	186	Covered	T15,T36,T53
DetectSt->StableSt	191	Covered	T35,T51,T52
IdleSt->DebounceSt	148	Covered	T15,T35,T36
StableSt->IdleSt	206	Covered	T35,T51,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T35,T36
0	1	Covered	T15,T35,T36
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T35,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T15,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T253,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T15,T36,T53
DetectSt	-	-	-	-	0	1	-	Covered	T35,T51,T52
DetectSt	-	-	-	-	0	0	-	Covered	T15,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T35,T51,T52
StableSt	-	-	-	-	-	-	0	Covered	T35,T51,T52
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	2942	0	0
CntIncr_A	6979152	93534	0	0
CntNoWrap_A	6979152	6332257	0	0
DetectStDropOut_A	6979152	412	0	0
DetectedOut_A	6979152	67887	0	0
DetectedPulseOut_A	6979152	841	0	0
DisabledIdleSt_A	6979152	5905530	0	0
DisabledNoDetection_A	6979152	5907656	0	0
EnterDebounceSt_A	6979152	1490	0	0
EnterDetectSt_A	6979152	1452	0	0
EnterStableSt_A	6979152	841	0	0
PulseIsPulse_A	6979152	841	0	0
StayInStableSt	6979152	66932	0	0
gen_high_event_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	719	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2942	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	16	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	10	0	0
T36	0	64	0	0
T51	0	20	0	0
T52	0	14	0	0
T53	0	12	0	0
T85	0	46	0	0
T86	0	24	0	0
T87	0	52	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	93534	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	447	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	140	0	0
T36	0	1689	0	0
T51	0	740	0	0
T52	0	196	0	0
T53	0	324	0	0
T85	0	1242	0	0
T86	0	731	0	0
T87	0	3068	0	0
T88	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6332257	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31685	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	412	0	0
T36	15901	7	0	0
T51	22099	0	0	0
T53	0	2	0	0
T55	56340	0	0	0
T86	0	12	0	0
T103	0	21	0	0
T108	435	0	0	0
T110	0	13	0	0
T111	0	13	0	0
T112	0	24	0	0
T113	0	13	0	0
T117	0	24	0	0
T125	427	0	0	0
T126	21517	0	0	0
T127	478	0	0	0
T177	502	0	0	0
T254	0	8	0	0
T259	823	0	0	0
T260	445	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	67887	0	0
T31	19449	0	0	0
T35	10543	412	0	0
T36	15901	0	0	0
T42	31493	0	0	0
T45	542	0	0	0
T51	0	959	0	0
T52	0	302	0	0
T85	0	8425	0	0
T121	510	0	0	0
T122	403	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T253	0	88	0	0
T255	0	44	0	0
T257	0	2108	0	0
T258	0	2851	0	0
T261	0	81	0	0
T262	0	73	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	841	0	0
T31	19449	0	0	0
T35	10543	5	0	0
T36	15901	0	0	0
T42	31493	0	0	0
T45	542	0	0	0
T51	0	10	0	0
T52	0	7	0	0
T85	0	23	0	0
T121	510	0	0	0
T122	403	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T253	0	1	0	0
T255	0	4	0	0
T257	0	27	0	0
T258	0	27	0	0
T261	0	3	0	0
T262	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5905530	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	28696	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5907656	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	28708	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1490	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	8	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	5	0	0
T36	0	32	0	0
T51	0	10	0	0
T52	0	7	0	0
T53	0	6	0	0
T85	0	23	0	0
T86	0	12	0	0
T87	0	26	0	0
T88	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1452	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	8	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	5	0	0
T36	0	32	0	0
T51	0	10	0	0
T52	0	7	0	0
T53	0	6	0	0
T85	0	23	0	0
T86	0	12	0	0
T87	0	26	0	0
T110	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	841	0	0
T31	19449	0	0	0
T35	10543	5	0	0
T36	15901	0	0	0
T42	31493	0	0	0
T45	542	0	0	0
T51	0	10	0	0
T52	0	7	0	0
T85	0	23	0	0
T121	510	0	0	0
T122	403	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T253	0	1	0	0
T255	0	4	0	0
T257	0	27	0	0
T258	0	27	0	0
T261	0	3	0	0
T262	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	841	0	0
T31	19449	0	0	0
T35	10543	5	0	0
T36	15901	0	0	0
T42	31493	0	0	0
T45	542	0	0	0
T51	0	10	0	0
T52	0	7	0	0
T85	0	23	0	0
T121	510	0	0	0
T122	403	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T253	0	1	0	0
T255	0	4	0	0
T257	0	27	0	0
T258	0	27	0	0
T261	0	3	0	0
T262	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	66932	0	0
T31	19449	0	0	0
T35	10543	405	0	0
T36	15901	0	0	0
T42	31493	0	0	0
T45	542	0	0	0
T51	0	948	0	0
T52	0	294	0	0
T85	0	8393	0	0
T121	510	0	0	0
T122	403	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T253	0	87	0	0
T255	0	40	0	0
T257	0	2078	0	0
T258	0	2815	0	0
T261	0	78	0	0
T262	0	67	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	719	0	0
T31	19449	0	0	0
T35	10543	3	0	0
T36	15901	0	0	0
T42	31493	0	0	0
T45	542	0	0	0
T51	0	9	0	0
T52	0	6	0	0
T85	0	14	0	0
T121	510	0	0	0
T122	403	0	0	0
T123	408	0	0	0
T124	523	0	0	0
T125	427	0	0	0
T253	0	1	0	0
T255	0	4	0	0
T257	0	24	0	0
T258	0	18	0	0
T261	0	3	0	0
T262	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T15,T2
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T54,T31,T271
1	0	Covered	T100,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T100,T101

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T1,T2,T7
DetectSt->IdleSt	186	Covered	T54,T31,T271
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T54,T31,T271
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	881	0	0
CntIncr_A	6979152	47708	0	0
CntNoWrap_A	6979152	6334318	0	0
DetectStDropOut_A	6979152	87	0	0
DetectedOut_A	6979152	17375	0	0
DetectedPulseOut_A	6979152	326	0	0
DisabledIdleSt_A	6979152	5967707	0	0
DisabledNoDetection_A	6979152	5969376	0	0
EnterDebounceSt_A	6979152	464	0	0
EnterDetectSt_A	6979152	418	0	0
EnterStableSt_A	6979152	326	0	0
PulseIsPulse_A	6979152	326	0	0
StayInStableSt	6979152	17008	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	283	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	881	0	0
T1	35031	19	0	0
T2	0	7	0	0
T7	0	15	0	0
T9	0	5	0	0
T12	0	3	0	0
T13	0	7	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	20	0	0
T35	0	4	0	0
T42	0	18	0	0
T54	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	47708	0	0
T1	35031	637	0	0
T2	0	394	0	0
T7	0	787	0	0
T9	0	132	0	0
T12	0	136	0	0
T13	0	515	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	515	0	0
T35	0	88	0	0
T42	0	1719	0	0
T54	0	153	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6334318	0	0
T1	35031	34514	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	87	0	0
T8	1533	0	0	0
T31	0	10	0	0
T33	766	0	0	0
T41	702	0	0	0
T54	12268	3	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T95	424	0	0	0
T119	0	13	0	0
T189	0	4	0	0
T264	0	1	0	0
T266	0	1	0	0
T271	0	4	0	0
T272	0	6	0	0
T273	0	10	0	0
T274	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	17375	0	0
T1	35031	530	0	0
T2	0	25	0	0
T7	0	527	0	0
T9	0	82	0	0
T12	0	15	0	0
T13	0	46	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	79	0	0
T42	0	41	0	0
T51	0	109	0	0
T126	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	326	0	0
T1	35031	9	0	0
T2	0	3	0	0
T7	0	7	0	0
T9	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	2	0	0
T42	0	9	0	0
T51	0	2	0	0
T126	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5967707	0	0
T1	35031	30216	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31701	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5969376	0	0
T1	35031	30216	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	464	0	0
T1	35031	10	0	0
T2	0	4	0	0
T7	0	8	0	0
T9	0	3	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	10	0	0
T35	0	2	0	0
T42	0	9	0	0
T54	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	418	0	0
T1	35031	9	0	0
T2	0	3	0	0
T7	0	7	0	0
T9	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T31	0	10	0	0
T35	0	2	0	0
T42	0	9	0	0
T54	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	326	0	0
T1	35031	9	0	0
T2	0	3	0	0
T7	0	7	0	0
T9	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	2	0	0
T42	0	9	0	0
T51	0	2	0	0
T126	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	326	0	0
T1	35031	9	0	0
T2	0	3	0	0
T7	0	7	0	0
T9	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	2	0	0
T42	0	9	0	0
T51	0	2	0	0
T126	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	17008	0	0
T1	35031	521	0	0
T2	0	22	0	0
T7	0	520	0	0
T9	0	80	0	0
T12	0	14	0	0
T13	0	43	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	76	0	0
T42	0	32	0	0
T51	0	107	0	0
T126	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	283	0	0
T1	35031	9	0	0
T2	0	3	0	0
T7	0	7	0	0
T9	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	1	0	0
T42	0	9	0	0
T51	0	2	0	0
T126	0	1	0	0