Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T36
1	0	Covered	T15,T35,T36
1	1	Covered	T15,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T35,T36
0	1	Covered	T86,T110,T254
1	0	Covered	T53,T85,T254

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T35,T36
0	1	Covered	T15,T35,T36
1	0	Covered	T275,T276

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T35,T36
1	-	Covered	T15,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T35,T36
DetectSt	168	Covered	T15,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T15,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T35,T36
DebounceSt->IdleSt	163	Covered	T88,T253,T100
DetectSt->IdleSt	186	Covered	T53,T85,T86
DetectSt->StableSt	191	Covered	T15,T35,T36
IdleSt->DebounceSt	148	Covered	T15,T35,T36
StableSt->IdleSt	206	Covered	T15,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T35,T36
0	1	Covered	T15,T35,T36
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T35,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T15,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T253,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T53,T85,T86
DetectSt	-	-	-	-	0	1	-	Covered	T15,T35,T36
DetectSt	-	-	-	-	0	0	-	Covered	T15,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T15,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T15,T35,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	2998	0	0
CntIncr_A	6979152	96302	0	0
CntNoWrap_A	6979152	6332201	0	0
DetectStDropOut_A	6979152	378	0	0
DetectedOut_A	6979152	74204	0	0
DetectedPulseOut_A	6979152	981	0	0
DisabledIdleSt_A	6979152	5902871	0	0
DisabledNoDetection_A	6979152	5904996	0	0
EnterDebounceSt_A	6979152	1520	0	0
EnterDetectSt_A	6979152	1478	0	0
EnterStableSt_A	6979152	981	0	0
PulseIsPulse_A	6979152	981	0	0
StayInStableSt	6979152	73108	0	0
gen_high_event_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	841	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	2998	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	44	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	46	0	0
T36	0	50	0	0
T51	0	42	0	0
T52	0	14	0	0
T53	0	28	0	0
T85	0	10	0	0
T86	0	46	0	0
T87	0	28	0	0
T88	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	96302	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	770	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	1127	0	0
T36	0	1275	0	0
T51	0	1575	0	0
T52	0	294	0	0
T53	0	767	0	0
T85	0	407	0	0
T86	0	1407	0	0
T87	0	1050	0	0
T88	0	974	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6332201	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31657	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	378	0	0
T58	18541	0	0	0
T59	46116	0	0	0
T71	1121	0	0	0
T79	496	0	0	0
T80	5141	0	0	0
T86	5667	23	0	0
T87	20776	0	0	0
T89	615	0	0	0
T90	1631	0	0	0
T110	0	25	0	0
T111	0	13	0	0
T112	0	27	0	0
T113	0	7	0	0
T117	0	7	0	0
T118	0	15	0	0
T193	1500	0	0	0
T254	0	20	0	0
T277	0	17	0	0
T278	0	20	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	74204	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	2973	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	1259	0	0
T36	0	2587	0	0
T51	0	2186	0	0
T52	0	204	0	0
T87	0	1603	0	0
T88	0	102	0	0
T255	0	636	0	0
T257	0	1243	0	0
T258	0	1127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	981	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	23	0	0
T36	0	25	0	0
T51	0	21	0	0
T52	0	7	0	0
T87	0	14	0	0
T88	0	6	0	0
T255	0	10	0	0
T257	0	23	0	0
T258	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5902871	0	0
T1	35031	34533	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	26189	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5904996	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	26189	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1520	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	23	0	0
T36	0	25	0	0
T51	0	21	0	0
T52	0	7	0	0
T53	0	14	0	0
T85	0	5	0	0
T86	0	23	0	0
T87	0	14	0	0
T88	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	1478	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	23	0	0
T36	0	25	0	0
T51	0	21	0	0
T52	0	7	0	0
T53	0	14	0	0
T85	0	5	0	0
T86	0	23	0	0
T87	0	14	0	0
T88	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	981	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	23	0	0
T36	0	25	0	0
T51	0	21	0	0
T52	0	7	0	0
T87	0	14	0	0
T88	0	6	0	0
T255	0	10	0	0
T257	0	23	0	0
T258	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	981	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	22	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	23	0	0
T36	0	25	0	0
T51	0	21	0	0
T52	0	7	0	0
T87	0	14	0	0
T88	0	6	0	0
T255	0	10	0	0
T257	0	23	0	0
T258	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	73108	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	2939	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	1234	0	0
T36	0	2558	0	0
T51	0	2161	0	0
T52	0	196	0	0
T87	0	1586	0	0
T88	0	96	0	0
T255	0	626	0	0
T257	0	1217	0	0
T258	0	1111	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	841	0	0
T2	18620	0	0	0
T3	740	0	0	0
T15	32180	10	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	21	0	0
T36	0	21	0	0
T51	0	17	0	0
T52	0	6	0	0
T87	0	11	0	0
T88	0	6	0	0
T255	0	10	0	0
T257	0	20	0	0
T258	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T15,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T1,T15,T2
1	1	Covered	T1,T15,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T2
0	1	Covered	T54,T13,T31
1	0	Covered	T100,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T2
0	1	Covered	T1,T2,T7
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T2
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T2
DetectSt	168	Covered	T1,T15,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T15,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T2
DebounceSt->IdleSt	163	Covered	T1,T2,T7
DetectSt->IdleSt	186	Covered	T54,T13,T31
DetectSt->StableSt	191	Covered	T1,T15,T2
IdleSt->DebounceSt	148	Covered	T1,T15,T2
StableSt->IdleSt	206	Covered	T1,T15,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T15,T2
0	1	Covered	T1,T15,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T100,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T2
DetectSt	-	-	-	-	1	-	-	Covered	T54,T13,T31
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6979152	882	0	0
CntIncr_A	6979152	44554	0	0
CntNoWrap_A	6979152	6334317	0	0
DetectStDropOut_A	6979152	48	0	0
DetectedOut_A	6979152	15471	0	0
DetectedPulseOut_A	6979152	364	0	0
DisabledIdleSt_A	6979152	5969169	0	0
DisabledNoDetection_A	6979152	5970848	0	0
EnterDebounceSt_A	6979152	469	0	0
EnterDetectSt_A	6979152	417	0	0
EnterStableSt_A	6979152	364	0	0
PulseIsPulse_A	6979152	364	0	0
StayInStableSt	6979152	15055	0	0
gen_high_level_sva.HighLevelEvent_A	6979152	6337531	0	0
gen_not_sticky_sva.StableStDropOut_A	6979152	308	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	882	0	0
T1	35031	23	0	0
T2	0	7	0	0
T7	0	10	0	0
T9	0	2	0	0
T12	0	26	0	0
T13	0	4	0	0
T14	423	0	0	0
T15	32180	24	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	5	0	0
T42	0	9	0	0
T54	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	44554	0	0
T1	35031	1064	0	0
T2	0	400	0	0
T7	0	614	0	0
T9	0	60	0	0
T12	0	1001	0	0
T13	0	326	0	0
T14	423	0	0	0
T15	32180	780	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	73	0	0
T42	0	762	0	0
T54	0	123	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6334317	0	0
T1	35031	34510	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	31677	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	48	0	0
T8	1533	0	0	0
T13	0	2	0	0
T31	0	1	0	0
T33	766	0	0	0
T41	702	0	0	0
T44	0	13	0	0
T54	12268	3	0	0
T62	525	0	0	0
T63	423	0	0	0
T64	524	0	0	0
T65	527	0	0	0
T66	413	0	0	0
T95	424	0	0	0
T128	0	2	0	0
T129	0	2	0	0
T265	0	2	0	0
T273	0	1	0	0
T279	0	6	0	0
T280	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	15471	0	0
T1	35031	353	0	0
T2	0	22	0	0
T7	0	259	0	0
T9	0	40	0	0
T12	0	472	0	0
T14	423	0	0	0
T15	32180	531	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	108	0	0
T36	0	349	0	0
T42	0	105	0	0
T51	0	154	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	364	0	0
T1	35031	11	0	0
T2	0	3	0	0
T7	0	4	0	0
T9	0	1	0	0
T12	0	13	0	0
T14	423	0	0	0
T15	32180	12	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T42	0	4	0	0
T51	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5969169	0	0
T1	35031	30216	0	0
T4	494	93	0	0
T5	435	34	0	0
T6	502	101	0	0
T14	423	22	0	0
T15	32180	28740	0	0
T16	736	335	0	0
T23	422	21	0	0
T24	650	249	0	0
T25	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	5970848	0	0
T1	35031	30216	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	28741	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	469	0	0
T1	35031	12	0	0
T2	0	4	0	0
T7	0	6	0	0
T9	0	1	0	0
T12	0	13	0	0
T13	0	2	0	0
T14	423	0	0	0
T15	32180	12	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	3	0	0
T42	0	5	0	0
T54	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	417	0	0
T1	35031	11	0	0
T2	0	3	0	0
T7	0	4	0	0
T9	0	1	0	0
T12	0	13	0	0
T13	0	2	0	0
T14	423	0	0	0
T15	32180	12	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	2	0	0
T42	0	4	0	0
T54	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	364	0	0
T1	35031	11	0	0
T2	0	3	0	0
T7	0	4	0	0
T9	0	1	0	0
T12	0	13	0	0
T14	423	0	0	0
T15	32180	12	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T42	0	4	0	0
T51	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	364	0	0
T1	35031	11	0	0
T2	0	3	0	0
T7	0	4	0	0
T9	0	1	0	0
T12	0	13	0	0
T14	423	0	0	0
T15	32180	12	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T42	0	4	0	0
T51	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	15055	0	0
T1	35031	342	0	0
T2	0	19	0	0
T7	0	255	0	0
T9	0	39	0	0
T12	0	459	0	0
T14	423	0	0	0
T15	32180	507	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	106	0	0
T36	0	345	0	0
T42	0	101	0	0
T51	0	151	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	6337531	0	0
T1	35031	34548	0	0
T4	494	94	0	0
T5	435	35	0	0
T6	502	102	0	0
T14	423	23	0	0
T15	32180	31714	0	0
T16	736	336	0	0
T23	422	22	0	0
T24	650	250	0	0
T25	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6979152	308	0	0
T1	35031	11	0	0
T2	0	3	0	0
T7	0	4	0	0
T9	0	1	0	0
T12	0	13	0	0
T14	423	0	0	0
T15	32180	0	0	0
T16	736	0	0	0
T17	566	0	0	0
T18	1025	0	0	0
T19	504	0	0	0
T20	527	0	0	0
T21	402	0	0	0
T22	509	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T42	0	4	0	0
T51	0	3	0	0
T126	0	2	0	0