Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
89.02	89.02	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	89.02	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.02	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	9	53	85.48

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	9	22	70.97	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1786

1

T1

4

T3

20

T11

26

auto[1]

679

1

T1

10

T11

2

T26

13

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1806

1

T1

9

T3

20

T11

28

auto[1]

659

1

T1

5

T33

3

T91

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1894

1

T1

5

T3

20

T11

28

auto[1]

571

1

T1

9

T26

8

T45

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1875

1

T1

9

T3

11

T11

23

auto[1]

590

1

T1

5

T3

9

T11

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2280

1

T1

14

T3

20

T11

23

auto[1]

185

1

T11

5

T26

1

T45

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2257

1

T1

14

T3

20

T11

24

auto[1]

208

1

T11

4

T26

1

T45

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2248

1

T1

14

T3

20

T11

24

auto[1]

217

1

T11

4

T26

6

T72

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2203

1

T1

14

T3

20

T11

24

auto[1]

262

1

T11

4

T43

16

T237

13

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2249

1

T1

14

T3

20

T11

28

auto[1]

216

1

T26

13

T45

5

T43

8

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1827

1

T1

5

T3

9

T11

21

auto[1]

638

1

T1

9

T3

11

T11

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	9	22	70.97	9
Automatically Generated Cross Bins	31	9	22	70.97	9
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

856

1

T1

14

T3

20

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

58

1

T11

5

T200

8

T83

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

81

1

T26

8

T43

8

T71

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T237

5

T239

2

T200

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

127

1

T237

8

T238

10

T203

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T129

1

T200

1

T347

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T238

6

T82

2

T250

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T79

1

T348

4

T349

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T237

6

T350

2

T351

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T352

2

T353

4

T345

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T26

5

T72

1

T351

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

15

1

T241

8

T250

1

T219

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T354

6

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T237

10

T129

1

T351

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T238

3

T95

2

T346

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

10

1

T219

6

T343

1

T240

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T45

5

T355

4

T356

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

36

1

T43

16

T95

1

T125

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T239

2

T241

5

T357

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T26

1

T254

5

T338

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T358

8

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

10

1

T11

4

T241

4

T359

2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

119

1

T11

2

T26

5

T190

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

112

1

T3

11

T11

2

T33

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T1

5

T91

4

T43

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

72

1

T3

9

T30

1

T72

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

71

1

T43

8

T71

4

T80

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

48

1

T11

5

T26

1

T207

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T33

3

T243

1

T333

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

117

1

T45

5

T91

10

T248

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

72

1

T26

8

T125

3

T348

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T91

4

T129

1

T241

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

46

1

T43

8

T224

3

T245

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T239

4

T200

7

T95

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T108

3

T242

4

T335

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T1

4

T356

4

T346

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T335

1

T341

1

T360

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

97

1

T59

11

T76

6

T237

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

67

1

T237

8

T251

2

T245

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

89

1

T59

9

T35

5

T80

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T33

2

T59

5

T82

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

82

1

T59

5

T34

4

T224

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T207

4

T334

2

T351

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T41

1

T350

2

T352

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T91

3

T242

2

T80

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T76

2

T78

2

T238

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T1

4

T108

3

T76

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

34

1

T97

5

T98

3

T292

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T361

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

30

1

T190

3

T362

1

T355

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T1

1

T33

1

T207

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T108

2

T200

8

T332

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T242

1

T363

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded