Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T10

4

T54

9

T57

9

auto[1]

1021

1

T10

2

T54

11

T57

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

491

1

T10

1

T54

6

T57

7

from_0to1

490

1

T10

1

T54

5

T57

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T10

4

T54

10

T57

7

auto[1]

991

1

T10

2

T54

10

T57

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T10

4

T54

10

T57

10

auto[1]

1048

1

T10

2

T54

10

T57

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T10

1

T54

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T54

1

T379

2

T380

2

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T54

1

T57

1

T30

4

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T57

1

T30

3

T379

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T10

1

T30

2

T380

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T54

1

T57

2

T30

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T57

1

T379

1

T37

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T54

1

T57

1

T30

6

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T54

1

T57

2

T30

4

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T54

1

T30

5

T37

3

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T54

1

T57

1

T30

5

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T57

1

T30

3

T182

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T54

1

T30

8

T37

5

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T54

1

T30

1

T182

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T30

2

T379

1

T380

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T54

1

T57

2

T30

5

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T10

4

T54

13

T57

6

auto[1]

996

1

T10

2

T54

7

T57

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T10

1

T54

5

T57

3

from_0to1

495

1

T10

1

T54

4

T57

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

975

1

T10

3

T54

12

T57

3

auto[1]

1051

1

T10

3

T54

8

T57

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T10

4

T54

12

T57

8

auto[1]

986

1

T10

2

T54

8

T57

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T10

1

T54

1

T30

3

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T54

1

T30

6

T380

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T54

1

T30

3

T182

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T30

1

T37

1

T76

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T30

5

T379

1

T37

4

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T54

1

T30

7

T182

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T54

1

T57

1

T30

2

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T30

3

T182

1

T380

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T30

2

T379

2

T37

5

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T30

3

T37

1

T77

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T54

2

T30

1

T182

1

auto[1]

from_1to0

auto[1]

auto[1]

79

1

T57

3

T30

7

T182

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T54

1

T30

1

T182

3

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T54

1

T30

2

T37

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T57

2

T379

1

T380

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T10

1

T57

1

T30

6

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T10

5

T54

14

T57

14

auto[1]

971

1

T10

1

T54

6

T57

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

491

1

T10

2

T54

6

T57

3

from_0to1

498

1

T10

2

T54

6

T57

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T10

3

T54

12

T57

12

auto[1]

988

1

T10

3

T54

8

T57

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T10

3

T54

6

T57

8

auto[1]

1018

1

T10

3

T54

14

T57

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T10

1

T54

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T10

1

T54

2

T57

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T30

6

T37

4

T76

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T54

3

T30

3

T182

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T57

1

T30

3

T182

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T54

1

T30

5

T182

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T10

1

T57

1

T30

5

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T10

1

T57

1

T30

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T30

3

T182

1

T379

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T30

3

T37

3

T76

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T30

4

T182

1

T380

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T57

1

T30

2

T380

2

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T54

2

T30

4

T380

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T54

2

T30

4

T182

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T30

2

T380

1

T37

5

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T54

1

T30

1

T379

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984

1

T10

4

T54

10

T57

15

auto[1]

1042

1

T10

2

T54

10

T57

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

490

1

T10

1

T54

5

T57

5

from_0to1

481

1

T54

6

T57

5

T30

21

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T10

2

T54

10

T57

10

auto[1]

1020

1

T10

4

T54

10

T57

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T10

4

T54

11

T57

14

auto[1]

1047

1

T10

2

T54

9

T57

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T54

1

T30

1

T379

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T57

1

T30

3

T379

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T57

1

T30

2

T37

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T57

1

T30

2

T182

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T54

1

T57

2

T30

2

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T54

1

T30

2

T380

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T54

2

T30

3

T380

2

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T54

1

T57

2

T30

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T54

1

T57

1

T30

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T54

2

T30

5

T379

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T54

1

T30

4

T182

2

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T10

1

T57

1

T30

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T57

1

T30

2

T37

3

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T30

3

T379

1

T37

4

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T30

4

T182

1

T379

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T54

1

T30

4

T182

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

970

1

T10

4

T54

10

T57

5

auto[1]

1056

1

T10

2

T54

10

T57

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

481

1

T10

2

T54

6

T57

5

from_0to1

483

1

T10

1

T54

5

T57

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T10

5

T54

12

T57

11

auto[1]

990

1

T10

1

T54

8

T57

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T10

4

T54

8

T57

11

auto[1]

1030

1

T10

2

T54

12

T57

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T10

1

T30

3

T380

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T54

1

T30

4

T37

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T10

1

T57

1

T30

2

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T54

1

T57

1

T30

4

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T54

1

T30

6

T182

2

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T54

2

T30

2

T76

2

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T30

2

T182

1

T379

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T57

1

T30

3

T182

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T54

1

T57

2

T30

3

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T57

1

T30

4

T182

2

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T54

1

T30

3

T379

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T54

2

T30

3

T182

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T57

2

T30

5

T379

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T10

1

T57

1

T30

2

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T54

2

T30

4

T380

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T57

1

T30

3

T379

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T10

4

T54

10

T57

9

auto[1]

1010

1

T10

2

T54

10

T57

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T10

2

T54

5

T57

5

from_0to1

501

1

T10

2

T54

5

T57

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T10

6

T54

16

T57

7

auto[1]

990

1

T54

4

T57

13

T30

56

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1009

1

T10

3

T54

13

T57

12

auto[1]

1017

1

T10

3

T54

7

T57

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T10

1

T54

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T30

4

T182

1

T379

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T30

3

T379

1

T380

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T57

1

T30

4

T182

2

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T54

1

T30

2

T379

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T10

1

T54

1

T30

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T54

1

T57

4

T30

4

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T30

5

T182

1

T379

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T10

1

T54

2

T30

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T54

1

T30

5

T37

3

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T54

1

T57

3

T30

4

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T30

3

T182

1

T37

3

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T54

1

T57

1

T30

3

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T10

1

T30

4

T37

3

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T54

1

T30

3

T182

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T30

5

T380

1

T37

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T10

5

T54

12

T57

16

auto[1]

1030

1

T10

1

T54

8

T57

4

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

487

1

T10

1

T54

5

T57

4

from_0to1

480

1

T10

1

T54

5

T57

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985

1

T10

5

T54

8

T57

4

auto[1]

1041

1

T10

1

T54

12

T57

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T10

4

T54

8

T57

12

auto[1]

997

1

T10

2

T54

12

T57

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T10

1

T30

3

T182

2

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T30

2

T182

1

T379

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T54

1

T57

2

T30

4

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T54

2

T30

4

T379

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T10

1

T57

1

T30

2

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T54

2

T30

2

T37

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T57

1

T30

3

T182

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T54

1

T30

2

T182

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T54

2

T30

3

T182

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T30

4

T37

4

T76

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T57

2

T30

3

T182

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T30

3

T182

1

T379

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T54

1

T30

4

T182

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T54

1

T30

5

T379

2

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T30

6

T380

1

T37

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T57

1

T30

3

T182

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T10

4

T54

15

T57

11

auto[1]

1023

1

T10

2

T54

5

T57

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

490

1

T10

1

T54

2

T57

6

from_0to1

479

1

T10

1

T54

3

T57

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T10

3

T54

11

T57

14

auto[1]

1027

1

T10

3

T54

9

T57

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T10

4

T54

13

T57

14

auto[1]

983

1

T10

2

T54

7

T57

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T57

2

T30

2

T380

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T57

3

T30

5

T379

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T54

1

T30

2

T379

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T57

1

T30

2

T182

3

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T57

3

T30

2

T76

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T30

2

T182

2

T379

3

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T54

1

T30

2

T182

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T10

1

T30

3

T379

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T54

1

T30

4

T379

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T30

2

T380

1

T37

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T10

1

T30

2

T182

2

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T30

3

T76

2

T314

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T54

2

T30

6

T380

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T57

1

T182

2

T380

1

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T57

1

T30

5

T37

2

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T30

2

T380

2

T37

5