Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113362

1

T5

5

T1

576

T6

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132936	1			T5	8		T1	840		T6	22
values[0x0]	64090	1			T5	4		T1	154		T6	12
values[0x1]	64946	1			T5	3		T1	170		T6	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	120410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141562

1

T5

10

T1

692

T6

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1766	1			T1	6		T53	1		T11	3
valid_sources[0x01]	859	1			T1	5		T69	3		T25	3
valid_sources[0x02]	855	1			T1	5		T25	4		T10	2
valid_sources[0x03]	1816	1			T25	3		T10	2		T11	3
valid_sources[0x04]	817	1			T25	1		T51	1		T11	3
valid_sources[0x05]	992	1			T1	5		T25	1		T10	1
valid_sources[0x06]	839	1			T1	5		T25	4		T11	5
valid_sources[0x07]	779	1			T1	2		T2	2		T25	5
valid_sources[0x08]	1033	1			T1	2		T15	63		T69	3
valid_sources[0x09]	960	1			T1	15		T7	1		T51	1
valid_sources[0x0a]	1193	1			T1	2		T25	1		T11	3
valid_sources[0x0b]	857	1			T1	2		T25	1		T10	2
valid_sources[0x0c]	1193	1			T6	1		T69	1		T51	1
valid_sources[0x0d]	861	1			T1	4		T25	3		T54	2
valid_sources[0x0e]	841	1			T1	2		T69	2		T25	1
valid_sources[0x0f]	896	1			T1	3		T69	4		T25	4
valid_sources[0x10]	2084	1			T1	9		T25	2		T51	1
valid_sources[0x11]	1546	1			T1	4		T25	1		T10	2
valid_sources[0x12]	902	1			T1	6		T69	2		T10	3
valid_sources[0x13]	975	1			T1	2		T25	1		T10	2
valid_sources[0x14]	1846	1			T1	4		T25	12		T10	7
valid_sources[0x15]	892	1			T51	1		T10	2		T11	4
valid_sources[0x16]	782	1			T1	10		T25	1		T52	22
valid_sources[0x17]	970	1			T1	3		T51	2		T10	1
valid_sources[0x18]	1164	1			T1	3		T25	1		T10	2
valid_sources[0x19]	872	1			T69	1		T25	1		T10	2
valid_sources[0x1a]	816	1			T1	5		T25	8		T57	4
valid_sources[0x1b]	795	1			T1	5		T25	8		T10	1
valid_sources[0x1c]	936	1			T1	11		T25	2		T11	3
valid_sources[0x1d]	1109	1			T1	3		T25	2		T10	1
valid_sources[0x1e]	1015	1			T1	5		T11	8		T26	1
valid_sources[0x1f]	917	1			T1	6		T6	3		T69	2
valid_sources[0x20]	1074	1			T1	4		T51	1		T10	3
valid_sources[0x21]	777	1			T10	3		T11	6		T26	7
valid_sources[0x22]	909	1			T1	2		T69	5		T54	3
valid_sources[0x23]	789	1			T25	6		T51	1		T10	1
valid_sources[0x24]	883	1			T1	9		T13	2		T25	1
valid_sources[0x25]	713	1			T1	1		T6	1		T69	1
valid_sources[0x26]	788	1			T1	3		T4	1		T69	2
valid_sources[0x27]	768	1			T1	6		T25	1		T10	5
valid_sources[0x28]	902	1			T1	2		T6	1		T69	1
valid_sources[0x29]	1033	1			T1	6		T6	7		T15	3
valid_sources[0x2a]	1167	1			T1	4		T69	1		T11	5
valid_sources[0x2b]	951	1			T1	7		T6	2		T25	2
valid_sources[0x2c]	1055	1			T7	4		T25	2		T10	3
valid_sources[0x2d]	1188	1			T1	9		T25	1		T57	1
valid_sources[0x2e]	781	1			T1	8		T25	1		T10	1
valid_sources[0x2f]	912	1			T1	2		T15	4		T16	1
valid_sources[0x30]	853	1			T1	3		T7	2		T16	2
valid_sources[0x31]	793	1			T1	2		T25	4		T10	1
valid_sources[0x32]	763	1			T1	10		T25	6		T10	1
valid_sources[0x33]	807	1			T1	7		T10	4		T11	8
valid_sources[0x34]	912	1			T1	6		T16	1		T11	5
valid_sources[0x35]	829	1			T25	2		T53	1		T11	3
valid_sources[0x36]	956	1			T1	2		T9	7		T25	1
valid_sources[0x37]	1126	1			T1	9		T69	2		T10	4
valid_sources[0x38]	857	1			T1	8		T22	1		T25	1
valid_sources[0x39]	907	1			T1	1		T13	1		T25	3
valid_sources[0x3a]	1393	1			T1	18		T25	1		T11	7
valid_sources[0x3b]	775	1			T25	3		T51	1		T11	5
valid_sources[0x3c]	803	1			T9	4		T25	1		T51	1
valid_sources[0x3d]	979	1			T1	16		T69	4		T11	4
valid_sources[0x3e]	1343	1			T1	4		T10	2		T11	2
valid_sources[0x3f]	915	1			T5	15		T25	9		T10	2
valid_sources[0x40]	847	1			T1	10		T22	2		T10	2
valid_sources[0x41]	850	1			T1	6		T25	3		T10	1
valid_sources[0x42]	940	1			T1	1		T51	1		T54	4
valid_sources[0x43]	816	1			T1	1		T25	4		T10	2
valid_sources[0x44]	871	1			T1	6		T25	3		T51	1
valid_sources[0x45]	804	1			T1	6		T7	3		T25	4
valid_sources[0x46]	789	1			T10	4		T11	4		T26	1
valid_sources[0x47]	1419	1			T3	714		T25	2		T51	2
valid_sources[0x48]	851	1			T1	11		T6	13		T14	1
valid_sources[0x49]	950	1			T1	1		T7	1		T22	3
valid_sources[0x4a]	1010	1			T1	13		T15	3		T10	1
valid_sources[0x4b]	966	1			T1	3		T13	1		T25	3
valid_sources[0x4c]	1061	1			T13	1		T69	4		T54	1
valid_sources[0x4d]	877	1			T1	9		T10	2		T11	6
valid_sources[0x4e]	1640	1			T8	1		T10	3		T54	2
valid_sources[0x4f]	822	1			T1	1		T25	1		T51	1
valid_sources[0x50]	866	1			T1	7		T25	2		T10	1
valid_sources[0x51]	998	1			T1	2		T25	2		T51	1
valid_sources[0x52]	873	1			T1	7		T25	1		T10	2
valid_sources[0x53]	791	1			T1	3		T16	1		T25	5
valid_sources[0x54]	762	1			T1	3		T11	3		T26	5
valid_sources[0x55]	1022	1			T1	11		T22	1		T69	2
valid_sources[0x56]	1215	1			T1	3		T25	1		T51	1
valid_sources[0x57]	926	1			T1	11		T6	1		T53	1
valid_sources[0x58]	1274	1			T1	1		T6	1		T15	20
valid_sources[0x59]	771	1			T25	2		T10	3		T11	9
valid_sources[0x5a]	1037	1			T1	3		T25	3		T11	6
valid_sources[0x5b]	884	1			T1	4		T2	3		T69	11
valid_sources[0x5c]	758	1			T6	3		T25	4		T54	2
valid_sources[0x5d]	822	1			T69	3		T25	2		T51	1
valid_sources[0x5e]	853	1			T15	44		T25	6		T51	2
valid_sources[0x5f]	1659	1			T1	3		T16	5		T10	5
valid_sources[0x60]	860	1			T1	2		T50	1		T54	1
valid_sources[0x61]	986	1			T1	5		T8	4		T24	63
valid_sources[0x62]	719	1			T1	4		T10	1		T11	6
valid_sources[0x63]	881	1			T1	4		T9	1		T25	1
valid_sources[0x64]	912	1			T1	8		T25	2		T10	1
valid_sources[0x65]	1687	1			T1	1		T25	1		T10	1
valid_sources[0x66]	851	1			T25	5		T10	6		T11	6
valid_sources[0x67]	974	1			T1	2		T69	1		T57	2
valid_sources[0x68]	794	1			T22	1		T25	4		T10	1
valid_sources[0x69]	880	1			T1	5		T4	1		T25	1
valid_sources[0x6a]	959	1			T1	2		T4	1		T16	6
valid_sources[0x6b]	980	1			T1	8		T69	1		T25	3
valid_sources[0x6c]	958	1			T1	12		T10	2		T11	7
valid_sources[0x6d]	766	1			T1	2		T69	3		T11	5
valid_sources[0x6e]	856	1			T1	2		T13	1		T22	5
valid_sources[0x6f]	889	1			T1	7		T11	4		T26	4
valid_sources[0x70]	2476	1			T1	5		T25	3		T57	2
valid_sources[0x71]	843	1			T1	2		T25	5		T10	1
valid_sources[0x72]	1744	1			T22	1		T69	2		T51	1
valid_sources[0x73]	973	1			T1	1		T25	1		T57	7
valid_sources[0x74]	2182	1			T1	4		T69	1		T54	2
valid_sources[0x75]	1888	1			T1	1		T10	1		T54	1
valid_sources[0x76]	947	1			T1	6		T22	6		T10	3
valid_sources[0x77]	1049	1			T1	3		T15	20		T10	1
valid_sources[0x78]	959	1			T1	3		T22	1		T51	1
valid_sources[0x79]	747	1			T1	3		T13	1		T25	3
valid_sources[0x7a]	800	1			T1	23		T11	1		T26	2
valid_sources[0x7b]	754	1			T1	4		T69	2		T25	3
valid_sources[0x7c]	846	1			T1	4		T51	1		T10	2
valid_sources[0x7d]	804	1			T1	4		T69	1		T25	4
valid_sources[0x7e]	977	1			T1	6		T6	2		T10	1
valid_sources[0x7f]	1770	1			T1	9		T25	2		T54	2
valid_sources[0x80]	784	1			T1	9		T2	1		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59915

1

T5

3

T1

434

T6

10

values[0x0]

all_enables

biggest_size

31300

1

T5

2

T1

74

T6

7

values[0x1]

all_enables

biggest_size

22147

1

T1

68

T3

61

T13

3