Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T13,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T5,T13,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T13,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T16
1	0	Covered	T1,T6,T2
1	1	Covered	T5,T13,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T13,T16
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T13,T16
0	1	Covered	T5,T13,T16
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T13,T16
1	-	Covered	T5,T13,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T13,T16
DetectSt	168	Covered	T5,T13,T16
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T5,T13,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T13,T16
DebounceSt->IdleSt	163	Covered	T23,T20,T38
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5,T13,T16
IdleSt->DebounceSt	148	Covered	T5,T13,T16
StableSt->IdleSt	206	Covered	T5,T13,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T13,T16
0	1	Covered	T5,T13,T16
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T16
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T13,T16
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T13,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T38,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T13,T16
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T5,T13,T16
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T13,T16
StableSt	-	-	-	-	-	-	0	Covered	T5,T13,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	279	0	0
CntIncr_A	9484281	115520	0	0
CntNoWrap_A	9484281	8838539	0	0
DetectStDropOut_A	9484281	0	0	0
DetectedOut_A	9484281	807	0	0
DetectedPulseOut_A	9484281	125	0	0
DisabledIdleSt_A	9484281	8716892	0	0
DisabledNoDetection_A	9484281	8719135	0	0
EnterDebounceSt_A	9484281	155	0	0
EnterDetectSt_A	9484281	125	0	0
EnterStableSt_A	9484281	125	0	0
PulseIsPulse_A	9484281	125	0	0
StayInStableSt	9484281	682	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	6822	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	125	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	279	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	6	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	2	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	4	0	0
T20	0	1	0	0
T23	0	5	0	0
T36	0	4	0	0
T37	0	14	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	115520	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	205	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	45	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	59635	0	0
T20	0	40	0	0
T23	0	236	0	0
T36	0	107	0	0
T37	0	524	0	0
T46	0	53	0	0
T47	0	52	0	0
T48	0	169	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838539	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	351	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	302	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	807	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	28	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	7	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	16	0	0
T23	0	4	0	0
T36	0	5	0	0
T37	0	38	0	0
T46	0	4	0	0
T47	0	9	0	0
T48	0	23	0	0
T109	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	125	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	1	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	2	0	0
T23	0	2	0	0
T36	0	2	0	0
T37	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8716892	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	4	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	224	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8719135	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	4	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	224	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	155	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	1	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	2	0	0
T20	0	1	0	0
T23	0	3	0	0
T36	0	2	0	0
T37	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	125	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	1	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	2	0	0
T23	0	2	0	0
T36	0	2	0	0
T37	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	125	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	1	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	2	0	0
T23	0	2	0	0
T36	0	2	0	0
T37	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	125	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	1	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	2	0	0
T23	0	2	0	0
T36	0	2	0	0
T37	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	682	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	25	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	6	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	14	0	0
T23	0	2	0	0
T36	0	3	0	0
T37	0	31	0	0
T46	0	3	0	0
T47	0	8	0	0
T48	0	21	0	0
T109	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6822	0	0
T1	42319	28	0	0
T2	692	2	0	0
T3	39847	14	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	7	0	0
T7	480	0	0	0
T8	0	1	0	0
T13	705	3	0	0
T14	714	0	0	0
T15	3975	11	0	0
T16	0	3	0	0
T22	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	125	0	0
T1	42319	0	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	1	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	0	2	0	0
T23	0	2	0	0
T36	0	2	0	0
T37	0	7	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T10,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T32,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T20,T21
1	0	Covered	T5,T1,T6
1	1	Covered	T10,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T32,T63
0	1	Covered	T85,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T32,T63
0	1	Unreachable
1	0	Covered	T10,T32,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T20,T21
DetectSt	168	Covered	T10,T32,T63
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T32,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T32,T63
DebounceSt->IdleSt	163	Covered	T20,T21,T76
DetectSt->IdleSt	186	Covered	T85,T89,T90
DetectSt->StableSt	191	Covered	T10,T32,T63
IdleSt->DebounceSt	148	Covered	T10,T20,T21
StableSt->IdleSt	206	Covered	T10,T32,T63

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T20,T21
0	1	Covered	T10,T20,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T32,T63
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T32,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T76,T113
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T85,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T10,T32,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T32,T63
StableSt	-	-	-	-	-	-	0	Covered	T10,T32,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	122	0	0
CntIncr_A	9484281	187353	0	0
CntNoWrap_A	9484281	8838696	0	0
DetectStDropOut_A	9484281	6	0	0
DetectedOut_A	9484281	9707	0	0
DetectedPulseOut_A	9484281	40	0	0
DisabledIdleSt_A	9484281	7997441	0	0
DisabledNoDetection_A	9484281	7999730	0	0
EnterDebounceSt_A	9484281	78	0	0
EnterDetectSt_A	9484281	46	0	0
EnterStableSt_A	9484281	40	0	0
PulseIsPulse_A	9484281	40	0	0
StayInStableSt	9484281	9667	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	6822	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_sticky_sva.StableStDropOut_A	9484281	86040	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	122	0	0
T10	5401	2	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	1	0	0
T21	0	4	0	0
T32	0	6	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	2	0	0
T64	443	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	6	0	0
T77	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	187353	0	0
T10	5401	63	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	22	0	0
T21	0	212	0	0
T32	0	240	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	90	0	0
T64	443	0	0	0
T74	0	17	0	0
T75	0	27	0	0
T76	0	333	0	0
T77	0	95	0	0
T78	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838696	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6	0	0
T85	183755	2	0	0
T89	0	1	0	0
T90	0	2	0	0
T116	0	1	0	0
T117	494	0	0	0
T118	492	0	0	0
T119	5566	0	0	0
T120	1673	0	0	0
T121	523	0	0	0
T122	524	0	0	0
T123	5468	0	0	0
T124	4256	0	0	0
T125	14929	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	9707	0	0
T10	5401	276	0	0
T11	26257	0	0	0
T12	952	0	0	0
T32	0	954	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	497	0	0
T64	443	0	0	0
T74	0	4	0	0
T75	0	8	0	0
T76	0	270	0	0
T77	0	514	0	0
T78	0	33	0	0
T84	0	231	0	0
T112	0	621	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	40	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T84	0	1	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	7997441	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	7999730	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	78	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	2	0	0
T21	0	4	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T77	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	46	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T84	0	1	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	40	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T84	0	1	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	40	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T84	0	1	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	9667	0	0
T10	5401	275	0	0
T11	26257	0	0	0
T12	952	0	0	0
T32	0	951	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	496	0	0
T64	443	0	0	0
T74	0	3	0	0
T75	0	7	0	0
T76	0	269	0	0
T77	0	513	0	0
T78	0	32	0	0
T84	0	230	0	0
T112	0	620	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6822	0	0
T1	42319	28	0	0
T2	692	2	0	0
T3	39847	14	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	7	0	0
T7	480	0	0	0
T8	0	1	0	0
T13	705	3	0	0
T14	714	0	0	0
T15	3975	11	0	0
T16	0	3	0	0
T22	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	86040	0	0
T10	5401	142	0	0
T11	26257	0	0	0
T12	952	0	0	0
T32	0	205	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	414	0	0
T64	443	0	0	0
T74	0	55	0	0
T75	0	18797	0	0
T76	0	225	0	0
T77	0	105	0	0
T78	0	143	0	0
T84	0	127	0	0
T112	0	94	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T10,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T21,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T20,T21
1	0	Covered	T1,T6,T2
1	1	Covered	T10,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T21,T32
0	1	Covered	T84,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T21,T32
0	1	Unreachable
1	0	Covered	T10,T21,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T20,T21
DetectSt	168	Covered	T10,T21,T32
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T21,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T21,T32
DebounceSt->IdleSt	163	Covered	T20,T63,T76
DetectSt->IdleSt	186	Covered	T84,T87,T88
DetectSt->StableSt	191	Covered	T10,T21,T32
IdleSt->DebounceSt	148	Covered	T10,T20,T21
StableSt->IdleSt	206	Covered	T10,T21,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T20,T21
0	1	Covered	T10,T20,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T21,T32
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T21,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T76,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T84,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T10,T21,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T21,T32
StableSt	-	-	-	-	-	-	0	Covered	T10,T21,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	133	0	0
CntIncr_A	9484281	368819	0	0
CntNoWrap_A	9484281	8838685	0	0
DetectStDropOut_A	9484281	5	0	0
DetectedOut_A	9484281	19423	0	0
DetectedPulseOut_A	9484281	46	0	0
DisabledIdleSt_A	9484281	7997441	0	0
DisabledNoDetection_A	9484281	7999730	0	0
EnterDebounceSt_A	9484281	84	0	0
EnterDetectSt_A	9484281	51	0	0
EnterStableSt_A	9484281	46	0	0
PulseIsPulse_A	9484281	46	0	0
StayInStableSt	9484281	19377	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_sticky_sva.StableStDropOut_A	9484281	449966	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	133	0	0
T10	5401	2	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T32	0	6	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	4	0	0
T64	443	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	8	0	0
T77	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	368819	0	0
T10	5401	43	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	21	0	0
T21	0	51	0	0
T32	0	102	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	360	0	0
T64	443	0	0	0
T74	0	27	0	0
T75	0	18357	0	0
T76	0	380	0	0
T77	0	43	0	0
T78	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838685	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	5	0	0
T84	16070	1	0	0
T87	0	2	0	0
T88	0	1	0	0
T113	553	0	0	0
T114	16428	0	0	0
T126	0	1	0	0
T127	494	0	0	0
T128	451	0	0	0
T129	13671	0	0	0
T130	522	0	0	0
T131	444	0	0	0
T132	406	0	0	0
T133	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	19423	0	0
T10	5401	179	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	357	0	0
T32	0	389	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T74	0	6	0	0
T75	0	453	0	0
T77	0	323	0	0
T78	0	105	0	0
T84	0	156	0	0
T112	0	574	0	0
T113	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	46	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	1	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T84	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	7997441	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	7999730	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	84	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	4	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	8	0	0
T77	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	51	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	1	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T84	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	46	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	1	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T84	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	46	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	1	0	0
T32	0	3	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T84	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	19377	0	0
T10	5401	178	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	356	0	0
T32	0	386	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T74	0	5	0	0
T75	0	452	0	0
T77	0	322	0	0
T78	0	104	0	0
T84	0	155	0	0
T112	0	573	0	0
T113	0	29	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	449966	0	0
T10	5401	249	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	132	0	0
T32	0	922	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T74	0	39	0	0
T75	0	25	0	0
T77	0	353	0	0
T78	0	67	0	0
T84	0	64	0	0
T112	0	141	0	0
T113	0	48	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T10,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T21,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T20,T21
1	0	Covered	T1,T6,T2
1	1	Covered	T10,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T21,T32
0	1	Covered	T32,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T21,T32
0	1	Unreachable
1	0	Covered	T10,T21,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T20,T21
DetectSt	168	Covered	T10,T21,T32
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T21,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T21,T32
DebounceSt->IdleSt	163	Covered	T20,T32,T74
DetectSt->IdleSt	186	Covered	T32,T84,T85
DetectSt->StableSt	191	Covered	T10,T21,T32
IdleSt->DebounceSt	148	Covered	T10,T20,T21
StableSt->IdleSt	206	Covered	T10,T21,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T20,T21
0	1	Covered	T10,T20,T21
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T21,T32
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T21,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T74,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T32,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T10,T21,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T21,T32
StableSt	-	-	-	-	-	-	0	Covered	T10,T21,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	137	0	0
CntIncr_A	9484281	110922	0	0
CntNoWrap_A	9484281	8838681	0	0
DetectStDropOut_A	9484281	9	0	0
DetectedOut_A	9484281	161132	0	0
DetectedPulseOut_A	9484281	34	0	0
DisabledIdleSt_A	9484281	7997441	0	0
DisabledNoDetection_A	9484281	7999730	0	0
EnterDebounceSt_A	9484281	96	0	0
EnterDetectSt_A	9484281	43	0	0
EnterStableSt_A	9484281	34	0	0
PulseIsPulse_A	9484281	34	0	0
StayInStableSt	9484281	161098	0	0
gen_high_event_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_sticky_sva.StableStDropOut_A	9484281	159730	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	137	0	0
T10	5401	2	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T32	0	14	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	2	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	6	0	0
T77	0	2	0	0
T112	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	110922	0	0
T10	5401	50	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	21	0	0
T21	0	52	0	0
T32	0	504	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	89	0	0
T64	443	0	0	0
T74	0	47	0	0
T75	0	53	0	0
T76	0	455	0	0
T77	0	45	0	0
T112	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838681	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	9	0	0
T32	1950	4	0	0
T34	6386	0	0	0
T43	36647	0	0	0
T63	1443	0	0	0
T71	16125	0	0	0
T84	0	3	0	0
T85	0	1	0	0
T108	11862	0	0	0
T134	0	1	0	0
T135	524	0	0	0
T136	640	0	0	0
T137	426	0	0	0
T138	2359	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	161132	0	0
T10	5401	376	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	257	0	0
T32	0	1	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	423	0	0
T64	443	0	0	0
T75	0	15	0	0
T76	0	223	0	0
T77	0	372	0	0
T112	0	255	0	0
T113	0	3	0	0
T114	0	66	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	34	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	1	0	0
T32	0	1	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	7997441	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	7999730	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	96	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T32	0	9	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T77	0	1	0	0
T112	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	43	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	1	0	0
T32	0	5	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T84	0	3	0	0
T112	0	1	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	34	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	1	0	0
T32	0	1	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	34	0	0
T10	5401	1	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	1	0	0
T32	0	1	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	1	0	0
T64	443	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	161098	0	0
T10	5401	375	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	256	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	422	0	0
T64	443	0	0	0
T75	0	14	0	0
T76	0	222	0	0
T77	0	371	0	0
T112	0	254	0	0
T113	0	2	0	0
T114	0	65	0	0
T139	0	99	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	159730	0	0
T10	5401	58	0	0
T11	26257	0	0	0
T12	952	0	0	0
T21	0	233	0	0
T32	0	110	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T63	0	494	0	0
T64	443	0	0	0
T75	0	18773	0	0
T76	0	285	0	0
T77	0	306	0	0
T112	0	497	0	0
T113	0	27	0	0
T114	0	587	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T30,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T8,T30,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T30,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T30,T42
1	0	Covered	T5,T1,T6
1	1	Covered	T8,T30,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T42
0	1	Covered	T8,T39,T140
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T30,T42
1	-	Covered	T8,T39,T140

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T30,T42
DetectSt	168	Covered	T8,T30,T42
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T8,T30,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T30,T42
DebounceSt->IdleSt	163	Covered	T36
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T30,T42
IdleSt->DebounceSt	148	Covered	T8,T30,T42
StableSt->IdleSt	206	Covered	T8,T30,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T30,T42
0	1	Covered	T8,T30,T42
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T30,T42
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T30,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T30,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T36
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T30,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T30,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T20,T39
StableSt	-	-	-	-	-	-	0	Covered	T8,T30,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	89	0	0
CntIncr_A	9484281	231801	0	0
CntNoWrap_A	9484281	8838729	0	0
DetectStDropOut_A	9484281	0	0	0
DetectedOut_A	9484281	2993	0	0
DetectedPulseOut_A	9484281	44	0	0
DisabledIdleSt_A	9484281	8157252	0	0
DisabledNoDetection_A	9484281	8159488	0	0
EnterDebounceSt_A	9484281	45	0	0
EnterDetectSt_A	9484281	44	0	0
EnterStableSt_A	9484281	44	0	0
PulseIsPulse_A	9484281	44	0	0
StayInStableSt	9484281	2923	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	89	0	0
T8	687	2	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	2	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T42	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	2	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	231801	0	0
T8	687	39	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	22	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	69	0	0
T36	0	17	0	0
T37	0	66	0	0
T39	0	76880	0	0
T40	0	34	0	0
T42	0	100	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	90	0	0
T140	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838729	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	2993	0	0
T8	687	20	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	23	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	41	0	0
T37	0	42	0	0
T39	0	84	0	0
T40	0	38	0	0
T42	0	147	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	43	0	0
T75	0	39	0	0
T140	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	44	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8157252	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8159488	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	45	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	1	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	44	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	44	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	44	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	2923	0	0
T8	687	19	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	22	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	39	0	0
T37	0	40	0	0
T39	0	81	0	0
T40	0	36	0	0
T42	0	145	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	41	0	0
T75	0	37	0	0
T140	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	16	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T39	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T77	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T9,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T9,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T23
1	0	Covered	T1,T6,T3
1	1	Covered	T2,T9,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T23
0	1	Covered	T146,T147,T148
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T23
0	1	Covered	T23,T36,T74
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T23
1	-	Covered	T23,T36,T74

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T23
DetectSt	168	Covered	T2,T9,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T9,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T23
DebounceSt->IdleSt	163	Covered	T75,T149,T150
DetectSt->IdleSt	186	Covered	T146,T147,T148
DetectSt->StableSt	191	Covered	T2,T9,T23
IdleSt->DebounceSt	148	Covered	T2,T9,T23
StableSt->IdleSt	206	Covered	T23,T20,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T23
0	1	Covered	T2,T9,T23
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T149,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T23
DetectSt	-	-	-	-	1	-	-	Covered	T146,T147,T148
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T20,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	100	0	0
CntIncr_A	9484281	359599	0	0
CntNoWrap_A	9484281	8838718	0	0
DetectStDropOut_A	9484281	3	0	0
DetectedOut_A	9484281	136468	0	0
DetectedPulseOut_A	9484281	45	0	0
DisabledIdleSt_A	9484281	8072398	0	0
DisabledNoDetection_A	9484281	8074646	0	0
EnterDebounceSt_A	9484281	52	0	0
EnterDetectSt_A	9484281	48	0	0
EnterStableSt_A	9484281	45	0	0
PulseIsPulse_A	9484281	45	0	0
StayInStableSt	9484281	136400	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	2632	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	100	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	2	0	0
T22	494	0	0	0
T23	0	4	0	0
T36	0	2	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	6	0	0
T151	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	359599	0	0
T2	692	37	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	49	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T23	0	52	0	0
T36	0	10	0	0
T74	0	90	0	0
T75	0	75	0	0
T77	0	124	0	0
T151	0	85	0	0
T152	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838718	0	0
T1	42319	39839	0	0
T2	692	289	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	3	0	0
T146	19607	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T153	18961	0	0	0
T154	570	0	0	0
T155	422	0	0	0
T156	670	0	0	0
T157	618	0	0	0
T158	407	0	0	0
T159	422	0	0	0
T160	11966	0	0	0
T161	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	136468	0	0
T2	692	117	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	41	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	23	0	0
T22	494	0	0	0
T23	0	200	0	0
T36	0	7	0	0
T74	0	72	0	0
T77	0	180	0	0
T78	0	12	0	0
T151	0	48	0	0
T152	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	45	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	2	0	0
T36	0	1	0	0
T74	0	1	0	0
T77	0	3	0	0
T78	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8072398	0	0
T1	42319	39839	0	0
T2	692	3	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8074646	0	0
T1	42319	39857	0	0
T2	692	3	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	52	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	2	0	0
T36	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	3	0	0
T151	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	48	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	2	0	0
T36	0	1	0	0
T74	0	1	0	0
T77	0	3	0	0
T78	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	45	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	2	0	0
T36	0	1	0	0
T74	0	1	0	0
T77	0	3	0	0
T78	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	45	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	2	0	0
T36	0	1	0	0
T74	0	1	0	0
T77	0	3	0	0
T78	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	136400	0	0
T2	692	115	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T9	0	39	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T23	0	197	0	0
T36	0	6	0	0
T74	0	71	0	0
T77	0	175	0	0
T78	0	11	0	0
T151	0	46	0	0
T152	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	2632	0	0
T1	42319	8	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	1	0	0
T6	497	6	0	0
T7	480	0	0	0
T8	0	2	0	0
T9	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	9	0	0
T16	60186	0	0	0
T22	0	5	0	0
T24	0	6	0	0
T69	0	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	20	0	0
T23	3352	1	0	0
T30	20069	0	0	0
T31	2267	0	0	0
T33	26142	0	0	0
T36	0	1	0	0
T42	1237	0	0	0
T46	683	0	0	0
T47	749	0	0	0
T65	489	0	0	0
T66	495	0	0	0
T74	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T81	0	2	0	0
T149	0	1	0	0
T152	0	1	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	424	0	0	0