Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T12,T23,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T12,T23,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T12,T23,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T30
1	0	Covered	T5,T1,T6
1	1	Covered	T12,T23,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T30
0	1	Covered	T30,T42,T37
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T23,T30
1	-	Covered	T30,T42,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T23,T30
DetectSt	168	Covered	T12,T23,T30
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T12,T23,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T23,T30
DebounceSt->IdleSt	163	Covered	T146
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T23,T30
IdleSt->DebounceSt	148	Covered	T12,T23,T30
StableSt->IdleSt	206	Covered	T23,T30,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T23,T30
0	1	Covered	T12,T23,T30
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T23,T30
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T23,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T23,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T146
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T23,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T23,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T42,T20
StableSt	-	-	-	-	-	-	0	Covered	T12,T23,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	105	0	0
CntIncr_A	9484281	67271	0	0
CntNoWrap_A	9484281	8838713	0	0
DetectStDropOut_A	9484281	0	0	0
DetectedOut_A	9484281	74221	0	0
DetectedPulseOut_A	9484281	52	0	0
DisabledIdleSt_A	9484281	8404185	0	0
DisabledNoDetection_A	9484281	8406419	0	0
EnterDebounceSt_A	9484281	53	0	0
EnterDetectSt_A	9484281	52	0	0
EnterStableSt_A	9484281	52	0	0
PulseIsPulse_A	9484281	52	0	0
StayInStableSt	9484281	74142	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	105	0	0
T12	952	2	0	0
T20	0	2	0	0
T23	3352	2	0	0
T26	14102	0	0	0
T30	0	4	0	0
T36	0	4	0	0
T37	0	4	0	0
T40	0	2	0	0
T42	0	4	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	2	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	2	0	0
T165	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	67271	0	0
T12	952	62	0	0
T20	0	22	0	0
T23	3352	26	0	0
T26	14102	0	0	0
T30	0	138	0	0
T36	0	27	0	0
T37	0	132	0	0
T40	0	34	0	0
T42	0	200	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	40	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	17	0	0
T165	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838713	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	74221	0	0
T12	952	386	0	0
T20	0	24	0	0
T23	3352	41	0	0
T26	14102	0	0	0
T30	0	84	0	0
T36	0	143	0	0
T37	0	195	0	0
T40	0	39	0	0
T42	0	300	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	42	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	39	0	0
T165	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	52	0	0
T12	952	1	0	0
T20	0	1	0	0
T23	3352	1	0	0
T26	14102	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	1	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	1	0	0
T165	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8404185	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8406419	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	53	0	0
T12	952	1	0	0
T20	0	1	0	0
T23	3352	1	0	0
T26	14102	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	1	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	1	0	0
T165	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	52	0	0
T12	952	1	0	0
T20	0	1	0	0
T23	3352	1	0	0
T26	14102	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	1	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	1	0	0
T165	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	52	0	0
T12	952	1	0	0
T20	0	1	0	0
T23	3352	1	0	0
T26	14102	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	1	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	1	0	0
T165	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	52	0	0
T12	952	1	0	0
T20	0	1	0	0
T23	3352	1	0	0
T26	14102	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	1	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	1	0	0
T165	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	74142	0	0
T12	952	384	0	0
T20	0	23	0	0
T23	3352	39	0	0
T26	14102	0	0	0
T30	0	81	0	0
T36	0	139	0	0
T37	0	192	0	0
T40	0	37	0	0
T42	0	297	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T86	0	41	0	0
T110	425	0	0	0
T111	401	0	0	0
T140	0	37	0	0
T165	522	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	23	0	0
T20	8226	0	0	0
T30	20069	1	0	0
T31	2267	0	0	0
T33	26142	0	0	0
T37	0	1	0	0
T42	1237	1	0	0
T46	683	0	0	0
T47	749	0	0	0
T65	489	0	0	0
T66	495	0	0	0
T77	0	1	0	0
T81	0	1	0	0
T86	0	1	0	0
T143	0	1	0	0
T163	0	1	0	0
T164	424	0	0	0
T166	0	1	0	0
T167	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T12,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T12,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T12,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T23
1	0	Covered	T1,T6,T3
1	1	Covered	T2,T12,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T23
0	1	Covered	T77,T149,T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T23
0	1	Covered	T2,T12,T23
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T12,T23
1	-	Covered	T2,T12,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T23
DetectSt	168	Covered	T2,T12,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T12,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T23
DebounceSt->IdleSt	163	Covered	T142,T143,T169
DetectSt->IdleSt	186	Covered	T77,T149,T168
DetectSt->StableSt	191	Covered	T2,T12,T23
IdleSt->DebounceSt	148	Covered	T2,T12,T23
StableSt->IdleSt	206	Covered	T2,T12,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T12,T23
0	1	Covered	T2,T12,T23
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T142,T143,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T23
DetectSt	-	-	-	-	1	-	-	Covered	T77,T149,T168
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T23
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	147	0	0
CntIncr_A	9484281	189373	0	0
CntNoWrap_A	9484281	8838671	0	0
DetectStDropOut_A	9484281	5	0	0
DetectedOut_A	9484281	114736	0	0
DetectedPulseOut_A	9484281	66	0	0
DisabledIdleSt_A	9484281	8243662	0	0
DisabledNoDetection_A	9484281	8245896	0	0
EnterDebounceSt_A	9484281	77	0	0
EnterDetectSt_A	9484281	71	0	0
EnterStableSt_A	9484281	66	0	0
PulseIsPulse_A	9484281	66	0	0
StayInStableSt	9484281	114637	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	3013	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	147	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	2	0	0
T22	494	0	0	0
T23	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T107	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	189373	0	0
T2	692	37	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	62	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T23	0	26	0	0
T36	0	10	0	0
T37	0	106	0	0
T39	0	38440	0	0
T41	0	16	0	0
T42	0	200	0	0
T107	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838671	0	0
T1	42319	39839	0	0
T2	692	289	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	5	0	0
T73	4967	0	0	0
T77	12954	1	0	0
T115	3079	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	525	0	0	0
T172	506	0	0	0
T173	2965	0	0	0
T174	528	0	0	0
T175	502	0	0	0
T176	434	0	0	0
T177	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	114736	0	0
T2	692	90	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	32	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T23	0	143	0	0
T36	0	124	0	0
T37	0	274	0	0
T39	0	45975	0	0
T41	0	58	0	0
T42	0	125	0	0
T107	0	128	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	66	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8243662	0	0
T1	42319	39839	0	0
T2	692	3	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8245896	0	0
T1	42319	39857	0	0
T2	692	3	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	77	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	71	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	66	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	66	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	114637	0	0
T2	692	89	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	31	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	21	0	0
T22	494	0	0	0
T23	0	142	0	0
T36	0	123	0	0
T37	0	271	0	0
T39	0	45973	0	0
T41	0	56	0	0
T42	0	123	0	0
T107	0	126	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	3013	0	0
T1	42319	7	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	3	0	0
T7	480	0	0	0
T8	0	2	0	0
T9	0	1	0	0
T13	705	0	0	0
T14	714	4	0	0
T15	3975	11	0	0
T16	60186	0	0	0
T22	0	5	0	0
T24	0	4	0	0
T69	0	16	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	31	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T22	494	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	0	2	0	0
T77	0	1	0	0
T86	0	1	0	0
T151	0	1	0	0
T178	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T23,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T23,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T23,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T23
1	0	Covered	T1,T6,T3
1	1	Covered	T2,T23,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T23,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T23,T30
0	1	Covered	T23,T30,T42
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T23,T30
1	-	Covered	T23,T30,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T23,T30
DetectSt	168	Covered	T2,T23,T30
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T23,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T23,T30
DebounceSt->IdleSt	163	Covered	T40,T179,T169
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T23,T30
IdleSt->DebounceSt	148	Covered	T2,T23,T30
StableSt->IdleSt	206	Covered	T23,T30,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T23,T30
0	1	Covered	T2,T23,T30
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T23,T30
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T23,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T23,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T179,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T23,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T23,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T30,T42
StableSt	-	-	-	-	-	-	0	Covered	T2,T23,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	128	0	0
CntIncr_A	9484281	120363	0	0
CntNoWrap_A	9484281	8838690	0	0
DetectStDropOut_A	9484281	0	0	0
DetectedOut_A	9484281	67317	0	0
DetectedPulseOut_A	9484281	61	0	0
DisabledIdleSt_A	9484281	8518979	0	0
DisabledNoDetection_A	9484281	8521214	0	0
EnterDebounceSt_A	9484281	67	0	0
EnterDetectSt_A	9484281	61	0	0
EnterStableSt_A	9484281	61	0	0
PulseIsPulse_A	9484281	61	0	0
StayInStableSt	9484281	67233	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	128	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	2	0	0
T22	494	0	0	0
T23	0	2	0	0
T30	0	4	0	0
T37	0	8	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	4	0	0
T140	0	4	0	0
T152	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	120363	0	0
T2	692	37	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T23	0	26	0	0
T30	0	138	0	0
T37	0	238	0	0
T40	0	34	0	0
T41	0	16	0	0
T42	0	200	0	0
T140	0	34	0	0
T152	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838690	0	0
T1	42319	39839	0	0
T2	692	289	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	67317	0	0
T2	692	198	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T23	0	90	0	0
T30	0	128	0	0
T37	0	408	0	0
T41	0	1	0	0
T42	0	369	0	0
T140	0	62	0	0
T152	0	86	0	0
T180	0	136	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	61	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T37	0	4	0	0
T41	0	1	0	0
T42	0	2	0	0
T140	0	2	0	0
T152	0	3	0	0
T180	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8518979	0	0
T1	42319	39839	0	0
T2	692	3	0	0
T3	39847	39343	0	0
T4	662	3	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8521214	0	0
T1	42319	39857	0	0
T2	692	3	0	0
T3	39847	39359	0	0
T4	662	3	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	67	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T37	0	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T140	0	2	0	0
T152	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	61	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T37	0	4	0	0
T41	0	1	0	0
T42	0	2	0	0
T140	0	2	0	0
T152	0	3	0	0
T180	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	61	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T37	0	4	0	0
T41	0	1	0	0
T42	0	2	0	0
T140	0	2	0	0
T152	0	3	0	0
T180	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	61	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T37	0	4	0	0
T41	0	1	0	0
T42	0	2	0	0
T140	0	2	0	0
T152	0	3	0	0
T180	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	67233	0	0
T2	692	196	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	21	0	0
T22	494	0	0	0
T23	0	89	0	0
T30	0	126	0	0
T37	0	402	0	0
T42	0	367	0	0
T140	0	59	0	0
T152	0	82	0	0
T178	0	163	0	0
T180	0	134	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	36	0	0
T23	3352	1	0	0
T30	20069	2	0	0
T31	2267	0	0	0
T33	26142	0	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	1237	2	0	0
T46	683	0	0	0
T47	749	0	0	0
T65	489	0	0	0
T66	495	0	0	0
T80	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T152	0	2	0	0
T164	424	0	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T20,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T20,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T20,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T20
1	0	Covered	T1,T6,T3
1	1	Covered	T20,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T39,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T39,T40
0	1	Covered	T77,T152,T181
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T39,T40
1	-	Covered	T77,T152,T181

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T39,T40
DetectSt	168	Covered	T20,T39,T40
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T20,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T39,T40
DebounceSt->IdleSt	163	Covered	T152,T81
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T20,T39,T40
IdleSt->DebounceSt	148	Covered	T20,T39,T40
StableSt->IdleSt	206	Covered	T20,T39,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T39,T40
0	1	Covered	T20,T39,T40
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T39,T40
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T152,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T39,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T20,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T77,T152
StableSt	-	-	-	-	-	-	0	Covered	T20,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	86	0	0
CntIncr_A	9484281	176312	0	0
CntNoWrap_A	9484281	8838732	0	0
DetectStDropOut_A	9484281	0	0	0
DetectedOut_A	9484281	53824	0	0
DetectedPulseOut_A	9484281	42	0	0
DisabledIdleSt_A	9484281	8161613	0	0
DisabledNoDetection_A	9484281	8163850	0	0
EnterDebounceSt_A	9484281	44	0	0
EnterDetectSt_A	9484281	42	0	0
EnterStableSt_A	9484281	42	0	0
PulseIsPulse_A	9484281	42	0	0
StayInStableSt	9484281	53757	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	6528	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	86	0	0
T20	8226	2	0	0
T36	8263	0	0	0
T39	133295	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	2	0	0
T77	0	4	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	2	0	0
T151	0	2	0	0
T152	0	3	0	0
T181	0	2	0	0
T182	501	0	0	0
T183	420	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	176312	0	0
T20	8226	22	0	0
T36	8263	0	0	0
T39	133295	38440	0	0
T40	0	34	0	0
T41	0	16	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	90	0	0
T77	0	89	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	16	0	0
T151	0	85	0	0
T152	0	60	0	0
T181	0	37	0	0
T182	501	0	0	0
T183	420	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838732	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	53824	0	0
T20	8226	23	0	0
T36	8263	0	0	0
T39	133295	45974	0	0
T40	0	38	0	0
T41	0	41	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	205	0	0
T77	0	22	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	42	0	0
T151	0	48	0	0
T152	0	95	0	0
T181	0	92	0	0
T182	501	0	0	0
T183	420	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	42	0	0
T20	8226	1	0	0
T36	8263	0	0	0
T39	133295	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	1	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T181	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8161613	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	3	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8163850	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	3	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	44	0	0
T20	8226	1	0	0
T36	8263	0	0	0
T39	133295	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	1	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T181	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	42	0	0
T20	8226	1	0	0
T36	8263	0	0	0
T39	133295	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	1	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T181	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	42	0	0
T20	8226	1	0	0
T36	8263	0	0	0
T39	133295	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	1	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T181	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	42	0	0
T20	8226	1	0	0
T36	8263	0	0	0
T39	133295	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	1	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T181	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	53757	0	0
T20	8226	22	0	0
T36	8263	0	0	0
T39	133295	45972	0	0
T40	0	36	0	0
T41	0	39	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T74	0	203	0	0
T77	0	19	0	0
T104	526	0	0	0
T105	403	0	0	0
T141	0	40	0	0
T151	0	46	0	0
T152	0	94	0	0
T181	0	91	0	0
T182	501	0	0	0
T183	420	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6528	0	0
T1	42319	33	0	0
T2	692	0	0	0
T3	39847	11	0	0
T4	662	0	0	0
T6	497	8	0	0
T7	480	0	0	0
T9	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	13	0	0
T16	60186	0	0	0
T22	0	7	0	0
T24	0	3	0	0
T25	0	24	0	0
T51	0	5	0	0
T69	0	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	15	0	0
T73	4967	0	0	0
T77	12954	1	0	0
T115	3079	0	0	0
T150	0	1	0	0
T152	0	1	0	0
T167	0	2	0	0
T169	0	1	0	0
T171	525	0	0	0
T172	506	0	0	0
T173	2965	0	0	0
T174	528	0	0	0
T175	502	0	0	0
T176	434	0	0	0
T177	402	0	0	0
T181	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T6,T2
1	1	Covered	T4,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T9
0	1	Covered	T86,T75,T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T9
0	1	Covered	T4,T8,T23
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T8,T9
1	-	Covered	T4,T8,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T9
DetectSt	168	Covered	T4,T8,T9
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T9
DebounceSt->IdleSt	163	Covered	T30,T36,T142
DetectSt->IdleSt	186	Covered	T86,T75,T185
DetectSt->StableSt	191	Covered	T4,T8,T9
IdleSt->DebounceSt	148	Covered	T4,T8,T9
StableSt->IdleSt	206	Covered	T4,T8,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T9
0	1	Covered	T4,T8,T9
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T9
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T142,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T86,T75,T185
DetectSt	-	-	-	-	0	1	-	Covered	T4,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T8,T23
StableSt	-	-	-	-	-	-	0	Covered	T4,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	133	0	0
CntIncr_A	9484281	295957	0	0
CntNoWrap_A	9484281	8838685	0	0
DetectStDropOut_A	9484281	3	0	0
DetectedOut_A	9484281	117713	0	0
DetectedPulseOut_A	9484281	61	0	0
DisabledIdleSt_A	9484281	8093719	0	0
DisabledNoDetection_A	9484281	8095949	0	0
EnterDebounceSt_A	9484281	70	0	0
EnterDetectSt_A	9484281	64	0	0
EnterStableSt_A	9484281	61	0	0
PulseIsPulse_A	9484281	61	0	0
StayInStableSt	9484281	117614	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	133	0	0
T4	662	2	0	0
T8	687	4	0	0
T9	500	2	0	0
T16	60186	0	0	0
T20	0	2	0	0
T22	494	0	0	0
T23	0	2	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	295957	0	0
T4	662	91	0	0
T8	687	78	0	0
T9	500	49	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T23	0	26	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	3413	0	0
T36	0	17	0	0
T37	0	106	0	0
T39	0	38440	0	0
T40	0	34	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838685	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	259	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	3	0	0
T74	2635	0	0	0
T75	22377	1	0	0
T86	656	1	0	0
T109	719	0	0	0
T140	2684	0	0	0
T185	0	1	0	0
T188	497	0	0	0
T189	491	0	0	0
T190	13787	0	0	0
T191	499	0	0	0
T192	539	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	117713	0	0
T4	662	31	0	0
T8	687	139	0	0
T9	500	41	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T23	0	130	0	0
T24	521	0	0	0
T25	5120	0	0	0
T37	0	82	0	0
T39	0	7491	0	0
T40	0	46	0	0
T41	0	40	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	516	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	61	0	0
T4	662	1	0	0
T8	687	2	0	0
T9	500	1	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8093719	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	3	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8095949	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	3	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	70	0	0
T4	662	1	0	0
T8	687	2	0	0
T9	500	1	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T30	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	64	0	0
T4	662	1	0	0
T8	687	2	0	0
T9	500	1	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T86	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	61	0	0
T4	662	1	0	0
T8	687	2	0	0
T9	500	1	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	61	0	0
T4	662	1	0	0
T8	687	2	0	0
T9	500	1	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T23	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	117614	0	0
T4	662	30	0	0
T8	687	136	0	0
T9	500	39	0	0
T16	60186	0	0	0
T20	0	21	0	0
T22	494	0	0	0
T23	0	129	0	0
T24	521	0	0	0
T25	5120	0	0	0
T37	0	79	0	0
T39	0	7489	0	0
T40	0	44	0	0
T41	0	38	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	508	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	21	0	0
T4	662	1	0	0
T8	687	1	0	0
T9	500	0	0	0
T16	60186	0	0	0
T22	494	0	0	0
T23	0	1	0	0
T24	521	0	0	0
T25	5120	0	0	0
T37	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	2	0	0
T80	0	1	0	0
T152	0	1	0	0
T167	0	2	0	0
T193	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T12,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T12,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T12,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T12
1	0	Covered	T1,T6,T3
1	1	Covered	T2,T12,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T30
0	1	Covered	T12,T30,T42
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T12,T30
1	-	Covered	T12,T30,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T30
DetectSt	168	Covered	T2,T12,T30
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T12,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T30
DebounceSt->IdleSt	163	Covered	T81,T195
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T12,T30
IdleSt->DebounceSt	148	Covered	T2,T12,T30
StableSt->IdleSt	206	Covered	T12,T30,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T12,T30
0	1	Covered	T2,T12,T30
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T30
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T30,T42
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	76	0	0
CntIncr_A	9484281	135365	0	0
CntNoWrap_A	9484281	8838742	0	0
DetectStDropOut_A	9484281	0	0	0
DetectedOut_A	9484281	9496	0	0
DetectedPulseOut_A	9484281	37	0	0
DisabledIdleSt_A	9484281	8375092	0	0
DisabledNoDetection_A	9484281	8377326	0	0
EnterDebounceSt_A	9484281	39	0	0
EnterDetectSt_A	9484281	37	0	0
EnterStableSt_A	9484281	37	0	0
PulseIsPulse_A	9484281	37	0	0
StayInStableSt	9484281	9438	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	6142	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	76	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	2	0	0
T22	494	0	0	0
T30	0	4	0	0
T36	0	4	0	0
T42	0	2	0	0
T74	0	2	0	0
T86	0	2	0	0
T107	0	2	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	135365	0	0
T2	692	37	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	62	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T30	0	138	0	0
T36	0	20	0	0
T42	0	100	0	0
T74	0	90	0	0
T86	0	40	0	0
T107	0	46	0	0
T140	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838742	0	0
T1	42319	39839	0	0
T2	692	289	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	9496	0	0
T2	692	44	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	179	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T30	0	101	0	0
T36	0	151	0	0
T42	0	253	0	0
T74	0	42	0	0
T86	0	41	0	0
T107	0	41	0	0
T140	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	37	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T42	0	1	0	0
T74	0	1	0	0
T86	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8375092	0	0
T1	42319	39839	0	0
T2	692	3	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8377326	0	0
T1	42319	39857	0	0
T2	692	3	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	39	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T42	0	1	0	0
T74	0	1	0	0
T86	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	37	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T42	0	1	0	0
T74	0	1	0	0
T86	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	37	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T42	0	1	0	0
T74	0	1	0	0
T86	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	37	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T30	0	2	0	0
T36	0	2	0	0
T42	0	1	0	0
T74	0	1	0	0
T86	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	9438	0	0
T2	692	42	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T12	0	178	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	21	0	0
T22	494	0	0	0
T30	0	98	0	0
T36	0	148	0	0
T42	0	252	0	0
T74	0	41	0	0
T86	0	39	0	0
T107	0	39	0	0
T140	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6142	0	0
T1	42319	26	0	0
T2	692	1	0	0
T3	39847	11	0	0
T4	662	1	0	0
T6	497	6	0	0
T7	480	1	0	0
T8	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	10	0	0
T16	60186	0	0	0
T22	0	10	0	0
T24	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	14	0	0
T12	952	1	0	0
T23	3352	0	0	0
T26	14102	0	0	0
T30	0	1	0	0
T36	0	1	0	0
T42	0	1	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T74	0	1	0	0
T110	425	0	0	0
T111	401	0	0	0
T150	0	1	0	0
T163	0	1	0	0
T165	522	0	0	0
T167	0	1	0	0
T184	0	1	0	0
T186	0	1	0	0