Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T23,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T8,T23,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T23,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T23,T20
1	0	Covered	T1,T6,T2
1	1	Covered	T8,T23,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T23,T20
0	1	Covered	T36,T149,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T23,T20
0	1	Covered	T8,T23,T36
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T23,T20
1	-	Covered	T8,T23,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T23,T20
DetectSt	168	Covered	T8,T23,T20
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T8,T23,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T23,T20
DebounceSt->IdleSt	163	Covered	T197,T169,T144
DetectSt->IdleSt	186	Covered	T36,T149,T196
DetectSt->StableSt	191	Covered	T8,T23,T20
IdleSt->DebounceSt	148	Covered	T8,T23,T20
StableSt->IdleSt	206	Covered	T8,T23,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T23,T20
0	1	Covered	T8,T23,T20
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T23,T20
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T23,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T23,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T197,T169,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T23,T20
DetectSt	-	-	-	-	1	-	-	Covered	T36,T149,T196
DetectSt	-	-	-	-	0	1	-	Covered	T8,T23,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T23,T20
StableSt	-	-	-	-	-	-	0	Covered	T8,T23,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	124	0	0
CntIncr_A	9484281	186479	0	0
CntNoWrap_A	9484281	8838694	0	0
DetectStDropOut_A	9484281	3	0	0
DetectedOut_A	9484281	6846	0	0
DetectedPulseOut_A	9484281	56	0	0
DisabledIdleSt_A	9484281	8444857	0	0
DisabledNoDetection_A	9484281	8447096	0	0
EnterDebounceSt_A	9484281	65	0	0
EnterDetectSt_A	9484281	59	0	0
EnterStableSt_A	9484281	56	0	0
PulseIsPulse_A	9484281	56	0	0
StayInStableSt	9484281	6765	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	124	0	0
T8	687	2	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	2	0	0
T23	0	4	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T38	0	4	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	4	0	0
T76	0	2	0	0
T114	0	2	0	0
T151	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	186479	0	0
T8	687	39	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	22	0	0
T23	0	52	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	20	0	0
T37	0	66	0	0
T38	0	126	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	180	0	0
T76	0	26	0	0
T114	0	18	0	0
T151	0	170	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838694	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	3	0	0
T21	1417	0	0	0
T36	8263	1	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T67	497	0	0	0
T104	526	0	0	0
T105	403	0	0	0
T106	421	0	0	0
T107	584	0	0	0
T149	0	1	0	0
T196	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6846	0	0
T8	687	40	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	24	0	0
T23	0	63	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	7	0	0
T37	0	158	0	0
T38	0	176	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	105	0	0
T76	0	200	0	0
T114	0	10	0	0
T151	0	198	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	56	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	2	0	0
T76	0	1	0	0
T114	0	1	0	0
T151	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8444857	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8447096	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	65	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	2	0	0
T76	0	1	0	0
T114	0	1	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	59	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	2	0	0
T76	0	1	0	0
T114	0	1	0	0
T151	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	56	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	2	0	0
T76	0	1	0	0
T114	0	1	0	0
T151	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	56	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	2	0	0
T76	0	1	0	0
T114	0	1	0	0
T151	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6765	0	0
T8	687	39	0	0
T9	500	0	0	0
T10	5401	0	0	0
T20	0	23	0	0
T23	0	61	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	6	0	0
T37	0	156	0	0
T38	0	173	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	102	0	0
T76	0	198	0	0
T114	0	9	0	0
T151	0	195	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	29	0	0
T8	687	1	0	0
T9	500	0	0	0
T10	5401	0	0	0
T23	0	2	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T69	1787	0	0	0
T74	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T142	0	1	0	0
T151	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T12,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T9,T12,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T12,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T12
1	0	Covered	T1,T6,T2
1	1	Covered	T9,T12,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T23
0	1	Covered	T80,T198
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T23
0	1	Covered	T12,T23,T36
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T23
1	-	Covered	T12,T23,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T12,T23
DetectSt	168	Covered	T9,T12,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T12,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T23
DebounceSt->IdleSt	163	Covered	T163
DetectSt->IdleSt	186	Covered	T80,T198
DetectSt->StableSt	191	Covered	T9,T12,T23
IdleSt->DebounceSt	148	Covered	T9,T12,T23
StableSt->IdleSt	206	Covered	T12,T23,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T12,T23
0	1	Covered	T9,T12,T23
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T12,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T163
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T12,T23
DetectSt	-	-	-	-	1	-	-	Covered	T80,T198
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T23,T20
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	97	0	0
CntIncr_A	9484281	181120	0	0
CntNoWrap_A	9484281	8838721	0	0
DetectStDropOut_A	9484281	2	0	0
DetectedOut_A	9484281	4695	0	0
DetectedPulseOut_A	9484281	46	0	0
DisabledIdleSt_A	9484281	8304144	0	0
DisabledNoDetection_A	9484281	8306376	0	0
EnterDebounceSt_A	9484281	49	0	0
EnterDetectSt_A	9484281	48	0	0
EnterStableSt_A	9484281	46	0	0
PulseIsPulse_A	9484281	46	0	0
StayInStableSt	9484281	4628	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	6213	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	97	0	0
T9	500	2	0	0
T10	5401	0	0	0
T12	0	4	0	0
T20	0	2	0	0
T23	0	4	0	0
T25	5120	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T38	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	2	0	0
T140	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	181120	0	0
T9	500	49	0	0
T10	5401	0	0	0
T12	0	124	0	0
T20	0	22	0	0
T23	0	52	0	0
T25	5120	0	0	0
T36	0	20	0	0
T37	0	53	0	0
T38	0	63	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	90	0	0
T140	0	17	0	0
T151	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838721	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	2	0	0
T80	22613	1	0	0
T95	12774	0	0	0
T139	1864	0	0	0
T141	564	0	0	0
T198	0	1	0	0
T199	442	0	0	0
T200	16416	0	0	0
T201	2874	0	0	0
T202	503	0	0	0
T203	8448	0	0	0
T204	531	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	4695	0	0
T9	500	41	0	0
T10	5401	0	0	0
T12	0	78	0	0
T20	0	22	0	0
T23	0	134	0	0
T25	5120	0	0	0
T36	0	81	0	0
T37	0	144	0	0
T38	0	40	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	207	0	0
T140	0	40	0	0
T151	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	46	0	0
T9	500	1	0	0
T10	5401	0	0	0
T12	0	2	0	0
T20	0	1	0	0
T23	0	2	0	0
T25	5120	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	1	0	0
T140	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8304144	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	3	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8306376	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	3	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	49	0	0
T9	500	1	0	0
T10	5401	0	0	0
T12	0	2	0	0
T20	0	1	0	0
T23	0	2	0	0
T25	5120	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	1	0	0
T140	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	48	0	0
T9	500	1	0	0
T10	5401	0	0	0
T12	0	2	0	0
T20	0	1	0	0
T23	0	2	0	0
T25	5120	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	1	0	0
T140	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	46	0	0
T9	500	1	0	0
T10	5401	0	0	0
T12	0	2	0	0
T20	0	1	0	0
T23	0	2	0	0
T25	5120	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	1	0	0
T140	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	46	0	0
T9	500	1	0	0
T10	5401	0	0	0
T12	0	2	0	0
T20	0	1	0	0
T23	0	2	0	0
T25	5120	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	1	0	0
T140	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	4628	0	0
T9	500	39	0	0
T10	5401	0	0	0
T12	0	75	0	0
T20	0	21	0	0
T23	0	131	0	0
T25	5120	0	0	0
T36	0	78	0	0
T37	0	143	0	0
T38	0	39	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T74	0	206	0	0
T140	0	38	0	0
T151	0	61	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6213	0	0
T1	42319	28	0	0
T2	692	1	0	0
T3	39847	10	0	0
T4	662	0	0	0
T6	497	7	0	0
T7	480	1	0	0
T8	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	9	0	0
T16	60186	0	0	0
T22	0	8	0	0
T24	0	5	0	0
T69	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	23	0	0
T12	952	1	0	0
T23	3352	1	0	0
T26	14102	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T74	0	1	0	0
T110	425	0	0	0
T111	401	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T165	522	0	0	0
T166	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T12,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T12,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T12,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T20
1	0	Covered	T1,T6,T2
1	1	Covered	T4,T12,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T20
0	1	Covered	T205,T196,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T20
0	1	Covered	T12,T36,T38
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T12,T20
1	-	Covered	T12,T36,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T20
DetectSt	168	Covered	T4,T12,T20
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T12,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T12,T20
DebounceSt->IdleSt	163	Covered	T166,T207,T169
DetectSt->IdleSt	186	Covered	T205,T196,T206
DetectSt->StableSt	191	Covered	T4,T12,T20
IdleSt->DebounceSt	148	Covered	T4,T12,T20
StableSt->IdleSt	206	Covered	T12,T20,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T12,T20
0	1	Covered	T4,T12,T20
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T20
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T12,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T166,T169,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T20
DetectSt	-	-	-	-	1	-	-	Covered	T205,T196,T206
DetectSt	-	-	-	-	0	1	-	Covered	T4,T12,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T20,T36
StableSt	-	-	-	-	-	-	0	Covered	T4,T12,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	128	0	0
CntIncr_A	9484281	194549	0	0
CntNoWrap_A	9484281	8838690	0	0
DetectStDropOut_A	9484281	4	0	0
DetectedOut_A	9484281	74563	0	0
DetectedPulseOut_A	9484281	58	0	0
DisabledIdleSt_A	9484281	8327127	0	0
DisabledNoDetection_A	9484281	8329366	0	0
EnterDebounceSt_A	9484281	68	0	0
EnterDetectSt_A	9484281	62	0	0
EnterStableSt_A	9484281	58	0	0
PulseIsPulse_A	9484281	58	0	0
StayInStableSt	9484281	74483	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	128	0	0
T4	662	2	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	4	0	0
T16	60186	0	0	0
T20	0	2	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	4	0	0
T38	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	4	0	0
T86	0	2	0	0
T136	0	2	0	0
T151	0	4	0	0
T166	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	194549	0	0
T4	662	91	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	124	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	20	0	0
T38	0	63	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	83	0	0
T86	0	40	0	0
T136	0	94	0	0
T151	0	170	0	0
T166	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838690	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	259	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	4	0	0
T88	22485	0	0	0
T196	0	1	0	0
T205	748	1	0	0
T206	0	1	0	0
T208	0	1	0	0
T209	406	0	0	0
T210	422	0	0	0
T211	522	0	0	0
T212	1673	0	0	0
T213	15690	0	0	0
T214	443	0	0	0
T215	467	0	0	0
T216	441	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	74563	0	0
T4	662	39	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	14	0	0
T16	60186	0	0	0
T20	0	24	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	14	0	0
T38	0	162	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	114	0	0
T86	0	165	0	0
T136	0	136	0	0
T151	0	85	0	0
T152	0	95	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	58	0	0
T4	662	1	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	2	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	2	0	0
T86	0	1	0	0
T136	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8327127	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	3	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8329366	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	3	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	68	0	0
T4	662	1	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	2	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	2	0	0
T86	0	1	0	0
T136	0	1	0	0
T151	0	2	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	62	0	0
T4	662	1	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	2	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	2	0	0
T86	0	1	0	0
T136	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	58	0	0
T4	662	1	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	2	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	2	0	0
T86	0	1	0	0
T136	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	58	0	0
T4	662	1	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	2	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	2	0	0
T86	0	1	0	0
T136	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	74483	0	0
T4	662	37	0	0
T8	687	0	0	0
T9	500	0	0	0
T12	0	12	0	0
T16	60186	0	0	0
T20	0	23	0	0
T22	494	0	0	0
T24	521	0	0	0
T25	5120	0	0	0
T36	0	12	0	0
T38	0	161	0	0
T50	4442	0	0	0
T51	527	0	0	0
T69	1787	0	0	0
T77	0	112	0	0
T86	0	163	0	0
T136	0	134	0	0
T151	0	83	0	0
T152	0	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	34	0	0
T12	952	2	0	0
T23	3352	0	0	0
T26	14102	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T45	17955	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T77	0	2	0	0
T80	0	1	0	0
T110	425	0	0	0
T111	401	0	0	0
T141	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T165	522	0	0	0
T178	0	1	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T20,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T20,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T20,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T39
1	0	Covered	T1,T6,T2
1	1	Covered	T20,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T36,T37
0	1	Covered	T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T36,T37
0	1	Covered	T37,T151,T197
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T36,T37
1	-	Covered	T37,T151,T197

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T36,T37
DetectSt	168	Covered	T20,T36,T37
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T20,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T36,T37
DebounceSt->IdleSt	163	Covered	T218
DetectSt->IdleSt	186	Covered	T81
DetectSt->StableSt	191	Covered	T20,T36,T37
IdleSt->DebounceSt	148	Covered	T20,T36,T37
StableSt->IdleSt	206	Covered	T20,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T36,T37
0	1	Covered	T20,T36,T37
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T36,T37
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T218
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T81
DetectSt	-	-	-	-	0	1	-	Covered	T20,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T37,T151
StableSt	-	-	-	-	-	-	0	Covered	T20,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	73	0	0
CntIncr_A	9484281	126654	0	0
CntNoWrap_A	9484281	8838745	0	0
DetectStDropOut_A	9484281	1	0	0
DetectedOut_A	9484281	26438	0	0
DetectedPulseOut_A	9484281	35	0	0
DisabledIdleSt_A	9484281	8210894	0	0
DisabledNoDetection_A	9484281	8213131	0	0
EnterDebounceSt_A	9484281	37	0	0
EnterDetectSt_A	9484281	36	0	0
EnterStableSt_A	9484281	35	0	0
PulseIsPulse_A	9484281	35	0	0
StayInStableSt	9484281	26383	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	6155	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	73	0	0
T20	8226	2	0	0
T36	8263	2	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	4	0	0
T152	0	2	0	0
T178	0	2	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	126654	0	0
T20	8226	22	0	0
T36	8263	17	0	0
T37	0	172	0	0
T38	0	63	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	26	0	0
T77	0	11	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	170	0	0
T152	0	30	0	0
T178	0	84	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838745	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1	0	0
T81	2870	1	0	0
T85	183755	0	0	0
T87	1397	0	0	0
T117	494	0	0	0
T118	492	0	0	0
T119	5566	0	0	0
T219	21810	0	0	0
T220	6344	0	0	0
T221	405	0	0	0
T222	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	26438	0	0
T20	8226	24	0	0
T36	8263	47	0	0
T37	0	571	0	0
T38	0	118	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	91	0	0
T77	0	110	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	90	0	0
T152	0	140	0	0
T178	0	178	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	35	0	0
T20	8226	1	0	0
T36	8263	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T178	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8210894	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	3	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8213131	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	3	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	37	0	0
T20	8226	1	0	0
T36	8263	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T178	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	36	0	0
T20	8226	1	0	0
T36	8263	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T178	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	35	0	0
T20	8226	1	0	0
T36	8263	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T178	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	35	0	0
T20	8226	1	0	0
T36	8263	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T178	0	1	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	26383	0	0
T20	8226	23	0	0
T36	8263	45	0	0
T37	0	566	0	0
T38	0	116	0	0
T39	133295	0	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T76	0	89	0	0
T77	0	108	0	0
T104	526	0	0	0
T105	403	0	0	0
T151	0	87	0	0
T152	0	138	0	0
T178	0	176	0	0
T182	501	0	0	0
T183	420	0	0	0
T217	0	79	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6155	0	0
T1	42319	33	0	0
T2	692	1	0	0
T3	39847	14	0	0
T4	662	0	0	0
T6	497	7	0	0
T7	480	1	0	0
T8	0	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	11	0	0
T16	60186	0	0	0
T22	0	9	0	0
T24	0	6	0	0
T69	0	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	13	0	0
T37	274589	1	0	0
T38	3708	0	0	0
T41	10121	0	0	0
T86	656	0	0	0
T88	0	1	0	0
T109	719	0	0	0
T140	2684	0	0	0
T145	0	1	0	0
T149	0	2	0	0
T151	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T188	497	0	0	0
T197	0	1	0	0
T205	0	1	0	0
T223	0	1	0	0
T224	18485	0	0	0
T225	490	0	0	0
T226	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T8,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T8,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T8,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T30
1	0	Covered	T5,T1,T6
1	1	Covered	T2,T8,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T42
0	1	Covered	T146
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T42
0	1	Covered	T2,T8,T42
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T42
1	-	Covered	T2,T8,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T42
DetectSt	168	Covered	T2,T8,T42
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T8,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T42
DebounceSt->IdleSt	163	Covered	T37,T178,T142
DetectSt->IdleSt	186	Covered	T146
DetectSt->StableSt	191	Covered	T2,T8,T42
IdleSt->DebounceSt	148	Covered	T2,T8,T42
StableSt->IdleSt	206	Covered	T2,T8,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T42
0	1	Covered	T2,T8,T42
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T42
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T178,T142
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T42
DetectSt	-	-	-	-	1	-	-	Covered	T146
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T42
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	142	0	0
CntIncr_A	9484281	56526	0	0
CntNoWrap_A	9484281	8838676	0	0
DetectStDropOut_A	9484281	1	0	0
DetectedOut_A	9484281	55015	0	0
DetectedPulseOut_A	9484281	67	0	0
DisabledIdleSt_A	9484281	8623625	0	0
DisabledNoDetection_A	9484281	8625860	0	0
EnterDebounceSt_A	9484281	74	0	0
EnterDetectSt_A	9484281	68	0	0
EnterStableSt_A	9484281	67	0	0
PulseIsPulse_A	9484281	67	0	0
StayInStableSt	9484281	54919	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	142	0	0
T2	692	4	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	2	0	0
T22	494	0	0	0
T36	0	2	0	0
T37	0	3	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	6	0	0
T74	0	2	0	0
T86	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	56526	0	0
T2	692	74	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	39	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T36	0	10	0	0
T37	0	106	0	0
T40	0	34	0	0
T41	0	16	0	0
T42	0	300	0	0
T74	0	90	0	0
T86	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838676	0	0
T1	42319	39839	0	0
T2	692	287	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1	0	0
T146	19607	1	0	0
T153	18961	0	0	0
T154	570	0	0	0
T155	422	0	0	0
T156	670	0	0	0
T157	618	0	0	0
T158	407	0	0	0
T159	422	0	0	0
T160	11966	0	0	0
T161	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	55015	0	0
T2	692	45	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	95	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	23	0	0
T22	494	0	0	0
T36	0	77	0	0
T37	0	197	0	0
T40	0	39	0	0
T41	0	1	0	0
T42	0	315	0	0
T74	0	44	0	0
T86	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	67	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T74	0	1	0	0
T86	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8623625	0	0
T1	42319	39839	0	0
T2	692	3	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8625860	0	0
T1	42319	39857	0	0
T2	692	3	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	74	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T74	0	1	0	0
T86	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	68	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T74	0	1	0	0
T86	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	67	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T74	0	1	0	0
T86	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	67	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T74	0	1	0	0
T86	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	54919	0	0
T2	692	43	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	94	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T36	0	76	0	0
T37	0	196	0	0
T40	0	37	0	0
T42	0	311	0	0
T74	0	43	0	0
T75	0	38	0	0
T86	0	81	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	36	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T74	0	1	0	0
T80	0	2	0	0
T86	0	1	0	0
T167	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T8,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T8,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T8,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T2,T8,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T20
0	1	Covered	T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T20
0	1	Covered	T2,T37,T162
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T20
1	-	Covered	T2,T37,T162

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T20
DetectSt	168	Covered	T2,T8,T20
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T8,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T20
DebounceSt->IdleSt	163	Covered	T166,T169
DetectSt->IdleSt	186	Covered	T206
DetectSt->StableSt	191	Covered	T2,T8,T20
IdleSt->DebounceSt	148	Covered	T2,T8,T20
StableSt->IdleSt	206	Covered	T2,T20,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T20
0	1	Covered	T2,T8,T20
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T20
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T20
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T166,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T20
DetectSt	-	-	-	-	1	-	-	Covered	T206
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T20,T37
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	86	0	0
CntIncr_A	9484281	81916	0	0
CntNoWrap_A	9484281	8838732	0	0
DetectStDropOut_A	9484281	1	0	0
DetectedOut_A	9484281	14359	0	0
DetectedPulseOut_A	9484281	41	0	0
DisabledIdleSt_A	9484281	8341461	0	0
DisabledNoDetection_A	9484281	8343692	0	0
EnterDebounceSt_A	9484281	44	0	0
EnterDetectSt_A	9484281	42	0	0
EnterStableSt_A	9484281	41	0	0
PulseIsPulse_A	9484281	41	0	0
StayInStableSt	9484281	14292	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9484281	6822	0	0
gen_low_level_sva.LowLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	86	0	0
T2	692	4	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	2	0	0
T22	494	0	0	0
T36	0	2	0	0
T37	0	6	0	0
T74	0	2	0	0
T77	0	2	0	0
T80	0	2	0	0
T114	0	2	0	0
T166	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	81916	0	0
T2	692	74	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	39	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T36	0	10	0	0
T37	0	172	0	0
T74	0	90	0	0
T77	0	23	0	0
T80	0	58	0	0
T114	0	18	0	0
T166	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838732	0	0
T1	42319	39839	0	0
T2	692	287	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1	0	0
T206	839	1	0	0
T208	58739	0	0	0
T227	962	0	0	0
T228	8838	0	0	0
T229	422	0	0	0
T230	516	0	0	0
T231	8416	0	0	0
T232	502	0	0	0
T233	406	0	0	0
T234	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	14359	0	0
T2	692	86	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	103	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	23	0	0
T22	494	0	0	0
T36	0	103	0	0
T37	0	126	0	0
T74	0	205	0	0
T77	0	47	0	0
T80	0	43	0	0
T114	0	51	0	0
T217	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	41	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T74	0	1	0	0
T77	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8341461	0	0
T1	42319	39839	0	0
T2	692	3	0	0
T3	39847	39343	0	0
T4	662	3	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8343692	0	0
T1	42319	39857	0	0
T2	692	3	0	0
T3	39847	39359	0	0
T4	662	3	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	44	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T74	0	1	0	0
T77	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	42	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T74	0	1	0	0
T77	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	41	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T74	0	1	0	0
T77	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	41	0	0
T2	692	2	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	1	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T22	494	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T74	0	1	0	0
T77	0	1	0	0
T80	0	1	0	0
T114	0	1	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	14292	0	0
T2	692	83	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	101	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	22	0	0
T22	494	0	0	0
T36	0	101	0	0
T37	0	121	0	0
T74	0	203	0	0
T77	0	45	0	0
T80	0	41	0	0
T114	0	49	0	0
T217	0	80	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	6822	0	0
T1	42319	28	0	0
T2	692	2	0	0
T3	39847	14	0	0
T4	662	0	0	0
T5	758	3	0	0
T6	497	7	0	0
T7	480	0	0	0
T8	0	1	0	0
T13	705	3	0	0
T14	714	0	0	0
T15	3975	11	0	0
T16	0	3	0	0
T22	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	13	0	0
T2	692	1	0	0
T3	39847	0	0	0
T4	662	0	0	0
T7	480	0	0	0
T8	687	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T22	494	0	0	0
T37	0	1	0	0
T81	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T218	0	1	0	0
T235	0	1	0	0