Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T11,T26
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T11,T26
1	0	Covered	T11,T26,T45
1	1	Covered	T25,T11,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T11,T26
0	1	Covered	T25,T45,T20
1	0	Covered	T45,T20,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T26,T20
0	1	Covered	T11,T26,T20
1	0	Covered	T83,T236

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T26,T20
1	-	Covered	T11,T26,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T11,T26
DetectSt	168	Covered	T25,T11,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T26,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T11,T26
DebounceSt->IdleSt	163	Covered	T20,T58
DetectSt->IdleSt	186	Covered	T25,T45,T20
DetectSt->StableSt	191	Covered	T11,T26,T20
IdleSt->DebounceSt	148	Covered	T25,T11,T26
StableSt->IdleSt	206	Covered	T11,T26,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T11,T26
0	1	Covered	T25,T11,T26
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T11,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T11,T26
IdleSt	0	-	-	-	-	-	-	Covered	T25,T11,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T11,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T11,T26
DetectSt	-	-	-	-	1	-	-	Covered	T25,T45,T20
DetectSt	-	-	-	-	0	1	-	Covered	T11,T26,T20
DetectSt	-	-	-	-	0	0	-	Covered	T25,T11,T26
StableSt	-	-	-	-	-	-	1	Covered	T11,T26,T20
StableSt	-	-	-	-	-	-	0	Covered	T11,T26,T20
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	2894	0	0
CntIncr_A	9484281	100879	0	0
CntNoWrap_A	9484281	8835924	0	0
DetectStDropOut_A	9484281	415	0	0
DetectedOut_A	9484281	66585	0	0
DetectedPulseOut_A	9484281	822	0	0
DisabledIdleSt_A	9484281	8386952	0	0
DisabledNoDetection_A	9484281	8389050	0	0
EnterDebounceSt_A	9484281	1449	0	0
EnterDetectSt_A	9484281	1445	0	0
EnterStableSt_A	9484281	822	0	0
PulseIsPulse_A	9484281	822	0	0
StayInStableSt	9484281	65661	0	0
gen_high_event_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	711	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	2894	0	0
T10	5401	0	0	0
T11	0	40	0	0
T20	0	16	0	0
T25	5120	54	0	0
T26	0	20	0	0
T43	0	28	0	0
T44	0	24	0	0
T45	0	12	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	22	0	0
T72	0	38	0	0
T73	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	100879	0	0
T10	5401	0	0	0
T11	0	1740	0	0
T20	0	750	0	0
T25	5120	1353	0	0
T26	0	660	0	0
T43	0	3780	0	0
T44	0	924	0	0
T45	0	455	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	747	0	0
T72	0	1041	0	0
T73	0	649	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8835924	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	415	0	0
T10	5401	0	0	0
T20	0	1	0	0
T25	5120	27	0	0
T45	0	2	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T72	0	18	0	0
T73	0	14	0	0
T92	0	20	0	0
T93	0	13	0	0
T94	0	13	0	0
T95	0	3	0	0
T96	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	66585	0	0
T11	26257	3343	0	0
T12	952	0	0	0
T20	0	426	0	0
T26	14102	459	0	0
T43	0	3907	0	0
T44	0	1923	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	1009	0	0
T200	0	2053	0	0
T237	0	3097	0	0
T238	0	677	0	0
T239	0	1678	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	822	0	0
T11	26257	20	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	10	0	0
T43	0	14	0	0
T44	0	12	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	22	0	0
T200	0	23	0	0
T237	0	23	0	0
T238	0	13	0	0
T239	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8386952	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8389050	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1449	0	0
T10	5401	0	0	0
T11	0	20	0	0
T20	0	9	0	0
T25	5120	27	0	0
T26	0	10	0	0
T43	0	14	0	0
T44	0	12	0	0
T45	0	6	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	11	0	0
T72	0	19	0	0
T73	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1445	0	0
T10	5401	0	0	0
T11	0	20	0	0
T20	0	7	0	0
T25	5120	27	0	0
T26	0	10	0	0
T43	0	14	0	0
T44	0	12	0	0
T45	0	6	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	11	0	0
T72	0	19	0	0
T73	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	822	0	0
T11	26257	20	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	10	0	0
T43	0	14	0	0
T44	0	12	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	22	0	0
T200	0	23	0	0
T237	0	23	0	0
T238	0	13	0	0
T239	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	822	0	0
T11	26257	20	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	10	0	0
T43	0	14	0	0
T44	0	12	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	22	0	0
T200	0	23	0	0
T237	0	23	0	0
T238	0	13	0	0
T239	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	65661	0	0
T11	26257	3318	0	0
T12	952	0	0	0
T20	0	421	0	0
T26	14102	448	0	0
T43	0	3890	0	0
T44	0	1911	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	986	0	0
T200	0	2026	0	0
T237	0	3066	0	0
T238	0	661	0	0
T239	0	1652	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	711	0	0
T11	26257	15	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	9	0	0
T43	0	11	0	0
T44	0	12	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	21	0	0
T200	0	19	0	0
T237	0	15	0	0
T238	0	10	0	0
T239	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T10
0	1	Covered	T36,T34,T41
1	0	Covered	T20,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T10
0	1	Covered	T1,T7,T10
1	0	Covered	T79,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T10
1	-	Covered	T1,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T10
DetectSt	168	Covered	T1,T7,T10
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T10
DebounceSt->IdleSt	163	Covered	T20,T34,T37
DetectSt->IdleSt	186	Covered	T20,T36,T34
DetectSt->StableSt	191	Covered	T1,T7,T10
IdleSt->DebounceSt	148	Covered	T1,T7,T10
StableSt->IdleSt	206	Covered	T1,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T10
0	1	Covered	T1,T7,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T10
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T37,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T20,T36,T34
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	896	0	0
CntIncr_A	9484281	47248	0	0
CntNoWrap_A	9484281	8837922	0	0
DetectStDropOut_A	9484281	70	0	0
DetectedOut_A	9484281	14905	0	0
DetectedPulseOut_A	9484281	345	0	0
DisabledIdleSt_A	9484281	8496917	0	0
DisabledNoDetection_A	9484281	8498539	0	0
EnterDebounceSt_A	9484281	478	0	0
EnterDetectSt_A	9484281	420	0	0
EnterStableSt_A	9484281	345	0	0
PulseIsPulse_A	9484281	345	0	0
StayInStableSt	9484281	14529	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	311	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	896	0	0
T1	42319	10	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	2	0	0
T10	0	4	0	0
T11	0	10	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	8	0	0
T26	0	2	0	0
T33	0	2	0	0
T36	0	3	0	0
T59	0	22	0	0
T91	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	47248	0	0
T1	42319	665	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	25	0	0
T10	0	50	0	0
T11	0	475	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	275	0	0
T26	0	45	0	0
T33	0	141	0	0
T36	0	163	0	0
T59	0	1210	0	0
T91	0	375	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8837922	0	0
T1	42319	39829	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	77	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	70	0	0
T21	1417	0	0	0
T34	0	4	0	0
T36	8263	1	0	0
T41	0	7	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T67	497	0	0	0
T97	0	21	0	0
T98	0	4	0	0
T99	0	3	0	0
T100	0	7	0	0
T101	0	13	0	0
T102	0	4	0	0
T103	0	1	0	0
T104	526	0	0	0
T105	403	0	0	0
T106	421	0	0	0
T107	584	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	14905	0	0
T1	42319	20	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	4	0	0
T10	0	6	0	0
T11	0	275	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	79	0	0
T26	0	52	0	0
T33	0	65	0	0
T59	0	1072	0	0
T91	0	76	0	0
T108	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	345	0	0
T1	42319	5	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	1	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	1	0	0
T33	0	1	0	0
T59	0	11	0	0
T91	0	3	0	0
T108	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8496917	0	0
T1	42319	33018	0	0
T2	692	291	0	0
T3	39847	32233	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	3	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8498539	0	0
T1	42319	33029	0	0
T2	692	292	0	0
T3	39847	32233	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	3	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	478	0	0
T1	42319	5	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	1	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	5	0	0
T26	0	1	0	0
T33	0	1	0	0
T36	0	2	0	0
T59	0	11	0	0
T91	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	420	0	0
T1	42319	5	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	1	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	3	0	0
T26	0	1	0	0
T33	0	1	0	0
T36	0	2	0	0
T59	0	11	0	0
T91	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	345	0	0
T1	42319	5	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	1	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	1	0	0
T33	0	1	0	0
T59	0	11	0	0
T91	0	3	0	0
T108	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	345	0	0
T1	42319	5	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	1	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	1	0	0
T33	0	1	0	0
T59	0	11	0	0
T91	0	3	0	0
T108	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	14529	0	0
T1	42319	15	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	3	0	0
T10	0	4	0	0
T11	0	270	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	78	0	0
T26	0	51	0	0
T33	0	64	0	0
T59	0	1061	0	0
T91	0	73	0	0
T108	0	17	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	311	0	0
T1	42319	5	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	1	0	0
T10	0	2	0	0
T11	0	5	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	1	0	0
T33	0	1	0	0
T59	0	11	0	0
T91	0	3	0	0
T108	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T11,T26
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T11,T26
1	0	Covered	T11,T26,T45
1	1	Covered	T25,T11,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T11,T26
0	1	Covered	T25,T45,T20
1	0	Covered	T11,T26,T45

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T43,T44
0	1	Covered	T20,T43,T44
1	0	Covered	T43,T82,T240

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T43,T44
1	-	Covered	T20,T43,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T11,T26
DetectSt	168	Covered	T25,T11,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T20,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T11,T26
DebounceSt->IdleSt	163	Covered	T20,T58
DetectSt->IdleSt	186	Covered	T25,T11,T26
DetectSt->StableSt	191	Covered	T20,T43,T44
IdleSt->DebounceSt	148	Covered	T25,T11,T26
StableSt->IdleSt	206	Covered	T20,T43,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T11,T26
0	1	Covered	T25,T11,T26
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T11,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T11,T26
IdleSt	0	-	-	-	-	-	-	Covered	T25,T11,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T11,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T11,T26
DetectSt	-	-	-	-	1	-	-	Covered	T25,T11,T26
DetectSt	-	-	-	-	0	1	-	Covered	T20,T43,T44
DetectSt	-	-	-	-	0	0	-	Covered	T25,T11,T26
StableSt	-	-	-	-	-	-	1	Covered	T20,T43,T44
StableSt	-	-	-	-	-	-	0	Covered	T20,T43,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	3233	0	0
CntIncr_A	9484281	110593	0	0
CntNoWrap_A	9484281	8835585	0	0
DetectStDropOut_A	9484281	457	0	0
DetectedOut_A	9484281	85611	0	0
DetectedPulseOut_A	9484281	966	0	0
DisabledIdleSt_A	9484281	8375600	0	0
DisabledNoDetection_A	9484281	8377688	0	0
EnterDebounceSt_A	9484281	1619	0	0
EnterDetectSt_A	9484281	1615	0	0
EnterStableSt_A	9484281	966	0	0
PulseIsPulse_A	9484281	966	0	0
StayInStableSt	9484281	84533	0	0
gen_high_event_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	808	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	3233	0	0
T10	5401	0	0	0
T11	0	4	0	0
T20	0	16	0	0
T25	5120	12	0	0
T26	0	18	0	0
T43	0	56	0	0
T44	0	20	0	0
T45	0	58	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	48	0	0
T72	0	16	0	0
T73	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	110593	0	0
T10	5401	0	0	0
T11	0	271	0	0
T20	0	715	0	0
T25	5120	294	0	0
T26	0	717	0	0
T43	0	7644	0	0
T44	0	830	0	0
T45	0	2207	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	1629	0	0
T72	0	436	0	0
T73	0	1126	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8835585	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	457	0	0
T10	5401	0	0	0
T20	0	1	0	0
T25	5120	6	0	0
T45	0	20	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	11	0	0
T72	0	7	0	0
T73	0	24	0	0
T92	0	6	0	0
T93	0	7	0	0
T94	0	8	0	0
T238	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	85611	0	0
T20	8226	434	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T43	0	2766	0	0
T44	0	403	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T82	0	4	0	0
T95	0	977	0	0
T104	526	0	0	0
T105	403	0	0	0
T129	0	1811	0	0
T182	501	0	0	0
T183	420	0	0	0
T200	0	574	0	0
T203	0	788	0	0
T237	0	2168	0	0
T239	0	806	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	966	0	0
T20	8226	5	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T43	0	28	0	0
T44	0	10	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T82	0	4	0	0
T95	0	12	0	0
T104	526	0	0	0
T105	403	0	0	0
T129	0	14	0	0
T182	501	0	0	0
T183	420	0	0	0
T200	0	13	0	0
T203	0	26	0	0
T237	0	25	0	0
T239	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8375600	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8377688	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1619	0	0
T10	5401	0	0	0
T11	0	2	0	0
T20	0	9	0	0
T25	5120	6	0	0
T26	0	9	0	0
T43	0	28	0	0
T44	0	10	0	0
T45	0	29	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	24	0	0
T72	0	8	0	0
T73	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1615	0	0
T10	5401	0	0	0
T11	0	2	0	0
T20	0	7	0	0
T25	5120	6	0	0
T26	0	9	0	0
T43	0	28	0	0
T44	0	10	0	0
T45	0	29	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	24	0	0
T72	0	8	0	0
T73	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	966	0	0
T20	8226	5	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T43	0	28	0	0
T44	0	10	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T82	0	4	0	0
T95	0	12	0	0
T104	526	0	0	0
T105	403	0	0	0
T129	0	14	0	0
T182	501	0	0	0
T183	420	0	0	0
T200	0	13	0	0
T203	0	26	0	0
T237	0	25	0	0
T239	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	966	0	0
T20	8226	5	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T43	0	28	0	0
T44	0	10	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T82	0	4	0	0
T95	0	12	0	0
T104	526	0	0	0
T105	403	0	0	0
T129	0	14	0	0
T182	501	0	0	0
T183	420	0	0	0
T200	0	13	0	0
T203	0	26	0	0
T237	0	25	0	0
T239	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	84533	0	0
T20	8226	429	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T43	0	2738	0	0
T44	0	393	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T95	0	964	0	0
T104	526	0	0	0
T105	403	0	0	0
T129	0	1796	0	0
T182	501	0	0	0
T183	420	0	0	0
T200	0	560	0	0
T203	0	762	0	0
T237	0	2133	0	0
T239	0	795	0	0
T241	0	692	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	808	0	0
T20	8226	5	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T43	0	5	0	0
T44	0	10	0	0
T48	763	0	0	0
T49	664	0	0	0
T62	2523	0	0	0
T95	0	11	0	0
T104	526	0	0	0
T105	403	0	0	0
T129	0	13	0	0
T182	501	0	0	0
T183	420	0	0	0
T200	0	12	0	0
T203	0	26	0	0
T237	0	15	0	0
T239	0	9	0	0
T241	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T25
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T33,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T33,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T33,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T30
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T33,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T33,T20
0	1	Covered	T1,T41,T224
1	0	Covered	T20,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T20,T91
0	1	Covered	T33,T91,T59
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T20,T91
1	-	Covered	T33,T20,T91

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T33,T20
DetectSt	168	Covered	T1,T33,T20
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T33,T20,T91

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T33,T20
DebounceSt->IdleSt	163	Covered	T1,T33,T20
DetectSt->IdleSt	186	Covered	T1,T20,T41
DetectSt->StableSt	191	Covered	T33,T20,T91
IdleSt->DebounceSt	148	Covered	T1,T33,T20
StableSt->IdleSt	206	Covered	T33,T20,T91

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T33,T20
0	1	Covered	T1,T33,T20
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T33,T20
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T33,T20
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T33,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T33,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T33,T20
DetectSt	-	-	-	-	1	-	-	Covered	T1,T20,T41
DetectSt	-	-	-	-	0	1	-	Covered	T33,T20,T91
DetectSt	-	-	-	-	0	0	-	Covered	T1,T33,T20
StableSt	-	-	-	-	-	-	1	Covered	T33,T20,T91
StableSt	-	-	-	-	-	-	0	Covered	T33,T20,T91
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	907	0	0
CntIncr_A	9484281	49954	0	0
CntNoWrap_A	9484281	8837911	0	0
DetectStDropOut_A	9484281	71	0	0
DetectedOut_A	9484281	18902	0	0
DetectedPulseOut_A	9484281	353	0	0
DisabledIdleSt_A	9484281	8467871	0	0
DisabledNoDetection_A	9484281	8469521	0	0
EnterDebounceSt_A	9484281	482	0	0
EnterDetectSt_A	9484281	428	0	0
EnterStableSt_A	9484281	353	0	0
PulseIsPulse_A	9484281	353	0	0
StayInStableSt	9484281	18498	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	907	0	0
T1	42319	19	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	8	0	0
T33	0	21	0	0
T34	0	11	0	0
T41	0	2	0	0
T59	0	18	0	0
T91	0	8	0	0
T108	0	7	0	0
T224	0	2	0	0
T242	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	49954	0	0
T1	42319	1163	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	285	0	0
T33	0	1764	0	0
T34	0	723	0	0
T41	0	89	0	0
T59	0	1818	0	0
T91	0	340	0	0
T108	0	291	0	0
T224	0	155	0	0
T242	0	631	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8837911	0	0
T1	42319	39820	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	71	0	0
T1	42319	9	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T41	0	1	0	0
T84	0	2	0	0
T99	0	4	0	0
T224	0	1	0	0
T243	0	5	0	0
T244	0	11	0	0
T245	0	1	0	0
T246	0	6	0	0
T247	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	18902	0	0
T20	8226	80	0	0
T31	2267	0	0	0
T33	26142	350	0	0
T34	0	104	0	0
T35	0	735	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T47	749	0	0	0
T59	0	44	0	0
T66	495	0	0	0
T76	0	21	0	0
T91	0	263	0	0
T108	0	86	0	0
T164	424	0	0	0
T182	501	0	0	0
T183	420	0	0	0
T242	0	65	0	0
T248	0	627	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	353	0	0
T20	8226	1	0	0
T31	2267	0	0	0
T33	26142	9	0	0
T34	0	4	0	0
T35	0	10	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T47	749	0	0	0
T59	0	9	0	0
T66	495	0	0	0
T76	0	3	0	0
T91	0	4	0	0
T108	0	3	0	0
T164	424	0	0	0
T182	501	0	0	0
T183	420	0	0	0
T242	0	4	0	0
T248	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8467871	0	0
T1	42319	30451	0	0
T2	692	291	0	0
T3	39847	32233	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8469521	0	0
T1	42319	30454	0	0
T2	692	292	0	0
T3	39847	32233	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	482	0	0
T1	42319	10	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	5	0	0
T33	0	12	0	0
T34	0	7	0	0
T41	0	1	0	0
T59	0	9	0	0
T91	0	4	0	0
T108	0	4	0	0
T224	0	1	0	0
T242	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	428	0	0
T1	42319	9	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	3	0	0
T33	0	9	0	0
T34	0	4	0	0
T41	0	1	0	0
T59	0	9	0	0
T91	0	4	0	0
T108	0	3	0	0
T224	0	1	0	0
T242	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	353	0	0
T20	8226	1	0	0
T31	2267	0	0	0
T33	26142	9	0	0
T34	0	4	0	0
T35	0	10	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T47	749	0	0	0
T59	0	9	0	0
T66	495	0	0	0
T76	0	3	0	0
T91	0	4	0	0
T108	0	3	0	0
T164	424	0	0	0
T182	501	0	0	0
T183	420	0	0	0
T242	0	4	0	0
T248	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	353	0	0
T20	8226	1	0	0
T31	2267	0	0	0
T33	26142	9	0	0
T34	0	4	0	0
T35	0	10	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T47	749	0	0	0
T59	0	9	0	0
T66	495	0	0	0
T76	0	3	0	0
T91	0	4	0	0
T108	0	3	0	0
T164	424	0	0	0
T182	501	0	0	0
T183	420	0	0	0
T242	0	4	0	0
T248	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	18498	0	0
T20	8226	79	0	0
T31	2267	0	0	0
T33	26142	341	0	0
T34	0	100	0	0
T35	0	725	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T47	749	0	0	0
T59	0	35	0	0
T66	495	0	0	0
T76	0	18	0	0
T91	0	259	0	0
T108	0	83	0	0
T164	424	0	0	0
T182	501	0	0	0
T183	420	0	0	0
T242	0	61	0	0
T248	0	618	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	299	0	0
T20	8226	0	0	0
T31	2267	0	0	0
T33	26142	9	0	0
T34	0	4	0	0
T35	0	10	0	0
T36	8263	0	0	0
T39	133295	0	0	0
T47	749	0	0	0
T59	0	9	0	0
T66	495	0	0	0
T76	0	3	0	0
T78	0	3	0	0
T91	0	4	0	0
T108	0	3	0	0
T164	424	0	0	0
T182	501	0	0	0
T183	420	0	0	0
T242	0	4	0	0
T248	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T11,T26
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T11,T26
1	0	Covered	T11,T26,T45
1	1	Covered	T25,T11,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T11,T26
0	1	Covered	T25,T20,T71
1	0	Covered	T20,T71,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T26,T45
0	1	Covered	T11,T26,T45
1	0	Covered	T249

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T26,T45
1	-	Covered	T11,T26,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T11,T26
DetectSt	168	Covered	T25,T11,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T26,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T11,T26
DebounceSt->IdleSt	163	Covered	T20,T58
DetectSt->IdleSt	186	Covered	T25,T20,T71
DetectSt->StableSt	191	Covered	T11,T26,T45
IdleSt->DebounceSt	148	Covered	T25,T11,T26
StableSt->IdleSt	206	Covered	T11,T26,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T11,T26
0	1	Covered	T25,T11,T26
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T11,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T11,T26
IdleSt	0	-	-	-	-	-	-	Covered	T25,T11,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T11,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T11,T26
DetectSt	-	-	-	-	1	-	-	Covered	T25,T20,T71
DetectSt	-	-	-	-	0	1	-	Covered	T11,T26,T45
DetectSt	-	-	-	-	0	0	-	Covered	T25,T11,T26
StableSt	-	-	-	-	-	-	1	Covered	T11,T26,T45
StableSt	-	-	-	-	-	-	0	Covered	T11,T26,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	3268	0	0
CntIncr_A	9484281	115425	0	0
CntNoWrap_A	9484281	8835550	0	0
DetectStDropOut_A	9484281	534	0	0
DetectedOut_A	9484281	75971	0	0
DetectedPulseOut_A	9484281	784	0	0
DisabledIdleSt_A	9484281	8386758	0	0
DisabledNoDetection_A	9484281	8388851	0	0
EnterDebounceSt_A	9484281	1636	0	0
EnterDetectSt_A	9484281	1632	0	0
EnterStableSt_A	9484281	784	0	0
PulseIsPulse_A	9484281	784	0	0
StayInStableSt	9484281	75080	0	0
gen_high_event_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	676	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	3268	0	0
T10	5401	0	0	0
T11	0	12	0	0
T20	0	16	0	0
T25	5120	22	0	0
T26	0	26	0	0
T43	0	54	0	0
T44	0	40	0	0
T45	0	18	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	56	0	0
T72	0	46	0	0
T73	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	115425	0	0
T10	5401	0	0	0
T11	0	426	0	0
T20	0	596	0	0
T25	5120	543	0	0
T26	0	819	0	0
T43	0	7344	0	0
T44	0	1300	0	0
T45	0	540	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	1896	0	0
T72	0	1279	0	0
T73	0	1318	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8835550	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	534	0	0
T10	5401	0	0	0
T20	0	1	0	0
T25	5120	11	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	16	0	0
T72	0	17	0	0
T73	0	28	0	0
T92	0	15	0	0
T93	0	28	0	0
T94	0	4	0	0
T96	0	19	0	0
T250	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	75971	0	0
T11	26257	719	0	0
T12	952	0	0	0
T20	0	461	0	0
T26	14102	663	0	0
T43	0	6951	0	0
T44	0	1175	0	0
T45	17955	1559	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	357	0	0
T200	0	725	0	0
T237	0	2793	0	0
T238	0	3326	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	784	0	0
T11	26257	6	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	13	0	0
T43	0	27	0	0
T44	0	20	0	0
T45	17955	9	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	11	0	0
T200	0	12	0	0
T237	0	23	0	0
T238	0	32	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8386758	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8388851	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1636	0	0
T10	5401	0	0	0
T11	0	6	0	0
T20	0	9	0	0
T25	5120	11	0	0
T26	0	13	0	0
T43	0	27	0	0
T44	0	20	0	0
T45	0	9	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	28	0	0
T72	0	23	0	0
T73	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1632	0	0
T10	5401	0	0	0
T11	0	6	0	0
T20	0	7	0	0
T25	5120	11	0	0
T26	0	13	0	0
T43	0	27	0	0
T44	0	20	0	0
T45	0	9	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	28	0	0
T72	0	23	0	0
T73	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	784	0	0
T11	26257	6	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	13	0	0
T43	0	27	0	0
T44	0	20	0	0
T45	17955	9	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	11	0	0
T200	0	12	0	0
T237	0	23	0	0
T238	0	32	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	784	0	0
T11	26257	6	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	13	0	0
T43	0	27	0	0
T44	0	20	0	0
T45	17955	9	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	11	0	0
T200	0	12	0	0
T237	0	23	0	0
T238	0	32	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	75080	0	0
T11	26257	711	0	0
T12	952	0	0	0
T20	0	456	0	0
T26	14102	647	0	0
T43	0	6920	0	0
T44	0	1155	0	0
T45	17955	1545	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	346	0	0
T200	0	710	0	0
T237	0	2764	0	0
T238	0	3285	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	676	0	0
T11	26257	4	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	10	0	0
T43	0	23	0	0
T44	0	20	0	0
T45	17955	4	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T110	425	0	0	0
T111	401	0	0	0
T129	0	11	0	0
T200	0	9	0	0
T237	0	17	0	0
T238	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T25
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T224,T243,T78
1	0	Covered	T20,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
1	0	Covered	T20,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T11
1	-	Covered	T1,T3,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T1,T3,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T11
DebounceSt->IdleSt	163	Covered	T1,T3,T20
DetectSt->IdleSt	186	Covered	T20,T224,T243
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T1,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T20,T224,T243
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	800	0	0
CntIncr_A	9484281	49650	0	0
CntNoWrap_A	9484281	8838018	0	0
DetectStDropOut_A	9484281	65	0	0
DetectedOut_A	9484281	13960	0	0
DetectedPulseOut_A	9484281	311	0	0
DisabledIdleSt_A	9484281	8472696	0	0
DisabledNoDetection_A	9484281	8474337	0	0
EnterDebounceSt_A	9484281	422	0	0
EnterDetectSt_A	9484281	379	0	0
EnterStableSt_A	9484281	311	0	0
PulseIsPulse_A	9484281	311	0	0
StayInStableSt	9484281	13617	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	276	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	800	0	0
T1	42319	13	0	0
T2	692	0	0	0
T3	39847	25	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	4	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	8	0	0
T26	0	4	0	0
T33	0	6	0	0
T45	0	10	0	0
T59	0	11	0	0
T91	0	21	0	0
T108	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	49650	0	0
T1	42319	555	0	0
T2	692	0	0	0
T3	39847	1275	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	138	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	311	0	0
T26	0	58	0	0
T33	0	483	0	0
T45	0	290	0	0
T59	0	821	0	0
T91	0	1470	0	0
T108	0	120	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838018	0	0
T1	42319	39826	0	0
T2	692	291	0	0
T3	39847	39318	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	65	0	0
T74	2635	0	0	0
T75	22377	0	0	0
T78	0	2	0	0
T86	656	0	0	0
T88	0	1	0	0
T99	0	3	0	0
T101	0	7	0	0
T109	719	0	0	0
T140	2684	0	0	0
T188	497	0	0	0
T189	491	0	0	0
T224	18485	3	0	0
T225	490	0	0	0
T226	405	0	0	0
T243	0	3	0	0
T244	0	1	0	0
T251	0	8	0	0
T252	0	5	0	0
T253	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	13960	0	0
T1	42319	66	0	0
T2	692	0	0	0
T3	39847	85	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	162	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	80	0	0
T26	0	135	0	0
T33	0	136	0	0
T45	0	473	0	0
T59	0	297	0	0
T91	0	106	0	0
T108	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	311	0	0
T1	42319	6	0	0
T2	692	0	0	0
T3	39847	11	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	2	0	0
T33	0	3	0	0
T45	0	5	0	0
T59	0	5	0	0
T91	0	10	0	0
T108	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8472696	0	0
T1	42319	30451	0	0
T2	692	291	0	0
T3	39847	32233	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8474337	0	0
T1	42319	30454	0	0
T2	692	292	0	0
T3	39847	32233	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	422	0	0
T1	42319	7	0	0
T2	692	0	0	0
T3	39847	14	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	5	0	0
T26	0	2	0	0
T33	0	3	0	0
T45	0	5	0	0
T59	0	6	0	0
T91	0	11	0	0
T108	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	379	0	0
T1	42319	6	0	0
T2	692	0	0	0
T3	39847	11	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	3	0	0
T26	0	2	0	0
T33	0	3	0	0
T45	0	5	0	0
T59	0	5	0	0
T91	0	10	0	0
T108	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	311	0	0
T1	42319	6	0	0
T2	692	0	0	0
T3	39847	11	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	2	0	0
T33	0	3	0	0
T45	0	5	0	0
T59	0	5	0	0
T91	0	10	0	0
T108	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	311	0	0
T1	42319	6	0	0
T2	692	0	0	0
T3	39847	11	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	2	0	0
T33	0	3	0	0
T45	0	5	0	0
T59	0	5	0	0
T91	0	10	0	0
T108	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	13617	0	0
T1	42319	60	0	0
T2	692	0	0	0
T3	39847	74	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	160	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	79	0	0
T26	0	133	0	0
T33	0	133	0	0
T45	0	463	0	0
T59	0	292	0	0
T91	0	96	0	0
T108	0	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	276	0	0
T1	42319	6	0	0
T2	692	0	0	0
T3	39847	11	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T11	0	2	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T26	0	2	0	0
T33	0	3	0	0
T43	0	4	0	0
T59	0	5	0	0
T91	0	10	0	0
T108	0	2	0	0
T242	0	2	0	0