Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T11,T26
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T25,T11,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T11,T26
1	0	Covered	T11,T26,T45
1	1	Covered	T25,T11,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T11,T26
0	1	Covered	T25,T45,T73
1	0	Covered	T45,T95,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T26,T20
0	1	Covered	T11,T26,T20
1	0	Covered	T254,T255,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T26,T20
1	-	Covered	T11,T26,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T11,T26
DetectSt	168	Covered	T25,T11,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T26,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T11,T26
DebounceSt->IdleSt	163	Covered	T20,T58
DetectSt->IdleSt	186	Covered	T25,T45,T73
DetectSt->StableSt	191	Covered	T11,T26,T20
IdleSt->DebounceSt	148	Covered	T25,T11,T26
StableSt->IdleSt	206	Covered	T11,T26,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T11,T26
0	1	Covered	T25,T11,T26
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T11,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T11,T26
IdleSt	0	-	-	-	-	-	-	Covered	T25,T11,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T11,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T11,T26
DetectSt	-	-	-	-	1	-	-	Covered	T25,T45,T73
DetectSt	-	-	-	-	0	1	-	Covered	T11,T26,T20
DetectSt	-	-	-	-	0	0	-	Covered	T25,T11,T26
StableSt	-	-	-	-	-	-	1	Covered	T11,T26,T20
StableSt	-	-	-	-	-	-	0	Covered	T11,T26,T20
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	3024	0	0
CntIncr_A	9484281	98890	0	0
CntNoWrap_A	9484281	8835794	0	0
DetectStDropOut_A	9484281	460	0	0
DetectedOut_A	9484281	73193	0	0
DetectedPulseOut_A	9484281	878	0	0
DisabledIdleSt_A	9484281	8385123	0	0
DisabledNoDetection_A	9484281	8387220	0	0
EnterDebounceSt_A	9484281	1515	0	0
EnterDetectSt_A	9484281	1509	0	0
EnterStableSt_A	9484281	878	0	0
PulseIsPulse_A	9484281	878	0	0
StayInStableSt	9484281	72212	0	0
gen_high_event_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	761	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	3024	0	0
T10	5401	0	0	0
T11	0	12	0	0
T20	0	14	0	0
T25	5120	30	0	0
T26	0	52	0	0
T43	0	28	0	0
T44	0	16	0	0
T45	0	46	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	44	0	0
T72	0	12	0	0
T73	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	98890	0	0
T10	5401	0	0	0
T11	0	504	0	0
T20	0	473	0	0
T25	5120	742	0	0
T26	0	1300	0	0
T43	0	3612	0	0
T44	0	568	0	0
T45	0	1750	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	1320	0	0
T72	0	294	0	0
T73	0	1123	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8835794	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	460	0	0
T10	5401	0	0	0
T25	5120	15	0	0
T45	0	18	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T73	0	24	0	0
T92	0	26	0	0
T93	0	22	0	0
T94	0	10	0	0
T95	0	13	0	0
T96	0	5	0	0
T220	0	1	0	0
T256	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	73193	0	0
T11	26257	641	0	0
T12	952	0	0	0
T20	0	385	0	0
T26	14102	1983	0	0
T43	0	4075	0	0
T44	0	419	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T71	0	2213	0	0
T72	0	1769	0	0
T110	425	0	0	0
T111	401	0	0	0
T237	0	1210	0	0
T238	0	1956	0	0
T239	0	974	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	878	0	0
T11	26257	6	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	26	0	0
T43	0	14	0	0
T44	0	8	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T71	0	22	0	0
T72	0	6	0	0
T110	425	0	0	0
T111	401	0	0	0
T237	0	18	0	0
T238	0	15	0	0
T239	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8385123	0	0
T1	42319	39839	0	0
T2	692	291	0	0
T3	39847	39343	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8387220	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1515	0	0
T10	5401	0	0	0
T11	0	6	0	0
T20	0	9	0	0
T25	5120	15	0	0
T26	0	26	0	0
T43	0	14	0	0
T44	0	8	0	0
T45	0	23	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	22	0	0
T72	0	6	0	0
T73	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	1509	0	0
T10	5401	0	0	0
T11	0	6	0	0
T20	0	5	0	0
T25	5120	15	0	0
T26	0	26	0	0
T43	0	14	0	0
T44	0	8	0	0
T45	0	23	0	0
T50	4442	0	0	0
T51	527	0	0	0
T52	422	0	0	0
T53	425	0	0	0
T54	502	0	0	0
T55	522	0	0	0
T56	426	0	0	0
T57	502	0	0	0
T71	0	22	0	0
T72	0	6	0	0
T73	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	878	0	0
T11	26257	6	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	26	0	0
T43	0	14	0	0
T44	0	8	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T71	0	22	0	0
T72	0	6	0	0
T110	425	0	0	0
T111	401	0	0	0
T237	0	18	0	0
T238	0	15	0	0
T239	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	878	0	0
T11	26257	6	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	26	0	0
T43	0	14	0	0
T44	0	8	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T71	0	22	0	0
T72	0	6	0	0
T110	425	0	0	0
T111	401	0	0	0
T237	0	18	0	0
T238	0	15	0	0
T239	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	72212	0	0
T11	26257	633	0	0
T12	952	0	0	0
T20	0	380	0	0
T26	14102	1954	0	0
T43	0	4058	0	0
T44	0	411	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T71	0	2187	0	0
T72	0	1762	0	0
T110	425	0	0	0
T111	401	0	0	0
T237	0	1187	0	0
T238	0	1936	0	0
T239	0	960	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	761	0	0
T11	26257	4	0	0
T12	952	0	0	0
T20	0	5	0	0
T26	14102	23	0	0
T43	0	11	0	0
T44	0	8	0	0
T45	17955	0	0	0
T60	1010	0	0	0
T61	904	0	0	0
T64	443	0	0	0
T70	523	0	0	0
T71	0	18	0	0
T72	0	5	0	0
T110	425	0	0	0
T111	401	0	0	0
T237	0	13	0	0
T238	0	10	0	0
T239	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T25
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T3,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T3,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T26
0	1	Covered	T1,T108,T34
1	0	Covered	T20,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T26
0	1	Covered	T1,T3,T26
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T26
1	-	Covered	T1,T3,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T26
DetectSt	168	Covered	T1,T3,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T3,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T26
DebounceSt->IdleSt	163	Covered	T3,T20,T59
DetectSt->IdleSt	186	Covered	T1,T20,T108
DetectSt->StableSt	191	Covered	T1,T3,T26
IdleSt->DebounceSt	148	Covered	T1,T3,T26
StableSt->IdleSt	206	Covered	T1,T3,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T26
0	1	Covered	T1,T3,T26
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T26
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T20,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T59,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T26
DetectSt	-	-	-	-	1	-	-	Covered	T1,T20,T108
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T26
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T26
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9484281	740	0	0
CntIncr_A	9484281	39695	0	0
CntNoWrap_A	9484281	8838078	0	0
DetectStDropOut_A	9484281	30	0	0
DetectedOut_A	9484281	13968	0	0
DetectedPulseOut_A	9484281	317	0	0
DisabledIdleSt_A	9484281	8475451	0	0
DisabledNoDetection_A	9484281	8477100	0	0
EnterDebounceSt_A	9484281	390	0	0
EnterDetectSt_A	9484281	351	0	0
EnterStableSt_A	9484281	317	0	0
PulseIsPulse_A	9484281	317	0	0
StayInStableSt	9484281	13626	0	0
gen_high_level_sva.HighLevelEvent_A	9484281	8841110	0	0
gen_not_sticky_sva.StableStDropOut_A	9484281	290	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	740	0	0
T1	42319	10	0	0
T2	692	0	0	0
T3	39847	20	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	8	0	0
T26	0	10	0	0
T30	0	2	0	0
T33	0	4	0	0
T34	0	3	0	0
T59	0	11	0	0
T91	0	8	0	0
T108	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	39695	0	0
T1	42319	400	0	0
T2	692	0	0	0
T3	39847	629	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	235	0	0
T26	0	255	0	0
T30	0	80	0	0
T33	0	364	0	0
T34	0	229	0	0
T59	0	796	0	0
T91	0	312	0	0
T108	0	226	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8838078	0	0
T1	42319	39829	0	0
T2	692	291	0	0
T3	39847	39323	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	30	0	0
T1	42319	1	0	0
T2	692	0	0	0
T3	39847	0	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T34	0	1	0	0
T80	0	1	0	0
T84	0	2	0	0
T101	0	2	0	0
T108	0	2	0	0
T243	0	3	0	0
T257	0	2	0	0
T258	0	12	0	0
T259	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	13968	0	0
T1	42319	97	0	0
T2	692	0	0	0
T3	39847	465	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	80	0	0
T26	0	230	0	0
T30	0	78	0	0
T33	0	48	0	0
T43	0	237	0	0
T59	0	323	0	0
T71	0	217	0	0
T91	0	291	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	317	0	0
T1	42319	4	0	0
T2	692	0	0	0
T3	39847	9	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	5	0	0
T30	0	1	0	0
T33	0	2	0	0
T43	0	3	0	0
T59	0	5	0	0
T71	0	4	0	0
T91	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8475451	0	0
T1	42319	30451	0	0
T2	692	291	0	0
T3	39847	32233	0	0
T4	662	261	0	0
T5	758	357	0	0
T6	497	96	0	0
T7	480	79	0	0
T13	705	304	0	0
T14	714	313	0	0
T15	3975	833	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8477100	0	0
T1	42319	30454	0	0
T2	692	292	0	0
T3	39847	32233	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	390	0	0
T1	42319	5	0	0
T2	692	0	0	0
T3	39847	11	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	5	0	0
T26	0	5	0	0
T30	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T59	0	6	0	0
T91	0	4	0	0
T108	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	351	0	0
T1	42319	5	0	0
T2	692	0	0	0
T3	39847	9	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	3	0	0
T26	0	5	0	0
T30	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T59	0	5	0	0
T91	0	4	0	0
T108	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	317	0	0
T1	42319	4	0	0
T2	692	0	0	0
T3	39847	9	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	5	0	0
T30	0	1	0	0
T33	0	2	0	0
T43	0	3	0	0
T59	0	5	0	0
T71	0	4	0	0
T91	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	317	0	0
T1	42319	4	0	0
T2	692	0	0	0
T3	39847	9	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	1	0	0
T26	0	5	0	0
T30	0	1	0	0
T33	0	2	0	0
T43	0	3	0	0
T59	0	5	0	0
T71	0	4	0	0
T91	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	13626	0	0
T1	42319	93	0	0
T2	692	0	0	0
T3	39847	456	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T20	0	79	0	0
T26	0	225	0	0
T30	0	77	0	0
T33	0	46	0	0
T43	0	234	0	0
T59	0	318	0	0
T71	0	209	0	0
T91	0	287	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	8841110	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9484281	290	0	0
T1	42319	4	0	0
T2	692	0	0	0
T3	39847	9	0	0
T4	662	0	0	0
T6	497	0	0	0
T7	480	0	0	0
T13	705	0	0	0
T14	714	0	0	0
T15	3975	0	0	0
T16	60186	0	0	0
T26	0	5	0	0
T30	0	1	0	0
T33	0	2	0	0
T41	0	1	0	0
T43	0	3	0	0
T59	0	5	0	0
T91	0	4	0	0
T242	0	1	0	0