Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1514892865	10226	0	0
auto_block_debounce_ctl_rd_A	1514892865	1597	0	0
auto_block_out_ctl_rd_A	1514892865	2418	0	0
com_det_ctl_0_rd_A	1514892865	3723	0	0
com_det_ctl_1_rd_A	1514892865	3945	0	0
com_det_ctl_2_rd_A	1514892865	3853	0	0
com_det_ctl_3_rd_A	1514892865	3810	0	0
com_out_ctl_0_rd_A	1514892865	4344	0	0
com_out_ctl_1_rd_A	1514892865	4432	0	0
com_out_ctl_2_rd_A	1514892865	4449	0	0
com_out_ctl_3_rd_A	1514892865	4235	0	0
com_pre_det_ctl_0_rd_A	1514892865	1191	0	0
com_pre_det_ctl_1_rd_A	1514892865	1140	0	0
com_pre_det_ctl_2_rd_A	1514892865	1335	0	0
com_pre_det_ctl_3_rd_A	1514892865	1188	0	0
com_pre_sel_ctl_0_rd_A	1514892865	4506	0	0
com_pre_sel_ctl_1_rd_A	1514892865	4490	0	0
com_pre_sel_ctl_2_rd_A	1514892865	4740	0	0
com_pre_sel_ctl_3_rd_A	1514892865	4734	0	0
com_sel_ctl_0_rd_A	1514892865	4585	0	0
com_sel_ctl_1_rd_A	1514892865	4395	0	0
com_sel_ctl_2_rd_A	1514892865	4463	0	0
com_sel_ctl_3_rd_A	1514892865	4812	0	0
ec_rst_ctl_rd_A	1514892865	2573	0	0
intr_enable_rd_A	1514892865	1525	0	0
key_intr_ctl_rd_A	1514892865	3449	0	0
key_intr_debounce_ctl_rd_A	1514892865	1364	0	0
key_invert_ctl_rd_A	1514892865	4350	0	0
pin_allowed_ctl_rd_A	1514892865	4858	0	0
pin_out_ctl_rd_A	1514892865	3597	0	0
pin_out_value_rd_A	1514892865	3505	0	0
regwen_rd_A	1514892865	1365	0	0
ulp_ac_debounce_ctl_rd_A	1514892865	1319	0	0
ulp_ctl_rd_A	1514892865	1337	0	0
ulp_lid_debounce_ctl_rd_A	1514892865	1361	0	0
ulp_pwrb_debounce_ctl_rd_A	1514892865	1378	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	10226	0	0
T4	159212	0	0	0
T8	288096	0	0	0
T9	217939	0	0	0
T10	0	10	0	0
T15	198768	9	0	0
T16	144450	0	0	0
T22	246994	0	0	0
T24	260974	0	0	0
T25	614518	0	0	0
T30	0	26	0	0
T36	0	7	0	0
T37	0	6	0	0
T38	0	2	0	0
T41	0	7	0	0
T50	222125	0	0	0
T69	867109	0	0	0
T75	0	5	0	0
T76	0	7	0	0
T166	0	31	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1597	0	0
T20	398371	0	0	0
T31	428951	0	0	0
T36	394701	24	0	0
T38	0	15	0	0
T39	102143	0	0	0
T47	359700	2	0	0
T48	30541	8	0	0
T66	240610	0	0	0
T74	0	11	0	0
T76	0	11	0	0
T164	50955	0	0	0
T182	248355	0	0	0
T183	52590	0	0	0
T207	0	22	0	0
T287	0	10	0	0
T288	0	15	0	0
T289	0	5	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	2418	0	0
T20	398371	0	0	0
T31	428951	0	0	0
T36	394701	34	0	0
T38	0	5	0	0
T39	102143	0	0	0
T47	359700	1	0	0
T48	30541	9	0	0
T66	240610	0	0	0
T74	0	2	0	0
T76	0	12	0	0
T164	50955	0	0	0
T182	248355	0	0	0
T183	52590	0	0	0
T207	0	14	0	0
T287	0	13	0	0
T288	0	23	0	0
T290	0	4	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	3723	0	0
T1	211597	128	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	32	0	0
T33	0	60	0	0
T36	0	15	0	0
T38	0	12	0	0
T43	0	24	0	0
T45	0	43	0	0
T59	0	64	0	0
T75	0	5	0	0
T108	0	34	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	3945	0	0
T1	211597	146	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	34	0	0
T33	0	58	0	0
T36	0	20	0	0
T38	0	14	0	0
T43	0	44	0	0
T45	0	48	0	0
T59	0	80	0	0
T75	0	1	0	0
T108	0	33	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	3853	0	0
T1	211597	134	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	45	0	0
T33	0	53	0	0
T36	0	15	0	0
T38	0	10	0	0
T43	0	53	0	0
T45	0	37	0	0
T59	0	75	0	0
T76	0	34	0	0
T108	0	35	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	3810	0	0
T1	211597	155	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	41	0	0
T33	0	47	0	0
T36	0	9	0	0
T38	0	19	0	0
T43	0	31	0	0
T45	0	24	0	0
T59	0	67	0	0
T75	0	16	0	0
T108	0	41	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4344	0	0
T1	211597	139	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	22	0	0
T33	0	38	0	0
T36	0	25	0	0
T38	0	15	0	0
T43	0	34	0	0
T45	0	33	0	0
T59	0	70	0	0
T75	0	6	0	0
T108	0	31	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4432	0	0
T1	211597	146	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	27	0	0
T33	0	37	0	0
T36	0	18	0	0
T38	0	12	0	0
T43	0	46	0	0
T45	0	37	0	0
T59	0	67	0	0
T75	0	26	0	0
T108	0	44	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4449	0	0
T1	211597	134	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	41	0	0
T33	0	67	0	0
T36	0	4	0	0
T38	0	3	0	0
T43	0	29	0	0
T45	0	53	0	0
T59	0	57	0	0
T75	0	10	0	0
T108	0	49	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4235	0	0
T1	211597	123	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	24	0	0
T33	0	30	0	0
T36	0	25	0	0
T38	0	13	0	0
T43	0	45	0	0
T45	0	35	0	0
T59	0	51	0	0
T75	0	9	0	0
T108	0	47	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1191	0	0
T21	225620	0	0	0
T36	394701	10	0	0
T38	0	15	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	0	0	0
T67	59733	0	0	0
T76	0	21	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T207	0	24	0	0
T290	0	3	0	0
T291	0	1	0	0
T292	0	11	0	0
T293	0	14	0	0
T294	0	35	0	0
T295	0	22	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1140	0	0
T21	225620	0	0	0
T36	394701	11	0	0
T38	0	12	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	0	0	0
T67	59733	0	0	0
T75	0	6	0	0
T76	0	9	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T207	0	14	0	0
T290	0	9	0	0
T291	0	17	0	0
T292	0	13	0	0
T293	0	8	0	0
T294	0	20	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1335	0	0
T21	225620	0	0	0
T36	394701	5	0	0
T38	0	9	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	0	0	0
T67	59733	0	0	0
T75	0	6	0	0
T76	0	30	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T170	0	6	0	0
T207	0	24	0	0
T290	0	7	0	0
T291	0	4	0	0
T292	0	4	0	0
T293	0	17	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1188	0	0
T21	225620	0	0	0
T36	394701	11	0	0
T38	0	5	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	0	0	0
T67	59733	0	0	0
T75	0	6	0	0
T76	0	15	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T170	0	1	0	0
T207	0	25	0	0
T290	0	10	0	0
T291	0	11	0	0
T292	0	14	0	0
T293	0	21	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4506	0	0
T1	211597	145	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	48	0	0
T33	0	51	0	0
T36	0	13	0	0
T38	0	11	0	0
T43	0	14	0	0
T45	0	38	0	0
T59	0	72	0	0
T75	0	1	0	0
T108	0	60	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4490	0	0
T1	211597	139	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	33	0	0
T33	0	34	0	0
T36	0	20	0	0
T38	0	5	0	0
T43	0	28	0	0
T45	0	16	0	0
T59	0	54	0	0
T76	0	46	0	0
T108	0	36	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4740	0	0
T1	211597	123	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	38	0	0
T33	0	46	0	0
T36	0	26	0	0
T38	0	14	0	0
T43	0	69	0	0
T45	0	40	0	0
T59	0	77	0	0
T75	0	14	0	0
T108	0	36	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4734	0	0
T1	211597	134	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	54	0	0
T33	0	49	0	0
T36	0	21	0	0
T38	0	12	0	0
T43	0	49	0	0
T45	0	26	0	0
T59	0	83	0	0
T75	0	3	0	0
T108	0	42	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4585	0	0
T1	211597	165	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	29	0	0
T33	0	51	0	0
T36	0	17	0	0
T38	0	15	0	0
T43	0	29	0	0
T45	0	31	0	0
T59	0	55	0	0
T75	0	12	0	0
T108	0	29	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4395	0	0
T1	211597	116	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	48	0	0
T33	0	28	0	0
T36	0	21	0	0
T38	0	13	0	0
T43	0	29	0	0
T45	0	43	0	0
T59	0	78	0	0
T75	0	4	0	0
T108	0	38	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4463	0	0
T1	211597	137	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	16	0	0
T33	0	50	0	0
T36	0	20	0	0
T38	0	10	0	0
T43	0	34	0	0
T45	0	31	0	0
T59	0	59	0	0
T76	0	54	0	0
T108	0	52	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4812	0	0
T1	211597	126	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	38	0	0
T33	0	54	0	0
T36	0	12	0	0
T38	0	10	0	0
T43	0	42	0	0
T45	0	20	0	0
T59	0	64	0	0
T75	0	8	0	0
T108	0	58	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	2573	0	0
T1	211597	53	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T26	0	5	0	0
T33	0	11	0	0
T36	0	5	0	0
T38	0	12	0	0
T43	0	12	0	0
T45	0	17	0	0
T59	0	52	0	0
T75	0	14	0	0
T108	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1525	0	0
T21	225620	0	0	0
T36	394701	16	0	0
T38	0	26	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	0	0	0
T67	59733	0	0	0
T75	0	5	0	0
T76	0	25	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T207	0	15	0	0
T289	0	20	0	0
T290	0	3	0	0
T291	0	7	0	0
T292	0	19	0	0
T293	0	24	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	3449	0	0
T8	288096	1	0	0
T9	217939	0	0	0
T10	212274	0	0	0
T24	260974	0	0	0
T25	614518	0	0	0
T36	0	19	0	0
T38	0	10	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T69	867109	0	0	0
T74	0	2	0	0
T75	0	3	0	0
T76	0	20	0	0
T136	0	1	0	0
T193	0	6	0	0
T207	0	32	0	0
T290	0	7	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1364	0	0
T21	225620	0	0	0
T36	394701	8	0	0
T38	0	10	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	0	0	0
T67	59733	0	0	0
T75	0	7	0	0
T76	0	30	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T170	0	3	0	0
T207	0	22	0	0
T290	0	1	0	0
T291	0	4	0	0
T292	0	22	0	0
T293	0	18	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4350	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	53	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T22	246994	0	0	0
T36	0	14	0	0
T38	0	13	0	0
T67	0	36	0	0
T68	0	61	0	0
T75	0	51	0	0
T76	0	69	0	0
T188	0	63	0	0
T290	0	63	0	0
T296	0	57	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	4858	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T26	239741	0	0	0
T36	0	10	0	0
T38	0	6	0	0
T45	897741	0	0	0
T57	248603	59	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T64	201956	0	0	0
T75	0	16	0	0
T76	0	236	0	0
T110	44707	0	0	0
T111	192941	0	0	0
T207	0	20	0	0
T291	0	17	0	0
T297	0	65	0	0
T298	0	66	0	0
T299	0	21	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	3597	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T26	239741	0	0	0
T36	0	7	0	0
T38	0	14	0	0
T45	897741	0	0	0
T57	248603	87	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T64	201956	0	0	0
T75	0	4	0	0
T76	0	242	0	0
T110	44707	0	0	0
T111	192941	0	0	0
T207	0	18	0	0
T290	0	8	0	0
T291	0	2	0	0
T297	0	64	0	0
T298	0	45	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	3505	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T26	239741	0	0	0
T36	0	7	0	0
T38	0	5	0	0
T45	897741	0	0	0
T57	248603	68	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T64	201956	0	0	0
T76	0	216	0	0
T110	44707	0	0	0
T111	192941	0	0	0
T207	0	16	0	0
T290	0	3	0	0
T291	0	14	0	0
T297	0	65	0	0
T298	0	51	0	0
T299	0	58	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1365	0	0
T21	225620	0	0	0
T36	394701	13	0	0
T38	0	13	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	0	0	0
T67	59733	0	0	0
T75	0	7	0	0
T76	0	31	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T170	0	6	0	0
T207	0	11	0	0
T290	0	7	0	0
T291	0	3	0	0
T292	0	17	0	0
T293	0	8	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1319	0	0
T21	225620	0	0	0
T36	394701	5	0	0
T38	0	8	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	10	0	0
T67	59733	0	0	0
T74	0	1	0	0
T75	0	12	0	0
T76	0	42	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T207	0	16	0	0
T290	0	3	0	0
T300	0	1	0	0
T301	0	8	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1337	0	0
T21	225620	0	0	0
T36	394701	6	0	0
T38	0	13	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	5	0	0
T67	59733	0	0	0
T75	0	8	0	0
T76	0	27	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T207	0	16	0	0
T290	0	16	0	0
T300	0	1	0	0
T301	0	6	0	0
T302	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1361	0	0
T21	225620	0	0	0
T36	394701	4	0	0
T38	0	6	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	1	0	0
T67	59733	0	0	0
T75	0	10	0	0
T76	0	19	0	0
T87	0	6	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T207	0	18	0	0
T290	0	14	0	0
T301	0	4	0	0
T302	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1378	0	0
T21	225620	0	0	0
T36	394701	8	0	0
T38	0	19	0	0
T48	30541	0	0	0
T49	79813	0	0	0
T62	53438	10	0	0
T67	59733	0	0	0
T74	0	1	0	0
T75	0	10	0	0
T76	0	38	0	0
T104	63207	0	0	0
T105	101017	0	0	0
T106	208937	0	0	0
T107	182746	0	0	0
T112	0	8	0	0
T207	0	10	0	0
T290	0	11	0	0
T301	0	3	0	0