Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T6,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T3
1	1	Covered	T1,T6,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T6,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T3
1	1	Covered	T1,T6,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T3,T10

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T10,T20,T21
1	-	Covered	T1,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	107421837	0	0
DstReqKnown_A	330874706	302514320	0	0
SrcAckBusyChk_A	2147483647	112670	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107421837	0	0
T1	2115970	213059	0	0
T2	716500	0	0	0
T3	4781630	52872	0	0
T4	1592120	0	0	0
T5	83426	1387	0	0
T6	646390	0	0	0
T7	2402160	2988	0	0
T10	212274	5136	0	0
T11	0	120502	0	0
T13	3526080	11432	0	0
T14	893930	0	0	0
T15	1987680	0	0	0
T16	1155600	7419	0	0
T20	0	111207	0	0
T23	0	5993	0	0
T25	614518	3780	0	0
T26	0	19061	0	0
T30	0	5640	0	0
T33	0	5876	0	0
T36	0	22938	0	0
T43	0	9903	0	0
T45	0	93654	0	0
T46	0	9163	0	0
T47	0	13388	0	0
T48	0	942	0	0
T49	0	2878	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330874706	302514320	0	0
T1	1438846	1355138	0	0
T2	23528	9928	0	0
T3	1354798	1338206	0	0
T4	22508	8908	0	0
T5	25772	12172	0	0
T6	16898	3298	0	0
T7	16320	2720	0	0
T13	23970	10370	0	0
T14	24276	10676	0	0
T15	135150	28628	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	112670	0	0
T1	2115970	122	0	0
T2	716500	0	0	0
T3	4781630	128	0	0
T4	1592120	0	0	0
T5	83426	7	0	0
T6	646390	0	0	0
T7	2402160	2	0	0
T10	212274	4	0	0
T11	0	72	0	0
T13	3526080	7	0	0
T14	893930	0	0	0
T15	1987680	0	0	0
T16	1155600	9	0	0
T20	0	66	0	0
T23	0	7	0	0
T25	614518	9	0	0
T26	0	36	0	0
T30	0	8	0	0
T33	0	80	0	0
T36	0	13	0	0
T43	0	6	0	0
T45	0	54	0	0
T46	0	8	0	0
T47	0	8	0	0
T48	0	8	0	0
T49	0	6	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7194298	7183588	0	0
T2	2436100	2433754	0	0
T3	16257542	16221502	0	0
T4	5413208	5410760	0	0
T5	1418242	1416032	0	0
T6	2197726	2194632	0	0
T7	8167344	8164794	0	0
T13	11988672	11985306	0	0
T14	3039362	3037084	0	0
T15	6758112	6718332	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T3,T10

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T20,T58,T27
1	-	Covered	T1,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T10
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T10
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	977968	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1095	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	977968	0	0
T1	211597	16265	0	0
T2	71650	0	0	0
T3	478163	6307	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T10	0	1283	0	0
T11	0	12336	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	1260	0	0
T21	0	1932	0	0
T26	0	3640	0	0
T30	0	717	0	0
T33	0	668	0	0
T59	0	5598	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1095	0	0
T1	211597	9	0	0
T2	71650	0	0	0
T3	478163	15	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T10	0	1	0	0
T11	0	7	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T21	0	1	0	0
T26	0	6	0	0
T30	0	1	0	0
T32	0	3	0	0
T33	0	9	0	0
T59	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1818113	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1905	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1818113	0	0
T1	211597	27003	0	0
T2	71650	0	0	0
T3	478163	6465	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	1491	0	0
T10	0	4277	0	0
T11	0	12828	0	0
T13	352608	0	0	0
T14	89393	481	0	0
T15	198768	1988	0	0
T16	144450	0	0	0
T25	0	432	0	0
T60	0	972	0	0
T61	0	202	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1905	0	0
T1	211597	16	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	1	0	0
T10	0	3	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	1	0	0
T15	198768	1	0	0
T16	144450	0	0	0
T25	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T10,T30,T31

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T10,T30,T31
1	1	Covered	T10,T30,T31

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T10,T30,T31

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T30,T31
1	1	Covered	T10,T30,T31

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T10,T30,T31
0	0	1	Covered	T10,T30,T31
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T10,T30,T31
0	0	1	Covered	T10,T30,T31
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	968501	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	981	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	968501	0	0
T10	212274	1287	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T20	0	1447	0	0
T21	0	3390	0	0
T30	0	716	0	0
T31	0	997	0	0
T32	0	1473	0	0
T37	0	776	0	0
T38	0	129	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T62	0	1321	0	0
T63	0	369	0	0
T64	201956	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	981	0	0
T10	212274	1	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	201956	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T10,T30,T31

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T10,T30,T31
1	1	Covered	T10,T30,T31

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T10,T30,T31

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T30,T31
1	1	Covered	T10,T30,T31

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T10,T30,T31
0	0	1	Covered	T10,T30,T31
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T10,T30,T31
0	0	1	Covered	T10,T30,T31
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	967484	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	978	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	967484	0	0
T10	212274	1285	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T20	0	1439	0	0
T21	0	3386	0	0
T30	0	714	0	0
T31	0	995	0	0
T32	0	1450	0	0
T37	0	763	0	0
T38	0	119	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T62	0	1280	0	0
T63	0	367	0	0
T64	201956	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	978	0	0
T10	212274	1	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	201956	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T10,T30,T31

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T10,T30,T31
1	1	Covered	T10,T30,T31

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T10,T30,T31

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T30,T31
1	1	Covered	T10,T30,T31

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T10,T30,T31
0	0	1	Covered	T10,T30,T31
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T10,T30,T31
0	0	1	Covered	T10,T30,T31
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	914694	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	910	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	914694	0	0
T10	212274	1283	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T20	0	1429	0	0
T21	0	3382	0	0
T30	0	712	0	0
T31	0	993	0	0
T32	0	1428	0	0
T37	0	744	0	0
T38	0	114	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T62	0	1265	0	0
T63	0	365	0	0
T64	201956	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	910	0	0
T10	212274	1	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	201956	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T6,T22,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T6,T22,T23
1	1	Covered	T6,T22,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T6,T22,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T22,T23
1	1	Covered	T6,T22,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T6,T22,T23
0	0	1	Covered	T6,T22,T23
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T6,T22,T23
0	0	1	Covered	T6,T22,T23
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	2581044	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	2884	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	2581044	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	9392	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T22	246994	36007	0	0
T23	0	17047	0	0
T30	0	33611	0	0
T31	0	17753	0	0
T37	0	15826	0	0
T65	0	16752	0	0
T66	0	35898	0	0
T67	0	8285	0	0
T68	0	9006	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	2884	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	20	0	0
T7	240216	0	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T22	246994	20	0	0
T23	0	20	0	0
T30	0	40	0	0
T31	0	20	0	0
T37	0	40	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T6,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T15
1	1	Covered	T1,T6,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T6,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T15
1	1	Covered	T1,T6,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T6,T15
0	0	1	Covered	T1,T6,T15
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T6,T15
0	0	1	Covered	T1,T6,T15
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	5758546	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	6568	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	5758546	0	0
T1	211597	36461	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	369	0	0
T7	240216	0	0	0
T10	0	37393	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	34122	0	0
T16	144450	0	0	0
T22	0	1998	0	0
T24	0	36026	0	0
T51	0	6626	0	0
T54	0	25186	0	0
T55	0	38078	0	0
T69	0	33124	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6568	0	0
T1	211597	20	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	1	0	0
T7	240216	0	0	0
T10	0	24	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	20	0	0
T16	144450	0	0	0
T22	0	1	0	0
T24	0	20	0	0
T51	0	20	0	0
T54	0	20	0	0
T55	0	20	0	0
T69	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T6,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T3
1	1	Covered	T1,T6,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T6,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T3
1	1	Covered	T1,T6,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T6,T3
0	0	1	Covered	T1,T6,T3
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T6,T3
0	0	1	Covered	T1,T6,T3
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	6908307	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	7678	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6908307	0	0
T1	211597	63059	0	0
T2	71650	0	0	0
T3	478163	6815	0	0
T4	159212	0	0	0
T6	64639	377	0	0
T7	240216	1499	0	0
T13	352608	0	0	0
T14	89393	491	0	0
T15	198768	38372	0	0
T16	144450	0	0	0
T22	0	2000	0	0
T24	0	36414	0	0
T25	0	473	0	0
T69	0	33374	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7678	0	0
T1	211597	36	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	1	0	0
T7	240216	1	0	0
T13	352608	0	0	0
T14	89393	1	0	0
T15	198768	22	0	0
T16	144450	0	0	0
T22	0	1	0	0
T24	0	20	0	0
T25	0	1	0	0
T69	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T15,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T15,T24
1	1	Covered	T1,T15,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T15,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T15,T24
1	1	Covered	T1,T15,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T15,T24
0	0	1	Covered	T1,T15,T24
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T15,T24
0	0	1	Covered	T1,T15,T24
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	5745786	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	6524	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	5745786	0	0
T1	211597	36694	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T10	0	37443	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	34244	0	0
T16	144450	0	0	0
T24	0	36228	0	0
T51	0	6666	0	0
T54	0	25331	0	0
T55	0	38213	0	0
T57	0	33356	0	0
T69	0	33237	0	0
T70	0	21856	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6524	0	0
T1	211597	20	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T10	0	24	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	20	0	0
T16	144450	0	0	0
T24	0	20	0	0
T51	0	20	0	0
T54	0	20	0	0
T55	0	20	0	0
T57	0	20	0	0
T69	0	20	0	0
T70	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T2,T4,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T2,T4,T8
1	1	Covered	T2,T4,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T2,T4,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T8
1	1	Covered	T2,T4,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T2,T4,T8
0	0	1	Covered	T2,T4,T8
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T2,T4,T8
0	0	1	Covered	T2,T4,T8
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	981850	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	970	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	981850	0	0
T2	71650	359	0	0
T3	478163	0	0	0
T4	159212	716	0	0
T7	240216	0	0	0
T8	288096	1479	0	0
T9	0	1977	0	0
T12	0	1435	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	47196	0	0
T22	246994	0	0	0
T23	0	716	0	0
T30	0	1673	0	0
T39	0	1430	0	0
T42	0	326	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	970	0	0
T2	71650	1	0	0
T3	478163	0	0	0
T4	159212	1	0	0
T7	240216	0	0	0
T8	288096	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	28	0	0
T22	246994	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1799050	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1902	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1799050	0	0
T1	211597	26836	0	0
T2	71650	357	0	0
T3	478163	6433	0	0
T4	159212	714	0	0
T6	64639	0	0	0
T7	240216	1489	0	0
T8	0	1477	0	0
T9	0	1975	0	0
T10	0	2558	0	0
T11	0	12774	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T25	0	430	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1902	0	0
T1	211597	16	0	0
T2	71650	1	0	0
T3	478163	16	0	0
T4	159212	1	0	0
T6	64639	0	0	0
T7	240216	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T25	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T5,T13,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T13,T16
1	1	Covered	T5,T13,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T5,T13,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T13,T16
1	1	Covered	T5,T13,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T13,T16
0	0	1	Covered	T5,T13,T16
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T13,T16
0	0	1	Covered	T5,T13,T16
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1280885	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1330	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1280885	0	0
T1	211597	0	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T5	41713	812	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	6471	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	0	5033	0	0
T20	0	3384	0	0
T23	0	3359	0	0
T36	0	6687	0	0
T46	0	5773	0	0
T47	0	8629	0	0
T48	0	602	0	0
T49	0	1442	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1330	0	0
T1	211597	0	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T5	41713	4	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	4	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	0	6	0	0
T20	0	2	0	0
T23	0	4	0	0
T36	0	4	0	0
T46	0	5	0	0
T47	0	5	0	0
T48	0	5	0	0
T49	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T5,T13,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T13,T16
1	1	Covered	T5,T13,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T5,T13,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T13,T16
1	1	Covered	T5,T13,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T13,T16
0	0	1	Covered	T5,T13,T16
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T5,T13,T16
0	0	1	Covered	T5,T13,T16
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1132019	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1152	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1132019	0	0
T1	211597	0	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T5	41713	575	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	4961	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	0	2386	0	0
T20	0	1455	0	0
T23	0	2634	0	0
T36	0	5224	0	0
T46	0	3390	0	0
T47	0	4759	0	0
T48	0	340	0	0
T49	0	1436	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1152	0	0
T1	211597	0	0	0
T2	71650	0	0	0
T3	478163	0	0	0
T4	159212	0	0	0
T5	41713	3	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T13	352608	3	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	0	3	0	0
T20	0	1	0	0
T23	0	3	0	0
T36	0	3	0	0
T46	0	3	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	6825542	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	6994	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6825542	0	0
T10	212274	0	0	0
T11	0	109318	0	0
T20	0	18818	0	0
T25	614518	21178	0	0
T26	0	43369	0	0
T43	0	122845	0	0
T44	0	29162	0	0
T45	0	113607	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	66308	0	0
T72	0	23899	0	0
T73	0	37096	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6994	0	0
T10	212274	0	0	0
T11	0	63	0	0
T20	0	11	0	0
T25	614518	51	0	0
T26	0	75	0	0
T43	0	73	0	0
T44	0	70	0	0
T45	0	65	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	77	0	0
T72	0	58	0	0
T73	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	6723313	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	6928	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6723313	0	0
T10	212274	0	0	0
T11	0	142591	0	0
T20	0	18785	0	0
T25	614518	20489	0	0
T26	0	47877	0	0
T43	0	144126	0	0
T44	0	29762	0	0
T45	0	112191	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	65149	0	0
T72	0	23655	0	0
T73	0	36886	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6928	0	0
T10	212274	0	0	0
T11	0	83	0	0
T20	0	11	0	0
T25	614518	51	0	0
T26	0	85	0	0
T43	0	87	0	0
T44	0	72	0	0
T45	0	65	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	77	0	0
T72	0	58	0	0
T73	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	6688155	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	7010	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6688155	0	0
T10	212274	0	0	0
T11	0	131615	0	0
T20	0	18780	0	0
T25	614518	19759	0	0
T26	0	39091	0	0
T43	0	99614	0	0
T44	0	25368	0	0
T45	0	94322	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	63994	0	0
T72	0	23411	0	0
T73	0	36676	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7010	0	0
T10	212274	0	0	0
T11	0	77	0	0
T20	0	11	0	0
T25	614518	51	0	0
T26	0	72	0	0
T43	0	60	0	0
T44	0	62	0	0
T45	0	56	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	77	0	0
T72	0	58	0	0
T73	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	6566601	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	6927	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6566601	0	0
T10	212274	0	0	0
T11	0	130408	0	0
T20	0	18793	0	0
T25	614518	19166	0	0
T26	0	30844	0	0
T43	0	119031	0	0
T44	0	30071	0	0
T45	0	109730	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	45119	0	0
T72	0	20739	0	0
T73	0	36466	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	6927	0	0
T10	212274	0	0	0
T11	0	77	0	0
T20	0	11	0	0
T25	614518	51	0	0
T26	0	59	0	0
T43	0	73	0	0
T44	0	74	0	0
T45	0	65	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	55	0	0
T72	0	52	0	0
T73	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1228300	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1206	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1228300	0	0
T10	212274	0	0	0
T11	0	13893	0	0
T20	0	15357	0	0
T25	614518	468	0	0
T26	0	2326	0	0
T43	0	9903	0	0
T44	0	358	0	0
T45	0	10903	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	4615	0	0
T72	0	716	0	0
T73	0	879	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1206	0	0
T10	212274	0	0	0
T11	0	8	0	0
T20	0	9	0	0
T25	614518	1	0	0
T26	0	4	0	0
T43	0	6	0	0
T44	0	1	0	0
T45	0	6	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	5	0	0
T72	0	2	0	0
T73	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1181621	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1169	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1181621	0	0
T10	212274	0	0	0
T11	0	13593	0	0
T20	0	15319	0	0
T25	614518	417	0	0
T26	0	2161	0	0
T43	0	9619	0	0
T44	0	348	0	0
T45	0	10590	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	4462	0	0
T72	0	696	0	0
T73	0	869	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1169	0	0
T10	212274	0	0	0
T11	0	8	0	0
T20	0	9	0	0
T25	614518	1	0	0
T26	0	4	0	0
T43	0	6	0	0
T44	0	1	0	0
T45	0	6	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	5	0	0
T72	0	2	0	0
T73	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1198665	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1192	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1198665	0	0
T10	212274	0	0	0
T11	0	13355	0	0
T20	0	15337	0	0
T25	614518	383	0	0
T26	0	2000	0	0
T43	0	9330	0	0
T44	0	338	0	0
T45	0	10334	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	4274	0	0
T72	0	676	0	0
T73	0	859	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1192	0	0
T10	212274	0	0	0
T11	0	8	0	0
T20	0	9	0	0
T25	614518	1	0	0
T26	0	4	0	0
T43	0	6	0	0
T44	0	1	0	0
T45	0	6	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	5	0	0
T72	0	2	0	0
T73	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T11,T26
1	1	Covered	T25,T11,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T25,T11,T26
0	0	1	Covered	T25,T11,T26
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1176217	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1201	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1176217	0	0
T10	212274	0	0	0
T11	0	13050	0	0
T20	0	15353	0	0
T25	614518	465	0	0
T26	0	1803	0	0
T43	0	9077	0	0
T44	0	328	0	0
T45	0	10087	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	4096	0	0
T72	0	656	0	0
T73	0	849	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1201	0	0
T10	212274	0	0	0
T11	0	8	0	0
T20	0	9	0	0
T25	614518	1	0	0
T26	0	4	0	0
T43	0	6	0	0
T44	0	1	0	0
T45	0	6	0	0
T50	222125	0	0	0
T51	52763	0	0	0
T52	69705	0	0	0
T53	53185	0	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T71	0	5	0	0
T72	0	2	0	0
T73	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	7497742	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	7638	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7497742	0	0
T1	211597	28908	0	0
T2	71650	0	0	0
T3	478163	6849	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	1497	0	0
T10	0	2574	0	0
T11	0	109530	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T25	0	21478	0	0
T26	0	43967	0	0
T30	0	720	0	0
T33	0	803	0	0
T45	0	114007	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7638	0	0
T1	211597	16	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	1	0	0
T10	0	2	0	0
T11	0	63	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T25	0	51	0	0
T26	0	75	0	0
T30	0	1	0	0
T33	0	10	0	0
T45	0	65	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	7334635	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	7504	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7334635	0	0
T1	211597	27272	0	0
T2	71650	0	0	0
T3	478163	6817	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	143020	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	18631	0	0
T25	0	20780	0	0
T26	0	48571	0	0
T30	0	718	0	0
T33	0	694	0	0
T36	0	1909	0	0
T45	0	112564	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7504	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	83	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	11	0	0
T25	0	51	0	0
T26	0	85	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	65	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	7267520	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	7573	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7267520	0	0
T1	211597	27119	0	0
T2	71650	0	0	0
T3	478163	6785	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	131966	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	18636	0	0
T25	0	20106	0	0
T26	0	39648	0	0
T30	0	716	0	0
T33	0	741	0	0
T36	0	1899	0	0
T45	0	94708	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7573	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	77	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	11	0	0
T25	0	51	0	0
T26	0	72	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	7158546	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	7508	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7158546	0	0
T1	211597	26963	0	0
T2	71650	0	0	0
T3	478163	6753	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	130758	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	18681	0	0
T25	0	19485	0	0
T26	0	31450	0	0
T30	0	714	0	0
T33	0	769	0	0
T36	0	1893	0	0
T45	0	110132	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	7508	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	77	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	11	0	0
T25	0	51	0	0
T26	0	59	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	65	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1761341	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1767	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1761341	0	0
T1	211597	28292	0	0
T2	71650	0	0	0
T3	478163	6721	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	1495	0	0
T10	0	2570	0	0
T11	0	13761	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T25	0	447	0	0
T26	0	2250	0	0
T30	0	712	0	0
T33	0	715	0	0
T45	0	10782	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1767	0	0
T1	211597	16	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	1	0	0
T10	0	2	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T25	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T33	0	10	0	0
T45	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1764012	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1766	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1764012	0	0
T1	211597	26665	0	0
T2	71650	0	0	0
T3	478163	6689	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	13483	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	15164	0	0
T25	0	405	0	0
T26	0	2095	0	0
T30	0	710	0	0
T33	0	756	0	0
T36	0	1875	0	0
T45	0	10487	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1766	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	9	0	0
T25	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1710724	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1724	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1710724	0	0
T1	211597	26516	0	0
T2	71650	0	0	0
T3	478163	6657	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	13231	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	15203	0	0
T25	0	370	0	0
T26	0	1915	0	0
T30	0	708	0	0
T33	0	728	0	0
T36	0	1861	0	0
T45	0	10238	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1724	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	9	0	0
T25	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1718738	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1749	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1718738	0	0
T1	211597	26352	0	0
T2	71650	0	0	0
T3	478163	6625	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	12936	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	15229	0	0
T25	0	449	0	0
T26	0	2083	0	0
T30	0	706	0	0
T33	0	760	0	0
T36	0	1842	0	0
T45	0	9968	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1749	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	9	0	0
T25	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1776701	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1811	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1776701	0	0
T1	211597	27648	0	0
T2	71650	0	0	0
T3	478163	6593	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	1493	0	0
T10	0	2566	0	0
T11	0	13701	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T25	0	440	0	0
T26	0	2227	0	0
T30	0	704	0	0
T33	0	697	0	0
T45	0	10732	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1811	0	0
T1	211597	16	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	1	0	0
T10	0	2	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T25	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T33	0	10	0	0
T45	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1693703	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1712	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1693703	0	0
T1	211597	26033	0	0
T2	71650	0	0	0
T3	478163	6561	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	13451	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	15104	0	0
T25	0	398	0	0
T26	0	2071	0	0
T30	0	702	0	0
T33	0	751	0	0
T36	0	1824	0	0
T45	0	10438	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1712	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	9	0	0
T25	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1708879	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1750	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1708879	0	0
T1	211597	25871	0	0
T2	71650	0	0	0
T3	478163	6529	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	13167	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	15148	0	0
T25	0	363	0	0
T26	0	1870	0	0
T30	0	700	0	0
T33	0	747	0	0
T36	0	1820	0	0
T45	0	10188	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1750	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	9	0	0
T25	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T3,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T1,T3,T25
0	0	1	Covered	T1,T3,T25
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	1695876	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	1742	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1695876	0	0
T1	211597	25682	0	0
T2	71650	0	0	0
T3	478163	6497	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	12879	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	15163	0	0
T25	0	440	0	0
T26	0	2224	0	0
T30	0	698	0	0
T33	0	722	0	0
T36	0	1805	0	0
T45	0	9918	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1742	0	0
T1	211597	15	0	0
T2	71650	0	0	0
T3	478163	16	0	0
T4	159212	0	0	0
T6	64639	0	0	0
T7	240216	0	0	0
T11	0	8	0	0
T13	352608	0	0	0
T14	89393	0	0	0
T15	198768	0	0	0
T16	144450	0	0	0
T20	0	9	0	0
T25	0	1	0	0
T26	0	4	0	0
T30	0	1	0	0
T33	0	10	0	0
T36	0	1	0	0
T45	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T10,T20,T21

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T10,T20,T21
1	1	Covered	T10,T20,T21

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T10,T20,T21
1	-	Covered	T10,T20,T21

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T10,T20,T21

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T20,T21
1	1	Covered	T10,T20,T21

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T10,T20,T21
0	0	1	Covered	T10,T20,T21
0	0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T6
0	1	-	Covered	T10,T20,T21
0	0	1	Covered	T10,T20,T21
0	0	0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1514892865	910759	0	0
DstReqKnown_A	9731609	8897480	0	0
SrcAckBusyChk_A	1514892865	922	0	0
SrcBusyKnown_A	1514892865	1513011723	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	910759	0	0
T10	212274	3004	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T20	0	6255	0	0
T21	0	3386	0	0
T32	0	2793	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T63	0	740	0	0
T64	201956	0	0	0
T74	0	1451	0	0
T75	0	3308	0	0
T76	0	1390	0	0
T77	0	1709	0	0
T78	0	3462	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9731609	8897480	0	0
T1	42319	39857	0	0
T2	692	292	0	0
T3	39847	39359	0	0
T4	662	262	0	0
T5	758	358	0	0
T6	497	97	0	0
T7	480	80	0	0
T13	705	305	0	0
T14	714	314	0	0
T15	3975	842	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	922	0	0
T10	212274	2	0	0
T11	131285	0	0	0
T12	376881	0	0	0
T20	0	4	0	0
T21	0	2	0	0
T32	0	6	0	0
T54	175701	0	0	0
T55	260944	0	0	0
T56	51163	0	0	0
T57	248603	0	0	0
T60	247729	0	0	0
T61	49738	0	0	0
T63	0	2	0	0
T64	201956	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	3	0	0
T77	0	2	0	0
T78	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514892865	1513011723	0	0
T1	211597	211282	0	0
T2	71650	71581	0	0
T3	478163	477103	0	0
T4	159212	159140	0	0
T5	41713	41648	0	0
T6	64639	64548	0	0
T7	240216	240141	0	0
T13	352608	352509	0	0
T14	89393	89326	0	0
T15	198768	197598	0	0