SYSRST_CTRL Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.350s	2.109ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.430s	2.453ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.720s	2.402ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.470s	2.550ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	7.380s	6.047ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.040s	2.054ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.425m	37.643ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.410s	2.387ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.630s	2.144ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.040s	2.054ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.410s	2.387ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.724m	195.149ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	7.999m	183.239ms	92	100	92.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	7.992m	181.284ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	21.913m	1.518s	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.530s	2.508ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.630s	2.200ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	50.738m	1.177s	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.970s	2.609ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	13.240m	4.290s	46	50	92.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.815m	41.133ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	9.710m	211.597ms	50	50	100.00
V2	alert_test	sysrst_ctrl_alert_test	6.080s	2.014ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.200s	2.009ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.500s	2.103ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.500s	2.103ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	7.380s	6.047ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.040s	2.054ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.410s	2.387ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	38.630s	8.686ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	7.380s	6.047ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.040s	2.054ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.410s	2.387ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	38.630s	8.686ms	20	20	100.00
V2		TOTAL			680	692	98.27
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.749m	42.011ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.884m	42.457ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.884m	42.457ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.883m	293.698ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			915	932	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	98.81	96.71	100.00	96.15	98.30	99.42	89.03

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 4 failures:

Test sysrst_ctrl_ultra_low_pwr has 4 failures.

4.sysrst_ctrl_ultra_low_pwr.79081443380349661860610700912477249416910146787736133194719928263753104873386
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3438861179 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 3496361179 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 4866361179 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 4892261973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.sysrst_ctrl_ultra_low_pwr.36179197893643509784035669638772366799178731988487361241679223067734619290280
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 4236197791 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 4513697791 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4513697791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 4 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 4 failures.

30.sysrst_ctrl_combo_detect_with_pre_cond.9771390191287428512088281551051837517428776029027327823271489131468350904114
Line 624, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 96302988219 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 106499603551 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x17
  UVM_INFO @ 106499673551 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x16
  UVM_INFO @ 106853063551 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 106867988219 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= d

70.sysrst_ctrl_combo_detect_with_pre_cond.56614773164830365956657678870176954573703389213199692360836110534557579288106
Line 574, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 28206195817 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 28206195817 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 28206195817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:124) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at AcPresentIdx has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

0.sysrst_ctrl_stress_all_with_rand_reset.7853846236891074174955079913880905788893801242741014335956901149958652913744
Line 617, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 53042439232 ps: (sysrst_ctrl_edge_detect_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
  UVM_ERROR @ 53042439232 ps: (sysrst_ctrl_edge_detect_vseq.sv:132) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
  UVM_INFO @ 53042439232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

14.sysrst_ctrl_stress_all_with_rand_reset.32517130870960416643071578211687763451643028686103533428616909747471810084570
Line 607, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 740919756777 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 740919756777 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 740919756777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

17.sysrst_ctrl_stress_all_with_rand_reset.104973435381093275767776228377526527281553942850036785772546004404650693743778
Line 563, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4226274151 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4234613909 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 1/10
  UVM_INFO @ 4234969946 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 4237407524 ps: (cip_base_vseq.sv:715) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 2/10

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:75) [sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

27.sysrst_ctrl_stress_all_with_rand_reset.41230810071719921903026760982534907943596888854328559099248004541727775075417
Line 715, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 89885054008 ps: (sysrst_ctrl_combo_detect_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 89885054008 ps: (sysrst_ctrl_combo_detect_vseq.sv:234) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 89885054008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

37.sysrst_ctrl_combo_detect_with_pre_cond.96525536489472217800062310704380687406206129898859222008807246582747400909212
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 14747453824 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 25093301748 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d
  UVM_INFO @ 25093341748 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1b
  UVM_INFO @ 25702541748 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 25702621748 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3

UVM_ERROR (sysrst_ctrl_pin_override_vseq.sv:25) [sysrst_ctrl_pin_override_vseq] Check failed out_val == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

37.sysrst_ctrl_stress_all_with_rand_reset.111171720556489161021127926810630675552206263841367974535485824622573610854484
Line 661, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 50998177730 ps: (sysrst_ctrl_pin_override_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Check failed out_val == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 51036030806 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 9/10
  UVM_INFO @ 51036734996 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 51036979670 ps: (cip_base_vseq.sv:715) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 10/10

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

60.sysrst_ctrl_combo_detect_with_pre_cond.89738047323999377049203134447797076698707527954633034832965026056479220001096
Line 626, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 77550810006 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 77700810006 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 77720810006 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 77870833958 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
  UVM_INFO @ 77870833958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

65.sysrst_ctrl_combo_detect_with_pre_cond.8203796444333419484774182263814708831006816964090014081619023146057602663985
Line 590, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 39516073106 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 39681073106 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 39701073106 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 49812983026 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d
  UVM_INFO @ 49813073936 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2f

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

95.sysrst_ctrl_combo_detect_with_pre_cond.96337465090831596226332100662278627399899384332339958410161505371852222537827
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15860988555 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-4
  UVM_INFO @ 26155089490 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
  UVM_INFO @ 26155803775 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x31
  UVM_INFO @ 26647660426 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 26650660423 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3