Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1763

1

T1

3

T18

48

T7

7

auto[1]

520

1

T1

1

T7

9

T52

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1714

1

T1

3

T18

12

T7

10

auto[1]

569

1

T1

1

T18

36

T7

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1723

1

T1

3

T18

48

T7

16

auto[1]

560

1

T1

1

T13

4

T52

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1713

1

T1

4

T18

36

T7

6

auto[1]

570

1

T18

12

T7

10

T10

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2042

1

T1

4

T18

24

T7

16

auto[1]

241

1

T18

24

T51

4

T48

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2103

1

T1

4

T18

48

T7

16

auto[1]

180

1

T48

1

T72

4

T109

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2161

1

T1

4

T18

48

T7

16

auto[1]

122

1

T51

4

T48

3

T270

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2094

1

T1

3

T18

24

T7

16

auto[1]

189

1

T1

1

T18

24

T37

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2060

1

T1

4

T18

48

T7

16

auto[1]

223

1

T13

4

T51

4

T37

37

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1692

1

T1

4

T18

36

T7

16

auto[1]

591

1

T18

12

T10

2

T52

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	884	1			T7	16		T10	2		T52	17
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	51	1			T48	1		T250	4		T75	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	108	1			T13	4		T37	34		T72	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	16	1			T351	8		T352	7		T353	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	31	1			T1	1		T110	6		T182	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	29	1			T253	1		T256	4		T76	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	24	1			T182	2		T354	5		T355	7
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	12	1			T37	3		T356	1		T352	7
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	44	1			T48	2		T270	4		T250	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	15	1			T182	3		T355	6		T76	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T357	4		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	16	1			T228	4		T355	7		T358	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T349	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	40	1			T228	4		T242	1		T358	22
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	35	1			T109	2		T359	9		T360	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	20	1			T72	3		T248	7		T361	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T248	6		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	11	1			T362	4		T363	1		T364	6
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T365	2		T366	2		T367	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	8	1			T48	1		T228	4		T368	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T369	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T369	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T359	6		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

114

1

T32

9

T34

12

T270

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

135

1

T48

1

T106

20

T32

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

42

1

T262

9

T266

7

T182

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

108

1

T7

7

T323

8

T248

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T7

3

T106

7

T72

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T10

2

T36

2

T84

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T48

2

T266

6

T323

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

67

1

T37

17

T33

4

T354

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

45

1

T38

1

T183

5

T83

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

69

1

T258

5

T323

10

T253

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T35

3

T110

2

T88

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

86

1

T37

17

T72

3

T101

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T52

3

T262

4

T84

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

34

1

T267

3

T370

3

T133

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T262

2

T149

1

T346

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

127

1

T52

10

T110

2

T256

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

46

1

T7

6

T81

2

T82

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T182

3

T183

6

T250

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T52

2

T371

2

T250

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T34

6

T250

2

T342

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T32

1

T84

4

T372

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

17

1

T52

2

T257

2

T86

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T259

1

T133

1

T357

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

62

1

T13

4

T37

3

T106

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T1

1

T110

2

T371

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T258

3

T256

4

T76

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T34

2

T133

1

T356

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T35

1

T48

1

T250

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T169

2

T373

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T266

1

T344

3

T168

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T371

1

T267

2

T374

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded