Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.35 96.71 100.00 96.79 98.82 99.52 93.38


Total tests in report: 914
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
58.55 58.55 76.53 76.53 65.50 65.50 90.64 90.64 17.31 17.31 77.74 77.74 68.59 68.59 13.54 13.54 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2852635464
77.62 19.07 92.55 16.03 86.02 20.53 96.80 6.16 48.72 31.41 93.01 15.27 85.74 17.15 40.51 26.97 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2861384975
82.46 4.83 94.96 2.41 88.65 2.63 96.80 0.00 71.79 23.08 95.38 2.37 88.44 2.70 41.18 0.67 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3314692811
85.93 3.47 96.03 1.06 89.61 0.96 96.80 0.00 80.77 8.97 96.12 0.74 91.14 2.70 51.03 9.85 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3636137535
88.48 2.55 97.22 1.19 90.87 1.26 97.03 0.23 86.54 5.77 97.08 0.96 93.74 2.60 56.87 5.85 /workspace/coverage/default/23.sysrst_ctrl_stress_all.1940241538
89.90 1.42 97.29 0.07 90.93 0.05 97.03 0.00 87.82 1.28 97.15 0.07 94.70 0.96 64.36 7.49 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1464840510
91.29 1.39 98.12 0.82 91.78 0.86 97.03 0.00 92.95 5.13 97.86 0.70 96.92 2.22 64.36 0.00 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.1501620045
92.36 1.07 98.13 0.02 92.82 1.04 97.72 0.68 92.95 0.00 97.89 0.04 96.92 0.00 70.10 5.74 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.842942499
93.11 0.75 98.34 0.21 93.53 0.71 97.95 0.23 92.95 0.00 97.93 0.04 97.01 0.10 74.05 3.95 /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2299476261
93.74 0.63 98.49 0.15 93.71 0.18 98.17 0.23 93.59 0.64 98.00 0.07 97.11 0.10 77.08 3.03 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2868618058
94.12 0.38 98.64 0.15 93.91 0.20 98.17 0.00 93.59 0.00 98.00 0.00 97.11 0.00 79.38 2.31 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.883325601
94.42 0.31 98.68 0.04 93.98 0.08 98.17 0.00 93.59 0.00 98.00 0.00 97.11 0.00 81.44 2.05 /workspace/coverage/default/10.sysrst_ctrl_combo_detect.165416695
94.71 0.28 98.68 0.00 94.01 0.03 99.77 1.60 93.59 0.00 98.00 0.00 97.21 0.10 81.69 0.26 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.2175354037
94.98 0.28 98.68 0.00 94.06 0.05 99.77 0.00 93.59 0.00 98.00 0.00 97.30 0.10 83.49 1.79 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2944740023
95.23 0.25 98.68 0.00 94.16 0.10 99.77 0.00 93.59 0.00 98.00 0.00 97.98 0.67 84.46 0.97 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1901871408
95.47 0.24 98.75 0.07 94.21 0.05 99.77 0.00 94.87 1.28 98.08 0.07 98.17 0.19 84.46 0.00 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1190362061
95.68 0.21 98.79 0.04 94.29 0.08 99.77 0.00 94.87 0.00 98.08 0.00 98.17 0.00 85.79 1.33 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.837190619
95.86 0.18 98.81 0.02 94.29 0.00 99.77 0.00 94.87 0.00 98.08 0.00 98.17 0.00 87.03 1.23 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.265477462
96.04 0.18 98.88 0.07 94.41 0.13 99.77 0.00 95.51 0.64 98.19 0.11 98.46 0.29 87.03 0.00 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.41216448
96.20 0.17 98.88 0.00 95.32 0.91 99.77 0.00 95.51 0.00 98.19 0.00 98.46 0.00 87.28 0.26 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1008056296
96.34 0.13 98.88 0.00 95.35 0.03 99.77 0.00 95.51 0.00 98.19 0.00 98.55 0.10 88.10 0.82 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2377080889
96.46 0.12 98.92 0.04 95.37 0.03 99.77 0.00 96.15 0.64 98.23 0.04 98.65 0.10 88.10 0.00 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.4064325655
96.58 0.12 98.96 0.04 95.40 0.03 99.77 0.00 96.79 0.64 98.26 0.04 98.75 0.10 88.10 0.00 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.205493869
96.67 0.10 98.96 0.00 95.40 0.00 99.77 0.00 96.79 0.00 98.30 0.04 99.23 0.48 88.26 0.15 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2142985645
96.77 0.10 98.96 0.00 95.40 0.00 99.77 0.00 96.79 0.00 98.30 0.00 99.23 0.00 88.92 0.67 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1727433394
96.85 0.08 99.01 0.06 95.40 0.00 99.77 0.00 96.79 0.00 98.30 0.00 99.23 0.00 89.44 0.51 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4107611655
96.93 0.08 99.01 0.00 95.40 0.00 99.77 0.00 96.79 0.00 98.30 0.00 99.23 0.00 90.00 0.56 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1732538504
96.99 0.07 99.03 0.02 95.70 0.30 99.77 0.00 96.79 0.00 98.34 0.04 99.33 0.10 90.00 0.00 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2991994993
97.06 0.06 99.09 0.06 95.80 0.10 99.77 0.00 96.79 0.00 98.41 0.07 99.33 0.00 90.21 0.21 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1470033105
97.12 0.06 99.09 0.00 95.80 0.00 99.77 0.00 96.79 0.00 98.41 0.00 99.33 0.00 90.62 0.41 /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3856580555
97.17 0.05 99.09 0.00 96.18 0.38 99.77 0.00 96.79 0.00 98.41 0.00 99.33 0.00 90.62 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3978594623
97.22 0.05 99.12 0.04 96.23 0.05 99.77 0.00 96.79 0.00 98.48 0.07 99.42 0.10 90.72 0.10 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.232793220
97.27 0.05 99.18 0.06 96.31 0.08 100.00 0.23 96.79 0.00 98.48 0.00 99.42 0.00 90.72 0.00 /workspace/coverage/default/12.sysrst_ctrl_alert_test.1611273173
97.32 0.05 99.22 0.04 96.46 0.15 100.00 0.00 96.79 0.00 98.56 0.07 99.52 0.10 90.72 0.00 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1217903356
97.37 0.04 99.22 0.00 96.46 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.52 0.00 91.03 0.31 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3668330036
97.41 0.04 99.23 0.02 96.46 0.00 100.00 0.00 96.79 0.00 98.60 0.04 99.52 0.00 91.23 0.21 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.6182763
97.44 0.04 99.23 0.00 96.46 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 91.49 0.26 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3585532578
97.47 0.03 99.23 0.00 96.46 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 91.69 0.21 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2243684240
97.50 0.03 99.23 0.00 96.46 0.00 100.00 0.00 96.79 0.00 98.60 0.00 99.52 0.00 91.90 0.21 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2794482237
97.52 0.02 99.25 0.02 96.46 0.00 100.00 0.00 96.79 0.00 98.63 0.04 99.52 0.00 92.00 0.10 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3988187762
97.55 0.02 99.27 0.02 96.46 0.00 100.00 0.00 96.79 0.00 98.67 0.04 99.52 0.00 92.10 0.10 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3537750968
97.57 0.02 99.27 0.00 96.46 0.00 100.00 0.00 96.79 0.00 98.67 0.00 99.52 0.00 92.26 0.15 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1361913845
97.59 0.02 99.27 0.00 96.49 0.03 100.00 0.00 96.79 0.00 98.67 0.00 99.52 0.00 92.36 0.10 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.175214759
97.60 0.02 99.27 0.00 96.61 0.13 100.00 0.00 96.79 0.00 98.67 0.00 99.52 0.00 92.36 0.00 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2124516792
97.62 0.01 99.27 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.67 0.00 99.52 0.00 92.46 0.10 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1515185638
97.63 0.01 99.27 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.67 0.00 99.52 0.00 92.56 0.10 /workspace/coverage/default/22.sysrst_ctrl_stress_all.3205784283
97.65 0.01 99.27 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.67 0.00 99.52 0.00 92.67 0.10 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1132601335
97.66 0.01 99.29 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.71 0.04 99.52 0.00 92.67 0.00 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1998189491
97.66 0.01 99.31 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.74 0.04 99.52 0.00 92.67 0.00 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.696602919
97.67 0.01 99.33 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.78 0.04 99.52 0.00 92.67 0.00 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.402848368
97.68 0.01 99.35 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.04 99.52 0.00 92.67 0.00 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1496201833
97.69 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.72 0.05 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4161475263
97.69 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.77 0.05 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4257609671
97.70 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.82 0.05 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.197952420
97.71 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.87 0.05 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1993997811
97.72 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.92 0.05 /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4078557313
97.72 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.97 0.05 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.785967687
97.73 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.03 0.05 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2818884735
97.74 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.08 0.05 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.325123463
97.75 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.13 0.05 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3882840130
97.75 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.18 0.05 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3447875510
97.76 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.23 0.05 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1696854593
97.77 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.28 0.05 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.134354342
97.77 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.33 0.05 /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.589627169
97.78 0.01 99.35 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.38 0.05 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.888200151
97.79 0.01 99.35 0.00 96.64 0.03 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.38 0.00 /workspace/coverage/default/13.sysrst_ctrl_stress_all.1912073645
97.79 0.01 99.35 0.00 96.66 0.03 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.38 0.00 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1850003072
97.79 0.01 99.35 0.00 96.69 0.03 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 93.38 0.00 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3139275441

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2512884180
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3749450079
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2426380751
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1067868648
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1406341992
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3711759868
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1605965923
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1837767289
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4138338698
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1724838599
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2893110318
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1810852496
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3589612927
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1418790751
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.909865305
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1079041860
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3330288525
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4169052070
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2244502050
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2094858258
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.576088982
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4172783467
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.210875555
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.186088935
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1707146487
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.527556011
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.951065578
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.318868057
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2037720137
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2694257552
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1865920071
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.486750819
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3084121643
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.310849528
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1878447954
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1395500153
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3764883803
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2575628683
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2095211697
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2137262360
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2885096565
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.603420229
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2739865782
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1066042099
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4258202807
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3559488453
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1951052070
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3112635031
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3311251129
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2155250785
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3880278186
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3825754130
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4173739045
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2861752638
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1760418237
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3405347646
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1685486657
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3996348362
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1360552638
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.500292608
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2769079762
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1619180418
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3116738834
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.626662780
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1187133954
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3405546602
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4274599467
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2821194941
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1818441776
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.706839329
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2061240764
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2651293043
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2848036683
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1209085861
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2161537094
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2573211067
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.661248498
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.445103497
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2480646369
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1229552233
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2205632245
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/workspace/coverage/default/41.sysrst_ctrl_smoke.3399296913
/workspace/coverage/default/41.sysrst_ctrl_stress_all.684966181
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2637027445
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3442177898
/workspace/coverage/default/42.sysrst_ctrl_alert_test.1065116403
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3963231634
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.3800450608
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3856119123
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1581612450
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2572545334
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2565155587
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3771513955
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.578942360
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1267797640
/workspace/coverage/default/42.sysrst_ctrl_smoke.2883704209
/workspace/coverage/default/42.sysrst_ctrl_stress_all.46339770
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2698565658
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.4266223261
/workspace/coverage/default/43.sysrst_ctrl_alert_test.352417977
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.822907137
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.67159951
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3479068430
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.1350105760
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4248259423
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1514962529
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.4219533684
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1075577052
/workspace/coverage/default/43.sysrst_ctrl_smoke.656265470
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1181044540
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4114861099
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.28281515
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2679428868
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1605416238
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3565762790
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1827679915
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2756923620
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.835098430
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2137914920
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.790677564
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1984612279
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3070743381
/workspace/coverage/default/44.sysrst_ctrl_smoke.1723699295
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2789508012
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2996725930
/workspace/coverage/default/45.sysrst_ctrl_alert_test.397690624
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.190757867
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1055493798
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3586653405
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2840381894
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.381309569
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.176285838
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1820902055
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.4276868749
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2324572810
/workspace/coverage/default/45.sysrst_ctrl_smoke.912070157
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2422723269
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.647240748
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3271329529
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1445789641
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2163124040
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1641807924
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1790258067
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2547006337
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3209745481
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.373728704
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1793628401
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2556706247
/workspace/coverage/default/46.sysrst_ctrl_smoke.3742301749
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2741982555
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2147186979
/workspace/coverage/default/47.sysrst_ctrl_alert_test.4293618886
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1677083478
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3626660891
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2040698020
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1841976035
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.202720417
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.992160403
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.402910574
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3551743727
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2208073916
/workspace/coverage/default/47.sysrst_ctrl_smoke.3385208960
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3915321950
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1297637027
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3048104669
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.961157344
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2130377316
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2055213976
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1766040981
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3724660432
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1454080661
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2324154738
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.380234130
/workspace/coverage/default/48.sysrst_ctrl_smoke.3643790185
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2096213362
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1764527306
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1404956547
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1024724924
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2649938005
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1742819991
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1180511536
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2641941280
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4122735573
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.331420163
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3869975556
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2107875497
/workspace/coverage/default/49.sysrst_ctrl_smoke.1575021068
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2506757733
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.382942682
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2805116005
/workspace/coverage/default/5.sysrst_ctrl_alert_test.3567147581
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2100489805
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2253911772
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3552634850
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.293290422
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3251869827
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.511266624
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1861922140
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3864568769
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.100546374
/workspace/coverage/default/5.sysrst_ctrl_smoke.678182340
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3743914632
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.249404352
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3352020214
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3023426102
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.687076939
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2532897029
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3455020071
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2909354414
/workspace/coverage/default/6.sysrst_ctrl_alert_test.487810318
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.9407139
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3690618530
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.381607528
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1535153313
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3996946338
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3918864484
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2989195899
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2972046076
/workspace/coverage/default/6.sysrst_ctrl_smoke.861397127
/workspace/coverage/default/6.sysrst_ctrl_stress_all.2018891211
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3867537118
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2711601782
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.335491662
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1387595635
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3773437780
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3427382538
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3760301069
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1867359307
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4096130604
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2496413593
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3014908188
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3387967452
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.4110300499
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.247987947
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1949413245
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1913226789
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2292949097
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.391446424
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1801592132
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.814607673
/workspace/coverage/default/7.sysrst_ctrl_smoke.2850844782
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3947730066
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1301700683
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2579473508
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1757814936
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3625633435
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.4187073374
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.482605291
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.762460326
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1617173261
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.209788009
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1242367815
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2108911565
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3706336769
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1084810872
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2673380749
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2872961002
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3925417622
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2916898773
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3705320961
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2256632078
/workspace/coverage/default/8.sysrst_ctrl_smoke.2115386641
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3098415865
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3340996681
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4243351170
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.4009757169
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3759584272
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.449774234
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.292216468
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3715250098
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1736129426
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2524206167
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3364837340
/workspace/coverage/default/9.sysrst_ctrl_alert_test.752955564
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.518745488
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2128983149
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3759122993
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1948909913
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.346658060
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1387313469
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1915279874
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3725086133
/workspace/coverage/default/9.sysrst_ctrl_smoke.2921547236
/workspace/coverage/default/9.sysrst_ctrl_stress_all.1438403578
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2954043071
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.4014857467
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4052496442
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1710371535
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3281809048
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1245559588
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3811381726



Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2547006337 Jul 22 04:53:07 PM PDT 24 Jul 22 04:53:09 PM PDT 24 2467045605 ps
T5 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3707923983 Jul 22 04:49:24 PM PDT 24 Jul 22 04:49:25 PM PDT 24 2650487830 ps
T6 /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3592038140 Jul 22 04:50:45 PM PDT 24 Jul 22 04:50:48 PM PDT 24 2107060192 ps
T1 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1757814936 Jul 22 04:52:08 PM PDT 24 Jul 22 04:53:53 PM PDT 24 42212924786 ps
T14 /workspace/coverage/default/48.sysrst_ctrl_smoke.3643790185 Jul 22 04:51:53 PM PDT 24 Jul 22 04:52:00 PM PDT 24 2108507406 ps
T15 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2764009660 Jul 22 04:50:45 PM PDT 24 Jul 22 04:50:50 PM PDT 24 2517489323 ps
T16 /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3649380012 Jul 22 04:48:19 PM PDT 24 Jul 22 04:48:25 PM PDT 24 4817692612 ps
T17 /workspace/coverage/default/13.sysrst_ctrl_stress_all.1912073645 Jul 22 04:50:10 PM PDT 24 Jul 22 04:50:45 PM PDT 24 14194340912 ps
T18 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2852635464 Jul 22 04:53:15 PM PDT 24 Jul 22 04:54:22 PM PDT 24 107998906573 ps
T19 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2137914920 Jul 22 04:51:33 PM PDT 24 Jul 22 04:51:35 PM PDT 24 2640853635 ps
T20 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2916898773 Jul 22 04:48:39 PM PDT 24 Jul 22 04:48:42 PM PDT 24 2477109037 ps
T21 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.329263383 Jul 22 04:49:53 PM PDT 24 Jul 22 04:49:57 PM PDT 24 3829761889 ps
T2 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2861384975 Jul 22 04:50:10 PM PDT 24 Jul 22 04:50:37 PM PDT 24 95026902024 ps
T3 /workspace/coverage/default/39.sysrst_ctrl_edge_detect.662114090 Jul 22 04:51:14 PM PDT 24 Jul 22 04:51:25 PM PDT 24 4159635682 ps
T25 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2991994993 Jul 22 04:50:19 PM PDT 24 Jul 22 04:50:26 PM PDT 24 8671901000 ps
T7 /workspace/coverage/default/36.sysrst_ctrl_combo_detect.3189659123 Jul 22 04:50:57 PM PDT 24 Jul 22 04:51:21 PM PDT 24 32197412441 ps
T56 /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.568257633 Jul 22 04:54:06 PM PDT 24 Jul 22 04:54:08 PM PDT 24 3145427827 ps
T57 /workspace/coverage/default/18.sysrst_ctrl_alert_test.3073766847 Jul 22 04:50:45 PM PDT 24 Jul 22 04:50:48 PM PDT 24 2022430517 ps
T26 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3321230444 Jul 22 04:50:38 PM PDT 24 Jul 22 04:51:31 PM PDT 24 47857990029 ps
T58 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1339435540 Jul 22 04:49:27 PM PDT 24 Jul 22 04:49:35 PM PDT 24 2611807355 ps
T59 /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1125353191 Jul 22 04:49:59 PM PDT 24 Jul 22 04:50:06 PM PDT 24 2613374062 ps
T8 /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1125246740 Jul 22 04:50:11 PM PDT 24 Jul 22 04:50:19 PM PDT 24 3658144203 ps
T9 /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2553458890 Jul 22 04:50:20 PM PDT 24 Jul 22 04:50:25 PM PDT 24 4761702533 ps
T10 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2868618058 Jul 22 04:48:23 PM PDT 24 Jul 22 04:49:19 PM PDT 24 86962487960 ps
T11 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.548911673 Jul 22 04:48:58 PM PDT 24 Jul 22 04:49:01 PM PDT 24 3409619217 ps
T12 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1497440325 Jul 22 04:49:36 PM PDT 24 Jul 22 04:49:38 PM PDT 24 4179306326 ps
T62 /workspace/coverage/default/29.sysrst_ctrl_stress_all.3901571145 Jul 22 04:50:20 PM PDT 24 Jul 22 04:50:32 PM PDT 24 8407170927 ps
T13 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1245559588 Jul 22 04:53:53 PM PDT 24 Jul 22 04:55:03 PM PDT 24 34370023251 ps
T68 /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3499997519 Jul 22 04:48:19 PM PDT 24 Jul 22 04:48:22 PM PDT 24 2629390888 ps
T120 /workspace/coverage/default/19.sysrst_ctrl_alert_test.3330959756 Jul 22 04:49:39 PM PDT 24 Jul 22 04:49:42 PM PDT 24 2027005762 ps
T121 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2362937761 Jul 22 04:50:19 PM PDT 24 Jul 22 04:50:30 PM PDT 24 3257390758 ps
T64 /workspace/coverage/default/16.sysrst_ctrl_stress_all.1763873938 Jul 22 04:49:13 PM PDT 24 Jul 22 04:49:48 PM PDT 24 13145641987 ps
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T44 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3636137535 Jul 22 04:50:46 PM PDT 24 Jul 22 04:51:25 PM PDT 24 31673619106 ps
T180 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1641399536 Jul 22 04:50:10 PM PDT 24 Jul 22 04:50:12 PM PDT 24 2644301978 ps
T181 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2989195899 Jul 22 04:48:30 PM PDT 24 Jul 22 04:48:37 PM PDT 24 2185962393 ps
T182 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4107611655 Jul 22 04:52:01 PM PDT 24 Jul 22 04:53:03 PM PDT 24 105520383941 ps
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T183 /workspace/coverage/default/49.sysrst_ctrl_stress_all.2506757733 Jul 22 04:52:02 PM PDT 24 Jul 22 04:57:55 PM PDT 24 140004152213 ps
T184 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.822907137 Jul 22 04:51:25 PM PDT 24 Jul 22 04:51:28 PM PDT 24 3286681146 ps
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T429 /workspace/coverage/default/24.sysrst_ctrl_stress_all.2512877676 Jul 22 04:49:52 PM PDT 24 Jul 22 04:50:03 PM PDT 24 7083722393 ps
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T431 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3384336868 Jul 22 04:49:46 PM PDT 24 Jul 22 04:49:54 PM PDT 24 2471268896 ps
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T151 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1496201833 Jul 22 04:50:57 PM PDT 24 Jul 22 04:51:06 PM PDT 24 12489037189 ps
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T119 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2218591318 Jul 22 04:51:03 PM PDT 24 Jul 22 04:51:08 PM PDT 24 5187684011 ps
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T316 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3332357755 Jul 22 04:49:38 PM PDT 24 Jul 22 04:50:27 PM PDT 24 18833080566 ps
T438 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.802006107 Jul 22 04:49:39 PM PDT 24 Jul 22 04:49:48 PM PDT 24 2614294185 ps
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T301 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1853540130 Jul 22 04:50:30 PM PDT 24 Jul 22 04:52:33 PM PDT 24 52827216508 ps
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T445 /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2187343637 Jul 22 04:50:01 PM PDT 24 Jul 22 04:50:04 PM PDT 24 2471492035 ps
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T446 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2706126938 Jul 22 04:49:12 PM PDT 24 Jul 22 04:49:18 PM PDT 24 3987407577 ps
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T448 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3570217827 Jul 22 04:48:49 PM PDT 24 Jul 22 04:48:52 PM PDT 24 2628601639 ps
T449 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3919861801 Jul 22 04:51:03 PM PDT 24 Jul 22 04:51:05 PM PDT 24 2627238753 ps
T450 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4248259423 Jul 22 04:51:22 PM PDT 24 Jul 22 04:51:25 PM PDT 24 2629481632 ps
T451 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.530205747 Jul 22 04:52:44 PM PDT 24 Jul 22 04:52:52 PM PDT 24 2251352840 ps
T342 /workspace/coverage/default/24.sysrst_ctrl_combo_detect.3547770602 Jul 22 04:49:43 PM PDT 24 Jul 22 04:52:44 PM PDT 24 138118032620 ps
T251 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.4009757169 Jul 22 04:52:09 PM PDT 24 Jul 22 04:54:23 PM PDT 24 56049047264 ps
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T74 /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.4129519436 Jul 22 04:49:44 PM PDT 24 Jul 22 04:49:49 PM PDT 24 2923758984 ps
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T456 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1602616293 Jul 22 04:47:53 PM PDT 24 Jul 22 04:47:58 PM PDT 24 2026676633 ps
T144 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3515476572 Jul 22 04:52:28 PM PDT 24 Jul 22 04:52:30 PM PDT 24 3284069731 ps
T457 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3500227359 Jul 22 04:49:36 PM PDT 24 Jul 22 04:49:38 PM PDT 24 2642264124 ps
T264 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1827679915 Jul 22 04:54:58 PM PDT 24 Jul 22 04:55:28 PM PDT 24 24584462137 ps
T458 /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4078557313 Jul 22 04:48:48 PM PDT 24 Jul 22 04:48:50 PM PDT 24 2558509423 ps
T459 /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.835938663 Jul 22 04:48:01 PM PDT 24 Jul 22 04:48:04 PM PDT 24 2257493025 ps
T460 /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.4016411725 Jul 22 04:52:30 PM PDT 24 Jul 22 04:52:36 PM PDT 24 3842644405 ps
T461 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3338314928 Jul 22 04:51:07 PM PDT 24 Jul 22 04:51:11 PM PDT 24 2260021800 ps
T462 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1793628401 Jul 22 04:51:43 PM PDT 24 Jul 22 04:51:50 PM PDT 24 2176128939 ps
T269 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3625633435 Jul 22 04:52:09 PM PDT 24 Jul 22 04:53:16 PM PDT 24 24831963422 ps
T260 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.463759302 Jul 22 04:50:36 PM PDT 24 Jul 22 04:52:52 PM PDT 24 103464850741 ps
T307 /workspace/coverage/default/8.sysrst_ctrl_stress_all.3098415865 Jul 22 04:49:08 PM PDT 24 Jul 22 04:49:44 PM PDT 24 13992041662 ps
T188 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.382942682 Jul 22 04:52:01 PM PDT 24 Jul 22 04:52:25 PM PDT 24 38354950437 ps
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