Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T5

11

T15

9

T2

31

auto[1]

977

1

T5

9

T15

11

T2

29

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

469

1

T5

6

T15

5

T2

13

from_0to1

470

1

T5

6

T15

6

T2

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T5

10

T15

11

T2

26

auto[1]

1031

1

T5

10

T15

9

T2

34

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T5

7

T15

12

T2

35

auto[1]

998

1

T5

13

T15

8

T2

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T15

1

T2

1

T10

2

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T5

3

T2

1

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T5

1

T2

3

T10

2

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T15

1

T2

1

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T15

1

T2

3

T10

2

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T15

1

T2

1

T10

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T2

1

T10

1

T390

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T5

2

T15

1

T2

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T5

1

T15

1

T2

4

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T2

3

T10

1

T104

1

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T15

2

T391

1

T312

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T5

1

T10

1

T40

2

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T15

1

T2

2

T10

3

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T5

1

T2

1

T40

4

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T5

1

T2

2

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T5

2

T15

2

T2

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1015

1

T5

9

T15

14

T2

31

auto[1]

999

1

T5

11

T15

6

T2

29

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

491

1

T5

3

T15

6

T2

14

from_0to1

496

1

T5

3

T15

5

T2

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

982

1

T5

9

T15

13

T2

24

auto[1]

1032

1

T5

11

T15

7

T2

36

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T5

14

T15

11

T2

25

auto[1]

962

1

T5

6

T15

9

T2

35

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T15

1

T2

2

T10

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T15

2

T2

1

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T5

1

T15

1

T2

3

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T2

1

T10

3

T40

4

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T5

2

T15

1

T2

4

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T15

1

T2

2

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T5

1

T10

2

T276

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T15

1

T10

2

T40

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T15

1

T2

1

T40

2

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T2

2

T10

1

T40

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T5

1

T15

1

T2

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T5

1

T2

2

T392

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T40

4

T392

1

T393

3

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T15

1

T2

2

T40

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T2

4

T10

1

T40

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T15

1

T2

2

T10

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

969

1

T5

7

T15

10

T2

30

auto[1]

1045

1

T5

13

T15

10

T2

30

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T5

5

T15

5

T2

17

from_0to1

477

1

T5

6

T15

6

T2

17

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1017

1

T5

12

T15

12

T2

33

auto[1]

997

1

T5

8

T15

8

T2

27

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T5

11

T15

15

T2

27

auto[1]

1031

1

T5

9

T15

5

T2

33

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T5

2

T15

2

T2

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T15

1

T2

2

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T2

2

T40

1

T391

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T2

3

T10

1

T392

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T5

2

T15

1

T2

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T15

2

T2

1

T393

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T2

2

T10

1

T390

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T2

1

T10

3

T104

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T5

1

T2

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T15

1

T2

4

T10

4

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T5

1

T15

1

T2

3

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T5

1

T2

1

T10

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T5

1

T15

1

T2

2

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T2

4

T40

3

T390

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T15

1

T2

3

T10

2

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T5

3

T15

1

T2

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1012

1

T5

11

T15

8

T2

28

auto[1]

1002

1

T5

9

T15

12

T2

32

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

476

1

T5

4

T15

4

T2

14

from_0to1

479

1

T5

4

T15

4

T2

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T5

14

T15

6

T2

29

auto[1]

1012

1

T5

6

T15

14

T2

31

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T5

11

T15

7

T2

38

auto[1]

991

1

T5

9

T15

13

T2

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T5

1

T2

1

T10

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T5

1

T2

2

T10

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T5

1

T2

2

T276

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T5

1

T2

1

T40

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T5

2

T2

2

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T5

1

T15

1

T10

2

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T15

1

T2

3

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T2

1

T40

1

T394

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T2

3

T40

1

T104

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T2

3

T10

3

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T2

2

T10

2

T40

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T15

4

T10

1

T40

3

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T5

1

T2

1

T10

3

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T2

1

T40

1

T276

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T15

1

T2

2

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T15

1

T2

4

T10

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T5

10

T15

7

T2

24

auto[1]

1036

1

T5

10

T15

13

T2

36

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

483

1

T5

5

T15

5

T2

12

from_0to1

478

1

T5

4

T15

6

T2

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T5

9

T15

11

T2

27

auto[1]

980

1

T5

11

T15

9

T2

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T5

11

T15

13

T2

32

auto[1]

982

1

T5

9

T15

7

T2

28

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T15

1

T10

2

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T2

1

T40

1

T38

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T5

1

T15

1

T2

2

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T5

2

T2

2

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T15

1

T2

1

T10

2

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T2

1

T10

1

T40

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T5

1

T15

1

T2

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T5

1

T15

1

T2

1

auto[1]

from_1to0

auto[0]

auto[0]

81

1

T15

1

T2

1

T10

3

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T5

2

T2

2

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T2

2

T10

1

T40

3

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T15

2

T2

2

T10

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T5

2

T15

1

T2

2

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T15

1

T2

1

T10

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T2

4

T10

1

T40

3

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T15

1

T2

1

T40

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T5

9

T15

10

T2

30

auto[1]

1011

1

T5

11

T15

10

T2

30

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

487

1

T5

5

T15

5

T2

11

from_0to1

480

1

T5

5

T15

5

T2

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

987

1

T5

9

T15

13

T2

29

auto[1]

1027

1

T5

11

T15

7

T2

31

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T5

12

T15

12

T2

34

auto[1]

993

1

T5

8

T15

8

T2

26

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T5

1

T15

1

T2

2

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T2

1

T10

1

T40

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T2

1

T10

1

T40

3

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T2

2

T10

2

T40

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T15

2

T10

3

T40

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T15

2

T2

3

T10

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T5

2

T38

2

T104

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T5

1

T2

1

T10

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T5

1

T2

2

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T15

2

T2

1

T40

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T5

2

T15

2

T2

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T5

1

T2

1

T10

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T2

2

T40

4

T104

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T5

1

T2

2

T10

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T5

1

T15

1

T2

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T2

1

T40

1

T104

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T5

9

T15

9

T2

33

auto[1]

982

1

T5

11

T15

11

T2

27

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

466

1

T5

3

T15

7

T2

16

from_0to1

474

1

T5

3

T15

6

T2

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011

1

T5

12

T15

10

T2

29

auto[1]

1003

1

T5

8

T15

10

T2

31

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T5

10

T15

16

T2

34

auto[1]

1014

1

T5

10

T15

4

T2

26

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T15

1

T2

1

T10

2

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T5

1

T2

3

T104

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T5

1

T15

1

T2

4

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T15

1

T2

3

T10

2

auto[0]

from_0to1

auto[0]

auto[0]

43

1

T2

2

T10

1

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T5

1

T15

1

T2

4

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T15

2

T2

2

T10

3

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T2

2

T40

2

T276

3

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T15

1

T2

2

T40

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T2

3

T10

2

T40

1

auto[1]

from_1to0

auto[1]

auto[0]

49

1

T15

3

T10

3

T40

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T5

1

T10

1

T40

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T15

2

T2

2

T10

2

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T2

1

T40

2

T104

2

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T5

1

T2

3

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T5

1

T15

1

T10

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T5

12

T15

10

T2

24

auto[1]

993

1

T5

8

T15

10

T2

36

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T5

4

T15

3

T2

16

from_0to1

490

1

T5

5

T15

4

T2

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T5

15

T15

13

T2

24

auto[1]

996

1

T5

5

T15

7

T2

36

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1009

1

T5

12

T15

8

T2

24

auto[1]

1005

1

T5

8

T15

12

T2

36

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T5

1

T15

1

T2

2

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T5

1

T2

2

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T2

2

T10

2

T40

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T2

5

T10

1

T40

4

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T5

2

T10

2

T40

3

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T15

2

T2

1

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T5

1

T15

1

T2

4

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T2

2

T40

1

T276

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T5

1

T15

1

T2

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T2

2

T10

2

T104

2

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T5

1

T10

1

T40

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T15

1

T2

1

T10

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T5

2

T15

1

T2

2

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T10

3

T40

1

T392

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T10

2

T104

1

T276

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T2

7

T40

1

T390

1