Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	143154	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

110710

1

T4

5

T5

48

T6

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	131845	1			T4	3		T5	62		T6	18
values[0x0]	60912	1			T4	3		T5	19		T1	319
values[0x1]	61107	1			T5	42		T6	1		T1	288

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	115791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

138073

1

T4

5

T5

62

T6

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	772	1			T17	1		T18	6		T2	5
valid_sources[0x01]	961	1			T18	3		T2	6		T7	4
valid_sources[0x02]	1087	1			T18	3		T2	5		T26	9
valid_sources[0x03]	1612	1			T1	22		T18	2		T2	1
valid_sources[0x04]	1290	1			T1	43		T18	7		T2	5
valid_sources[0x05]	2090	1			T18	7		T20	1		T2	9
valid_sources[0x06]	830	1			T1	2		T18	1		T2	4
valid_sources[0x07]	730	1			T17	2		T18	3		T2	3
valid_sources[0x08]	855	1			T17	1		T2	2		T26	1
valid_sources[0x09]	739	1			T18	4		T2	2		T26	2
valid_sources[0x0a]	775	1			T18	1		T2	4		T7	14
valid_sources[0x0b]	695	1			T18	5		T20	2		T2	2
valid_sources[0x0c]	829	1			T18	3		T2	4		T7	10
valid_sources[0x0d]	881	1			T17	1		T18	2		T2	3
valid_sources[0x0e]	1401	1			T18	1		T2	5		T7	1
valid_sources[0x0f]	969	1			T17	2		T18	1		T2	4
valid_sources[0x10]	784	1			T1	8		T17	6		T18	4
valid_sources[0x11]	736	1			T18	4		T2	4		T26	1
valid_sources[0x12]	735	1			T18	7		T2	9		T26	2
valid_sources[0x13]	879	1			T2	1		T7	2		T51	4
valid_sources[0x14]	743	1			T6	2		T18	5		T2	3
valid_sources[0x15]	815	1			T18	6		T2	1		T10	5
valid_sources[0x16]	1074	1			T17	2		T18	4		T2	5
valid_sources[0x17]	777	1			T17	1		T18	3		T2	5
valid_sources[0x18]	809	1			T18	10		T2	8		T26	11
valid_sources[0x19]	816	1			T18	2		T2	7		T26	3
valid_sources[0x1a]	877	1			T17	1		T18	2		T2	4
valid_sources[0x1b]	931	1			T18	1		T2	11		T59	1
valid_sources[0x1c]	1135	1			T5	5		T18	1		T2	3
valid_sources[0x1d]	906	1			T17	1		T18	1		T2	4
valid_sources[0x1e]	1746	1			T6	3		T17	2		T18	5
valid_sources[0x1f]	823	1			T18	2		T20	6		T2	6
valid_sources[0x20]	777	1			T17	2		T18	2		T2	5
valid_sources[0x21]	810	1			T18	2		T2	2		T26	4
valid_sources[0x22]	939	1			T17	4		T18	10		T20	1
valid_sources[0x23]	735	1			T17	1		T18	3		T2	7
valid_sources[0x24]	793	1			T17	2		T18	2		T2	1
valid_sources[0x25]	1095	1			T18	1		T2	1		T7	1
valid_sources[0x26]	1031	1			T17	1		T18	4		T20	4
valid_sources[0x27]	860	1			T1	31		T18	1		T2	4
valid_sources[0x28]	869	1			T18	1		T20	3		T2	3
valid_sources[0x29]	846	1			T16	1		T17	5		T2	2
valid_sources[0x2a]	872	1			T18	3		T2	3		T25	2
valid_sources[0x2b]	1156	1			T5	3		T18	8		T2	3
valid_sources[0x2c]	1229	1			T18	1		T2	2		T25	1
valid_sources[0x2d]	1027	1			T18	4		T20	1		T2	4
valid_sources[0x2e]	828	1			T18	3		T2	6		T58	2
valid_sources[0x2f]	1102	1			T18	3		T2	11		T26	1
valid_sources[0x30]	1883	1			T18	4		T2	1		T10	9
valid_sources[0x31]	871	1			T18	5		T20	2		T2	3
valid_sources[0x32]	754	1			T18	8		T2	1		T7	2
valid_sources[0x33]	972	1			T1	14		T17	3		T18	5
valid_sources[0x34]	878	1			T1	11		T18	5		T20	1
valid_sources[0x35]	1266	1			T16	1		T18	4		T2	2
valid_sources[0x36]	835	1			T18	9		T2	1		T26	7
valid_sources[0x37]	923	1			T1	36		T18	1		T26	2
valid_sources[0x38]	963	1			T1	27		T2	2		T26	1
valid_sources[0x39]	1210	1			T17	1		T18	2		T2	2
valid_sources[0x3a]	1477	1			T18	2		T2	5		T26	8
valid_sources[0x3b]	865	1			T18	2		T20	1		T21	1
valid_sources[0x3c]	772	1			T18	4		T2	5		T25	1
valid_sources[0x3d]	776	1			T17	1		T18	4		T2	4
valid_sources[0x3e]	784	1			T18	2		T2	4		T7	5
valid_sources[0x3f]	796	1			T18	2		T2	4		T26	2
valid_sources[0x40]	876	1			T17	3		T18	10		T21	1
valid_sources[0x41]	958	1			T17	1		T18	2		T26	3
valid_sources[0x42]	924	1			T5	26		T1	33		T18	4
valid_sources[0x43]	1022	1			T4	1		T17	5		T18	2
valid_sources[0x44]	841	1			T17	1		T18	3		T2	6
valid_sources[0x45]	769	1			T18	2		T2	4		T26	2
valid_sources[0x46]	1133	1			T17	1		T18	4		T21	1
valid_sources[0x47]	878	1			T5	31		T14	1		T18	1
valid_sources[0x48]	751	1			T18	1		T20	1		T2	3
valid_sources[0x49]	833	1			T1	1		T18	1		T2	6
valid_sources[0x4a]	863	1			T18	1		T2	9		T25	1
valid_sources[0x4b]	1921	1			T26	1		T59	1		T10	2
valid_sources[0x4c]	816	1			T1	5		T18	3		T2	7
valid_sources[0x4d]	1071	1			T18	1		T2	7		T26	5
valid_sources[0x4e]	892	1			T1	11		T18	1		T2	4
valid_sources[0x4f]	1638	1			T20	3		T2	2		T25	1
valid_sources[0x50]	955	1			T1	2		T18	3		T2	4
valid_sources[0x51]	797	1			T18	2		T21	1		T2	3
valid_sources[0x52]	849	1			T1	5		T18	4		T2	5
valid_sources[0x53]	1680	1			T4	2		T15	122		T17	1
valid_sources[0x54]	763	1			T2	6		T7	2		T26	3
valid_sources[0x55]	930	1			T5	11		T18	3		T2	2
valid_sources[0x56]	830	1			T18	1		T2	5		T10	3
valid_sources[0x57]	732	1			T17	3		T18	5		T2	5
valid_sources[0x58]	683	1			T18	1		T2	7		T58	1
valid_sources[0x59]	1071	1			T18	4		T2	1		T26	4
valid_sources[0x5a]	891	1			T17	3		T2	1		T26	4
valid_sources[0x5b]	760	1			T17	4		T18	1		T2	7
valid_sources[0x5c]	965	1			T18	5		T2	8		T26	1
valid_sources[0x5d]	757	1			T18	2		T2	8		T7	1
valid_sources[0x5e]	861	1			T26	4		T58	3		T10	2
valid_sources[0x5f]	866	1			T18	2		T2	9		T26	3
valid_sources[0x60]	730	1			T18	3		T21	1		T2	1
valid_sources[0x61]	801	1			T18	1		T21	1		T2	5
valid_sources[0x62]	869	1			T18	5		T2	3		T7	8
valid_sources[0x63]	2033	1			T18	3		T2	5		T26	5
valid_sources[0x64]	976	1			T17	4		T18	5		T21	1
valid_sources[0x65]	937	1			T1	15		T18	4		T2	1
valid_sources[0x66]	1702	1			T18	2		T26	9		T10	3
valid_sources[0x67]	850	1			T1	11		T18	3		T2	9
valid_sources[0x68]	860	1			T18	2		T20	1		T2	1
valid_sources[0x69]	788	1			T5	3		T1	2		T18	6
valid_sources[0x6a]	727	1			T1	3		T18	2		T26	3
valid_sources[0x6b]	905	1			T18	4		T2	6		T7	3
valid_sources[0x6c]	1512	1			T5	2		T1	4		T17	1
valid_sources[0x6d]	679	1			T18	1		T2	3		T26	1
valid_sources[0x6e]	1880	1			T1	8		T17	2		T18	3
valid_sources[0x6f]	1087	1			T18	2		T20	1		T2	1
valid_sources[0x70]	825	1			T18	1		T2	9		T26	1
valid_sources[0x71]	771	1			T1	2		T17	1		T18	4
valid_sources[0x72]	1778	1			T17	2		T18	4		T2	6
valid_sources[0x73]	932	1			T1	11		T18	4		T2	11
valid_sources[0x74]	1101	1			T5	16		T1	22		T2	1
valid_sources[0x75]	806	1			T18	7		T2	3		T26	6
valid_sources[0x76]	835	1			T5	2		T18	6		T2	8
valid_sources[0x77]	1575	1			T5	2		T1	15		T18	2
valid_sources[0x78]	731	1			T1	36		T2	4		T7	2
valid_sources[0x79]	791	1			T18	1		T2	3		T10	7
valid_sources[0x7a]	1029	1			T18	1		T20	1		T2	1
valid_sources[0x7b]	820	1			T18	2		T2	4		T10	3
valid_sources[0x7c]	938	1			T1	22		T17	1		T2	4
valid_sources[0x7d]	2032	1			T18	6		T2	9		T10	9
valid_sources[0x7e]	714	1			T18	1		T2	3		T25	2
valid_sources[0x7f]	1571	1			T18	8		T2	6		T26	5
valid_sources[0x80]	788	1			T18	2		T2	5		T26	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59865

1

T4

3

T5

29

T6

10

values[0x0]

all_enables

biggest_size

29824

1

T4

2

T5

11

T1

117

values[0x1]

all_enables

biggest_size

21021

1

T5

8

T1

52

T15

5