Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T21,T2,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T2,T10
1	0	Covered	T5,T6,T1
1	1	Covered	T21,T2,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T2,T10
0	1	Covered	T35,T74,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T2,T10
0	1	Covered	T21,T2,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T2,T10
1	-	Covered	T21,T2,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T2,T10
DetectSt	168	Covered	T21,T2,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T21,T2,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T2,T10
DebounceSt->IdleSt	163	Covered	T40,T35,T49
DetectSt->IdleSt	186	Covered	T35,T74,T85
DetectSt->StableSt	191	Covered	T21,T2,T10
IdleSt->DebounceSt	148	Covered	T21,T2,T10
StableSt->IdleSt	206	Covered	T21,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T2,T10
0	1	Covered	T21,T2,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T2,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T2,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T2,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T35,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T2,T10
DetectSt	-	-	-	-	1	-	-	Covered	T35,T74,T85
DetectSt	-	-	-	-	0	1	-	Covered	T21,T2,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T2,T10
StableSt	-	-	-	-	-	-	0	Covered	T21,T2,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	298	0	0
CntIncr_A	8421531	110776	0	0
CntNoWrap_A	8421531	7777532	0	0
DetectStDropOut_A	8421531	6	0	0
DetectedOut_A	8421531	844	0	0
DetectedPulseOut_A	8421531	131	0	0
DisabledIdleSt_A	8421531	7654550	0	0
DisabledNoDetection_A	8421531	7656753	0	0
EnterDebounceSt_A	8421531	168	0	0
EnterDetectSt_A	8421531	137	0	0
EnterStableSt_A	8421531	131	0	0
PulseIsPulse_A	8421531	131	0	0
StayInStableSt	8421531	712	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	6773	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	130	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	298	0	0
T2	19005	6	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	2	0	0
T21	766	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	5	0	0
T40	0	2	0	0
T49	0	1	0	0
T52	0	4	0	0
T53	0	6	0	0
T55	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	110776	0	0
T2	19005	109	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	10	0	0
T21	766	20	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	198	0	0
T40	0	176	0	0
T49	0	7	0	0
T52	0	32	0	0
T53	0	171	0	0
T55	0	36	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777532	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	6	0	0
T35	12511	1	0	0
T36	12707	0	0	0
T45	771	0	0	0
T66	491	0	0	0
T67	493	0	0	0
T74	0	1	0	0
T80	2188	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	522	0	0	0
T95	548	0	0	0
T96	423	0	0	0
T97	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	844	0	0
T2	19005	15	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	3	0	0
T21	766	11	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	1	0	0
T52	0	8	0	0
T53	0	18	0	0
T55	0	10	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	9	0	0
T107	0	12	0	0
T108	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	131	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	1	0	0
T21	766	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7654550	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7656753	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	168	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	1	0	0
T21	766	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	3	0	0
T40	0	2	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	137	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	1	0	0
T21	766	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	2	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	131	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	1	0	0
T21	766	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	131	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	1	0	0
T21	766	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	712	0	0
T2	19005	12	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	2	0	0
T21	766	10	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T52	0	6	0	0
T53	0	15	0	0
T55	0	9	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	8	0	0
T107	0	10	0	0
T108	0	5	0	0
T115	0	13	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	6773	0	0
T1	8442	28	0	0
T5	529	6	0	0
T6	421	1	0	0
T14	421	4	0	0
T15	503	6	0	0
T16	963	0	0	0
T17	2839	18	0	0
T18	21599	32	0	0
T19	528	6	0	0
T20	495	8	0	0
T21	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	130	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	1	0	0
T21	766	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T35	0	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T55	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T25,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T25,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T10
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T25,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T12
0	1	Covered	T2,T40,T36
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T12
0	1	Unreachable
1	0	Covered	T2,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T25,T10
DetectSt	168	Covered	T2,T10,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T12
DebounceSt->IdleSt	163	Covered	T25,T40,T49
DetectSt->IdleSt	186	Covered	T2,T40,T36
DetectSt->StableSt	191	Covered	T2,T10,T12
IdleSt->DebounceSt	148	Covered	T2,T25,T10
StableSt->IdleSt	206	Covered	T2,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T25,T10
0	1	Covered	T2,T25,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T25,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T40,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T25,T10
DetectSt	-	-	-	-	1	-	-	Covered	T2,T40,T36
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	207	0	0
CntIncr_A	8421531	505883	0	0
CntNoWrap_A	8421531	7777623	0	0
DetectStDropOut_A	8421531	24	0	0
DetectedOut_A	8421531	1344110	0	0
DetectedPulseOut_A	8421531	55	0	0
DisabledIdleSt_A	8421531	5346486	0	0
DisabledNoDetection_A	8421531	5348742	0	0
EnterDebounceSt_A	8421531	129	0	0
EnterDetectSt_A	8421531	79	0	0
EnterStableSt_A	8421531	55	0	0
PulseIsPulse_A	8421531	55	0	0
StayInStableSt	8421531	1344055	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	6773	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_sticky_sva.StableStDropOut_A	8421531	575372	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	207	0	0
T2	19005	4	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	2	0	0
T12	0	4	0	0
T25	1734	1	0	0
T26	9572	0	0	0
T35	0	2	0	0
T36	0	6	0	0
T40	0	9	0	0
T49	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	505883	0	0
T2	19005	102	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	76	0	0
T12	0	86	0	0
T25	1734	96	0	0
T26	9572	0	0	0
T35	0	64	0	0
T36	0	180	0	0
T40	0	160	0	0
T49	0	47	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	65	0	0
T73	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777623	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	24	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T36	0	2	0	0
T40	0	3	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	2	0	0
T124	0	2	0	0
T125	0	3	0	0
T126	0	3	0	0
T127	0	2	0	0
T128	0	2	0	0
T129	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1344110	0	0
T2	19005	159	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	13	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T33	0	45	0	0
T35	0	194	0	0
T36	0	123	0	0
T40	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	577	0	0
T73	0	192	0	0
T105	0	94	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	55	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	5346486	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	5348742	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	129	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T25	1734	1	0	0
T26	9572	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T40	0	5	0	0
T49	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	79	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T40	0	4	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	55	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	55	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1344055	0	0
T2	19005	158	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T12	0	11	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T33	0	44	0	0
T35	0	193	0	0
T36	0	122	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	576	0	0
T73	0	191	0	0
T105	0	93	0	0
T117	0	264	0	0
T118	0	346700	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	6773	0	0
T1	8442	28	0	0
T5	529	6	0	0
T6	421	1	0	0
T14	421	4	0	0
T15	503	6	0	0
T16	963	0	0	0
T17	2839	18	0	0
T18	21599	32	0	0
T19	528	6	0	0
T20	495	8	0	0
T21	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	575372	0	0
T2	19005	155	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	24	0	0
T12	0	68	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T33	0	263	0	0
T35	0	82	0	0
T36	0	149	0	0
T40	0	128	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	90	0	0
T73	0	588	0	0
T105	0	681	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T14
1	1	Covered	T5,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T25,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T25,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T10
1	0	Covered	T5,T6,T14
1	1	Covered	T2,T25,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T61,T40
0	1	Covered	T2,T10,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T61,T40
0	1	Unreachable
1	0	Covered	T12,T61,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T25,T10
DetectSt	168	Covered	T2,T10,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T61,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T12
DebounceSt->IdleSt	163	Covered	T2,T25,T49
DetectSt->IdleSt	186	Covered	T2,T10,T79
DetectSt->StableSt	191	Covered	T12,T61,T40
IdleSt->DebounceSt	148	Covered	T2,T25,T10
StableSt->IdleSt	206	Covered	T12,T61,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T25,T10
0	1	Covered	T2,T25,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T25,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T25,T130
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T25,T10
DetectSt	-	-	-	-	1	-	-	Covered	T2,T10,T79
DetectSt	-	-	-	-	0	1	-	Covered	T12,T61,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T61,T40
StableSt	-	-	-	-	-	-	0	Covered	T12,T61,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	182	0	0
CntIncr_A	8421531	6739	0	0
CntNoWrap_A	8421531	7777648	0	0
DetectStDropOut_A	8421531	15	0	0
DetectedOut_A	8421531	12812	0	0
DetectedPulseOut_A	8421531	56	0	0
DisabledIdleSt_A	8421531	5346486	0	0
DisabledNoDetection_A	8421531	5348742	0	0
EnterDebounceSt_A	8421531	112	0	0
EnterDetectSt_A	8421531	71	0	0
EnterStableSt_A	8421531	56	0	0
PulseIsPulse_A	8421531	56	0	0
StayInStableSt	8421531	12756	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_sticky_sva.StableStDropOut_A	8421531	2163707	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	182	0	0
T2	19005	8	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	2	0	0
T12	0	4	0	0
T25	1734	1	0	0
T26	9572	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T40	0	2	0	0
T49	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	6739	0	0
T2	19005	50	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	49	0	0
T12	0	40	0	0
T25	1734	19	0	0
T26	9572	0	0	0
T35	0	13	0	0
T36	0	19	0	0
T40	0	83	0	0
T49	0	48	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	22	0	0
T73	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777648	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	15	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	3	0	0
T137	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	12812	0	0
T12	835	29	0	0
T13	6874	0	0	0
T33	0	203	0	0
T35	0	46	0	0
T36	0	171	0	0
T40	0	510	0	0
T46	621	0	0	0
T61	0	119	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	597	0	0
T105	0	600	0	0
T117	0	46	0	0
T118	0	732	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	56	0	0
T12	835	2	0	0
T13	6874	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T46	621	0	0	0
T61	0	1	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	1	0	0
T105	0	1	0	0
T117	0	1	0	0
T118	0	3	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	5346486	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	5348742	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	112	0	0
T2	19005	5	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T25	1734	1	0	0
T26	9572	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T49	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	71	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	56	0	0
T12	835	2	0	0
T13	6874	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T46	621	0	0	0
T61	0	1	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	1	0	0
T105	0	1	0	0
T117	0	1	0	0
T118	0	3	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	56	0	0
T12	835	2	0	0
T13	6874	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T46	621	0	0	0
T61	0	1	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	1	0	0
T105	0	1	0	0
T117	0	1	0	0
T118	0	3	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	12756	0	0
T12	835	27	0	0
T13	6874	0	0	0
T33	0	202	0	0
T35	0	45	0	0
T36	0	170	0	0
T40	0	509	0	0
T46	621	0	0	0
T61	0	118	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	596	0	0
T105	0	599	0	0
T117	0	45	0	0
T118	0	729	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2163707	0	0
T12	835	114	0	0
T13	6874	0	0	0
T33	0	87	0	0
T35	0	294	0	0
T36	0	363	0	0
T40	0	104	0	0
T46	621	0	0	0
T61	0	599	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	137	0	0
T105	0	99	0	0
T117	0	340	0	0
T118	0	626471	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T25,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T25,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T10
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T25,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T61,T40
0	1	Covered	T25,T10,T36
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T61,T40
0	1	Unreachable
1	0	Covered	T12,T61,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T25,T10
DetectSt	168	Covered	T25,T10,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T61,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T10,T12
DebounceSt->IdleSt	163	Covered	T2,T36,T49
DetectSt->IdleSt	186	Covered	T25,T10,T36
DetectSt->StableSt	191	Covered	T12,T61,T40
IdleSt->DebounceSt	148	Covered	T2,T25,T10
StableSt->IdleSt	206	Covered	T12,T61,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T25,T10
0	1	Covered	T2,T25,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T10,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T25,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T36,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T25,T10
DetectSt	-	-	-	-	1	-	-	Covered	T25,T10,T36
DetectSt	-	-	-	-	0	1	-	Covered	T12,T61,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T61,T40
StableSt	-	-	-	-	-	-	0	Covered	T12,T61,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	195	0	0
CntIncr_A	8421531	485998	0	0
CntNoWrap_A	8421531	7777635	0	0
DetectStDropOut_A	8421531	12	0	0
DetectedOut_A	8421531	293912	0	0
DetectedPulseOut_A	8421531	44	0	0
DisabledIdleSt_A	8421531	5346486	0	0
DisabledNoDetection_A	8421531	5348742	0	0
EnterDebounceSt_A	8421531	140	0	0
EnterDetectSt_A	8421531	56	0	0
EnterStableSt_A	8421531	44	0	0
PulseIsPulse_A	8421531	44	0	0
StayInStableSt	8421531	293868	0	0
gen_high_event_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_sticky_sva.StableStDropOut_A	8421531	1163211	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	195	0	0
T2	19005	5	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	2	0	0
T12	0	4	0	0
T25	1734	2	0	0
T26	9572	0	0	0
T35	0	2	0	0
T36	0	6	0	0
T40	0	2	0	0
T49	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	485998	0	0
T2	19005	405	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	60	0	0
T12	0	90	0	0
T25	1734	57	0	0
T26	9572	0	0	0
T35	0	55	0	0
T36	0	400	0	0
T40	0	37	0	0
T49	0	50	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	91	0	0
T73	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777635	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	12	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	1	0	0
T25	1734	1	0	0
T26	9572	0	0	0
T36	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T90	0	1	0	0
T125	0	2	0	0
T130	0	2	0	0
T133	0	1	0	0
T138	0	2	0	0
T139	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	293912	0	0
T12	835	50	0	0
T13	6874	0	0	0
T35	0	260	0	0
T36	0	103	0	0
T40	0	284	0	0
T46	621	0	0	0
T61	0	422	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	706	0	0
T79	0	406	0	0
T105	0	159	0	0
T117	0	199	0	0
T119	0	130	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	44	0	0
T12	835	2	0	0
T13	6874	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T46	621	0	0	0
T61	0	1	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	1	0	0
T79	0	1	0	0
T105	0	1	0	0
T117	0	1	0	0
T119	0	1	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	5346486	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	5348742	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	140	0	0
T2	19005	5	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T25	1734	1	0	0
T26	9572	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T40	0	1	0	0
T49	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	56	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	1	0	0
T12	0	2	0	0
T25	1734	1	0	0
T26	9572	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T61	0	1	0	0
T73	0	1	0	0
T105	0	1	0	0
T117	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	44	0	0
T12	835	2	0	0
T13	6874	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T46	621	0	0	0
T61	0	1	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	1	0	0
T79	0	1	0	0
T105	0	1	0	0
T117	0	1	0	0
T119	0	1	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	44	0	0
T12	835	2	0	0
T13	6874	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T46	621	0	0	0
T61	0	1	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	1	0	0
T79	0	1	0	0
T105	0	1	0	0
T117	0	1	0	0
T119	0	1	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	293868	0	0
T12	835	48	0	0
T13	6874	0	0	0
T35	0	259	0	0
T36	0	102	0	0
T40	0	283	0	0
T46	621	0	0	0
T61	0	421	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	705	0	0
T79	0	405	0	0
T105	0	158	0	0
T117	0	198	0	0
T119	0	129	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1163211	0	0
T12	835	58	0	0
T13	6874	0	0	0
T35	0	40	0	0
T36	0	37	0	0
T40	0	388	0	0
T46	621	0	0	0
T61	0	233	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T73	0	39	0	0
T79	0	12456	0	0
T105	0	616	0	0
T117	0	170	0	0
T119	0	57	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T40,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T40,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T40,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T40,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T40,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T40,T45
0	1	Covered	T3,T40,T45
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T40,T45
1	-	Covered	T3,T40,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T40,T45
DetectSt	168	Covered	T3,T40,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T40,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T40,T45
DebounceSt->IdleSt	163	Covered	T49,T73,T140
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T40,T45
IdleSt->DebounceSt	148	Covered	T3,T40,T45
StableSt->IdleSt	206	Covered	T3,T40,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T40,T45
0	1	Covered	T3,T40,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T40,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T40,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T40,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T140,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T40,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T40,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T40,T45
StableSt	-	-	-	-	-	-	0	Covered	T3,T40,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	85	0	0
CntIncr_A	8421531	2475	0	0
CntNoWrap_A	8421531	7777745	0	0
DetectStDropOut_A	8421531	0	0	0
DetectedOut_A	8421531	2678	0	0
DetectedPulseOut_A	8421531	40	0	0
DisabledIdleSt_A	8421531	7423756	0	0
DisabledNoDetection_A	8421531	7425955	0	0
EnterDebounceSt_A	8421531	45	0	0
EnterDetectSt_A	8421531	40	0	0
EnterStableSt_A	8421531	40	0	0
PulseIsPulse_A	8421531	40	0	0
StayInStableSt	8421531	2615	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	85	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	4	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T142	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2475	0	0
T3	831	71	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	18	0	0
T40	0	60	0	0
T41	0	36	0	0
T42	0	59	0	0
T44	0	12	0	0
T45	0	72	0	0
T49	0	14	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	21	0	0
T142	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777745	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2678	0	0
T3	831	30	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	39	0	0
T40	0	83	0	0
T41	0	180	0	0
T42	0	51	0	0
T44	0	39	0	0
T45	0	153	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T142	0	37	0	0
T143	0	68	0	0
T144	0	165	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	40	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7423756	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7425955	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	45	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T142	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	40	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	40	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	40	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2615	0	0
T3	831	29	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	38	0	0
T40	0	80	0	0
T41	0	178	0	0
T42	0	49	0	0
T44	0	37	0	0
T45	0	150	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T142	0	35	0	0
T143	0	66	0	0
T144	0	162	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	16	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T77	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T5,T1,T14
1	1	Covered	T3,T9,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T40
0	1	Covered	T3,T40,T45
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T40
1	-	Covered	T3,T40,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T40
DetectSt	168	Covered	T3,T9,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T9,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T40
DebounceSt->IdleSt	163	Covered	T39,T49,T149
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T9,T40
IdleSt->DebounceSt	148	Covered	T3,T9,T40
StableSt->IdleSt	206	Covered	T3,T40,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T40
0	1	Covered	T3,T9,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T149,T132
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T40,T45
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	120	0	0
CntIncr_A	8421531	184992	0	0
CntNoWrap_A	8421531	7777710	0	0
DetectStDropOut_A	8421531	0	0	0
DetectedOut_A	8421531	56211	0	0
DetectedPulseOut_A	8421531	58	0	0
DisabledIdleSt_A	8421531	7293387	0	0
DisabledNoDetection_A	8421531	7295598	0	0
EnterDebounceSt_A	8421531	62	0	0
EnterDetectSt_A	8421531	58	0	0
EnterStableSt_A	8421531	58	0	0
PulseIsPulse_A	8421531	58	0	0
StayInStableSt	8421531	56127	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	2531	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	120	0	0
T3	831	4	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	3	0	0
T40	0	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	4	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	6	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	184992	0	0
T3	831	142	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	99	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	36	0	0
T40	0	60	0	0
T42	0	59	0	0
T43	0	54	0	0
T45	0	72	0	0
T49	0	14	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	113	0	0
T150	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777710	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	56211	0	0
T3	831	78	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	444	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	125	0	0
T40	0	55	0	0
T42	0	33	0	0
T43	0	112	0	0
T45	0	61	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	273	0	0
T142	0	12	0	0
T150	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	58	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	3	0	0
T142	0	1	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7293387	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7295598	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	62	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	3	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	58	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	3	0	0
T142	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	58	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	3	0	0
T142	0	1	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	58	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	3	0	0
T142	0	1	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	56127	0	0
T3	831	75	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	442	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	123	0	0
T40	0	53	0	0
T42	0	32	0	0
T43	0	110	0	0
T45	0	59	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	268	0	0
T142	0	11	0	0
T150	0	61	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2531	0	0
T1	8442	0	0	0
T2	0	58	0	0
T3	0	2	0	0
T5	529	3	0	0
T6	421	0	0	0
T14	421	1	0	0
T15	503	6	0	0
T16	963	0	0	0
T17	2839	12	0	0
T18	21599	0	0	0
T19	528	5	0	0
T20	495	3	0	0
T58	0	5	0	0
T59	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	31	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T142	0	1	0	0
T144	0	2	0	0
T146	0	1	0	0
T150	0	1	0	0