Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T11,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T11,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T11,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T11,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T11,T46
0	1	Covered	T2
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T11,T46
0	1	Covered	T2,T45,T39
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T11,T46
1	-	Covered	T2,T45,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T11,T46
DetectSt	168	Covered	T2,T11,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T11,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T11,T46
DebounceSt->IdleSt	163	Covered	T49,T143
DetectSt->IdleSt	186	Covered	T2
DetectSt->StableSt	191	Covered	T2,T11,T46
IdleSt->DebounceSt	148	Covered	T2,T11,T46
StableSt->IdleSt	206	Covered	T2,T45,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T11,T46
0	1	Covered	T2,T11,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T11,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T11,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T143
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T11,T46
DetectSt	-	-	-	-	1	-	-	Covered	T2
DetectSt	-	-	-	-	0	1	-	Covered	T2,T11,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T45,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T11,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	74	0	0
CntIncr_A	8421531	130456	0	0
CntNoWrap_A	8421531	7777756	0	0
DetectStDropOut_A	8421531	1	0	0
DetectedOut_A	8421531	68502	0	0
DetectedPulseOut_A	8421531	35	0	0
DisabledIdleSt_A	8421531	7374366	0	0
DisabledNoDetection_A	8421531	7376580	0	0
EnterDebounceSt_A	8421531	38	0	0
EnterDetectSt_A	8421531	36	0	0
EnterStableSt_A	8421531	35	0	0
PulseIsPulse_A	8421531	35	0	0
StayInStableSt	8421531	68449	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	74	0	0
T2	19005	4	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T44	0	2	0	0
T45	0	4	0	0
T46	0	2	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	3	0	0
T151	0	4	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	130456	0	0
T2	19005	20	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	95	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	18	0	0
T44	0	12	0	0
T45	0	72	0	0
T46	0	95	0	0
T49	0	15	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	42	0	0
T151	0	140	0	0
T152	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777756	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	68502	0	0
T2	19005	42	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	45	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T44	0	104	0	0
T45	0	74	0	0
T46	0	47	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	7	0	0
T145	0	41	0	0
T151	0	85	0	0
T152	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	35	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7374366	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7376580	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	38	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	36	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	35	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	35	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	68449	0	0
T2	19005	41	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T11	0	43	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T44	0	102	0	0
T45	0	72	0	0
T46	0	45	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T77	0	472	0	0
T143	0	6	0	0
T145	0	40	0	0
T151	0	82	0	0
T152	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	16	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T126	0	1	0	0
T141	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T154,T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T9
1	-	Covered	T2,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T9
DetectSt	168	Covered	T2,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T9
DebounceSt->IdleSt	163	Covered	T2,T49,T77
DetectSt->IdleSt	186	Covered	T154,T155
DetectSt->StableSt	191	Covered	T2,T8,T9
IdleSt->DebounceSt	148	Covered	T2,T8,T9
StableSt->IdleSt	206	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T77,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T154,T155
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	128	0	0
CntIncr_A	8421531	70155	0	0
CntNoWrap_A	8421531	7777702	0	0
DetectStDropOut_A	8421531	2	0	0
DetectedOut_A	8421531	4193	0	0
DetectedPulseOut_A	8421531	59	0	0
DisabledIdleSt_A	8421531	7499020	0	0
DisabledNoDetection_A	8421531	7501225	0	0
EnterDebounceSt_A	8421531	68	0	0
EnterDetectSt_A	8421531	61	0	0
EnterStableSt_A	8421531	59	0	0
PulseIsPulse_A	8421531	59	0	0
StayInStableSt	8421531	4102	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	2881	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	128	0	0
T2	19005	7	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	4	0	0
T9	0	4	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	2	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	2	0	0
T73	0	2	0	0
T150	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	70155	0	0
T2	19005	124	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	70	0	0
T9	0	198	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	30	0	0
T41	0	72	0	0
T42	0	59	0	0
T49	0	15	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	14	0	0
T73	0	71	0	0
T150	0	246	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777702	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2	0	0
T154	1026	1	0	0
T155	0	1	0	0
T157	1778	0	0	0
T158	433	0	0	0
T159	17448	0	0	0
T160	422	0	0	0
T161	406	0	0	0
T162	699	0	0	0
T163	500	0	0	0
T164	451	0	0	0
T165	613	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	4193	0	0
T2	19005	286	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	84	0	0
T9	0	84	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	41	0	0
T41	0	287	0	0
T42	0	52	0	0
T44	0	4	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	41	0	0
T73	0	171	0	0
T150	0	154	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	59	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	2	0	0
T9	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	1	0	0
T73	0	1	0	0
T150	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7499020	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7501225	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	68	0	0
T2	19005	4	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	2	0	0
T9	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	1	0	0
T73	0	1	0	0
T150	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	61	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	2	0	0
T9	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	1	0	0
T73	0	1	0	0
T150	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	59	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	2	0	0
T9	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	1	0	0
T73	0	1	0	0
T150	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	59	0	0
T2	19005	3	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	2	0	0
T9	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	1	0	0
T73	0	1	0	0
T150	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	4102	0	0
T2	19005	281	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	81	0	0
T9	0	81	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	39	0	0
T41	0	284	0	0
T42	0	50	0	0
T44	0	3	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T64	0	39	0	0
T73	0	169	0	0
T150	0	150	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2881	0	0
T1	8442	0	0	0
T2	0	62	0	0
T4	493	2	0	0
T5	529	4	0	0
T6	421	1	0	0
T14	421	2	0	0
T15	503	8	0	0
T16	963	5	0	0
T17	2839	13	0	0
T18	21599	0	0	0
T19	528	7	0	0
T20	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	26	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	1	0	0
T9	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T132	0	4	0	0
T143	0	2	0	0
T145	0	1	0	0
T150	0	2	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T40
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T3,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T40
0	1	Covered	T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T40
0	1	Covered	T3,T40,T45
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T40
1	-	Covered	T3,T40,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T40
DetectSt	168	Covered	T2,T3,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T40
DebounceSt->IdleSt	163	Covered	T49,T77,T149
DetectSt->IdleSt	186	Covered	T166
DetectSt->StableSt	191	Covered	T2,T3,T40
IdleSt->DebounceSt	148	Covered	T2,T3,T40
StableSt->IdleSt	206	Covered	T2,T3,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T40
0	1	Covered	T2,T3,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T167,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T40
DetectSt	-	-	-	-	1	-	-	Covered	T166
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T40,T45
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	120	0	0
CntIncr_A	8421531	169744	0	0
CntNoWrap_A	8421531	7777710	0	0
DetectStDropOut_A	8421531	3	0	0
DetectedOut_A	8421531	58229	0	0
DetectedPulseOut_A	8421531	55	0	0
DisabledIdleSt_A	8421531	7428611	0	0
DisabledNoDetection_A	8421531	7430823	0	0
EnterDebounceSt_A	8421531	63	0	0
EnterDetectSt_A	8421531	58	0	0
EnterStableSt_A	8421531	55	0	0
PulseIsPulse_A	8421531	55	0	0
StayInStableSt	8421531	58148	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	120	0	0
T2	19005	2	0	0
T3	831	4	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	4	0	0
T42	0	2	0	0
T44	0	4	0	0
T45	0	6	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	169744	0	0
T2	19005	94	0	0
T3	831	142	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	18	0	0
T40	0	60	0	0
T41	0	72	0	0
T42	0	59	0	0
T44	0	24	0	0
T45	0	108	0	0
T49	0	16	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777710	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	3	0	0
T76	27289	0	0	0
T166	19034	3	0	0
T169	55688	0	0	0
T170	524	0	0	0
T171	522	0	0	0
T172	1058	0	0	0
T173	422	0	0	0
T174	622	0	0	0
T175	404	0	0	0
T176	646	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	58229	0	0
T2	19005	178	0	0
T3	831	65	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	134	0	0
T40	0	55	0	0
T41	0	221	0	0
T42	0	52	0	0
T44	0	96	0	0
T45	0	168	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	68	0	0
T177	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	55	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7428611	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7430823	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	63	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	58	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	1	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	55	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	55	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	58148	0	0
T2	19005	176	0	0
T3	831	62	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	133	0	0
T40	0	53	0	0
T41	0	218	0	0
T42	0	50	0	0
T44	0	93	0	0
T45	0	164	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T79	0	66	0	0
T177	0	34	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	28	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T77	0	1	0	0
T144	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T3,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T46
0	1	Covered	T44
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T46
0	1	Covered	T3,T45,T179
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T46
1	-	Covered	T3,T45,T179

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T46
DetectSt	168	Covered	T2,T3,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T46
DebounceSt->IdleSt	163	Covered	T45,T49,T172
DetectSt->IdleSt	186	Covered	T44
DetectSt->StableSt	191	Covered	T2,T3,T46
IdleSt->DebounceSt	148	Covered	T2,T3,T46
StableSt->IdleSt	206	Covered	T2,T3,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T46
0	1	Covered	T2,T3,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T46
DetectSt	-	-	-	-	1	-	-	Covered	T44
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T45,T179
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	57	0	0
CntIncr_A	8421531	1572	0	0
CntNoWrap_A	8421531	7777773	0	0
DetectStDropOut_A	8421531	1	0	0
DetectedOut_A	8421531	1996	0	0
DetectedPulseOut_A	8421531	26	0	0
DisabledIdleSt_A	8421531	7764569	0	0
DisabledNoDetection_A	8421531	7766782	0	0
EnterDebounceSt_A	8421531	30	0	0
EnterDetectSt_A	8421531	27	0	0
EnterStableSt_A	8421531	26	0	0
PulseIsPulse_A	8421531	26	0	0
StayInStableSt	8421531	1956	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	6281	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	57	0	0
T2	19005	2	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	2	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	2	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1572	0	0
T2	19005	10	0	0
T3	831	71	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	61	0	0
T44	0	12	0	0
T45	0	72	0	0
T46	0	95	0	0
T49	0	15	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	42	0	0
T144	0	17	0	0
T179	0	59	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777773	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1	0	0
T44	6334	1	0	0
T82	13545	0	0	0
T180	528	0	0	0
T181	437	0	0	0
T182	21103	0	0	0
T183	28000	0	0	0
T184	657	0	0	0
T185	682	0	0	0
T186	1811	0	0	0
T187	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1996	0	0
T2	19005	59	0	0
T3	831	142	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	40	0	0
T45	0	35	0	0
T46	0	47	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	169	0	0
T144	0	65	0	0
T149	0	142	0	0
T179	0	22	0	0
T188	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	26	0	0
T2	19005	1	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T149	0	2	0	0
T179	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7764569	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7766782	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	30	0	0
T2	19005	1	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	27	0	0
T2	19005	1	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T179	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	26	0	0
T2	19005	1	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T149	0	2	0	0
T179	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	26	0	0
T2	19005	1	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T149	0	2	0	0
T179	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1956	0	0
T2	19005	57	0	0
T3	831	141	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	38	0	0
T45	0	34	0	0
T46	0	45	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	166	0	0
T144	0	64	0	0
T149	0	139	0	0
T179	0	21	0	0
T188	0	48	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	6281	0	0
T1	8442	26	0	0
T2	0	70	0	0
T5	529	4	0	0
T6	421	2	0	0
T14	421	2	0	0
T15	503	6	0	0
T16	963	0	0	0
T17	2839	17	0	0
T18	21599	19	0	0
T19	528	4	0	0
T20	495	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	11	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	952	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T45	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T149	0	1	0	0
T172	0	1	0	0
T179	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T191,T192,T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T40
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T9
1	-	Covered	T2,T3,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T9
DetectSt	168	Covered	T2,T3,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T9
DebounceSt->IdleSt	163	Covered	T49,T193,T137
DetectSt->IdleSt	186	Covered	T191,T192,T154
DetectSt->StableSt	191	Covered	T2,T3,T9
IdleSt->DebounceSt	148	Covered	T2,T3,T9
StableSt->IdleSt	206	Covered	T2,T3,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T193,T137
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T191,T192,T154
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	140	0	0
CntIncr_A	8421531	249070	0	0
CntNoWrap_A	8421531	7777690	0	0
DetectStDropOut_A	8421531	3	0	0
DetectedOut_A	8421531	70123	0	0
DetectedPulseOut_A	8421531	65	0	0
DisabledIdleSt_A	8421531	7163123	0	0
DisabledNoDetection_A	8421531	7165326	0	0
EnterDebounceSt_A	8421531	72	0	0
EnterDetectSt_A	8421531	68	0	0
EnterStableSt_A	8421531	65	0	0
PulseIsPulse_A	8421531	65	0	0
StayInStableSt	8421531	70037	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	140	0	0
T2	19005	2	0	0
T3	831	4	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	2	0	0
T40	0	2	0	0
T44	0	4	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	2	0	0
T150	0	4	0	0
T151	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	249070	0	0
T2	19005	94	0	0
T3	831	142	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	99	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	61	0	0
T40	0	30	0	0
T44	0	24	0	0
T49	0	14	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	71	0	0
T150	0	164	0	0
T151	0	140	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777690	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	3	0	0
T154	0	1	0	0
T191	991	1	0	0
T192	0	1	0	0
T194	11011	0	0	0
T195	841	0	0	0
T196	7408	0	0	0
T197	404	0	0	0
T198	422	0	0	0
T199	410	0	0	0
T200	987	0	0	0
T201	427	0	0	0
T202	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	70123	0	0
T2	19005	31	0	0
T3	831	76	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	44	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	147	0	0
T40	0	98	0	0
T44	0	97	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	62	0	0
T143	0	5	0	0
T150	0	120	0	0
T151	0	69	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	65	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7163123	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7165326	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	72	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T150	0	2	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	68	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	65	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	65	0	0
T2	19005	1	0	0
T3	831	2	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	70037	0	0
T2	19005	30	0	0
T3	831	73	0	0
T7	6439	0	0	0
T8	731	0	0	0
T9	0	42	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T38	0	145	0	0
T40	0	97	0	0
T44	0	94	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	61	0	0
T143	0	3	0	0
T150	0	118	0	0
T151	0	67	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	43	0	0
T2	19005	1	0	0
T3	831	1	0	0
T7	6439	0	0	0
T8	731	0	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T73	0	1	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0
T203	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T8,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T10
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T8,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T45
0	1	Covered	T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T45
0	1	Covered	T45,T39,T179
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T45
1	-	Covered	T45,T39,T179

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T45
DetectSt	168	Covered	T2,T8,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T45
DebounceSt->IdleSt	163	Covered	T45,T49,T44
DetectSt->IdleSt	186	Covered	T189
DetectSt->StableSt	191	Covered	T2,T8,T45
IdleSt->DebounceSt	148	Covered	T2,T8,T45
StableSt->IdleSt	206	Covered	T2,T45,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T45
0	1	Covered	T2,T8,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T45
DetectSt	-	-	-	-	1	-	-	Covered	T189
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T39,T179
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	77	0	0
CntIncr_A	8421531	2135	0	0
CntNoWrap_A	8421531	7777753	0	0
DetectStDropOut_A	8421531	1	0	0
DetectedOut_A	8421531	2614	0	0
DetectedPulseOut_A	8421531	36	0	0
DisabledIdleSt_A	8421531	7636580	0	0
DisabledNoDetection_A	8421531	7638793	0	0
EnterDebounceSt_A	8421531	41	0	0
EnterDetectSt_A	8421531	37	0	0
EnterStableSt_A	8421531	36	0	0
PulseIsPulse_A	8421531	36	0	0
StayInStableSt	8421531	2558	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	6008	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	77	0	0
T2	19005	4	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	2	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	4	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	3	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T150	0	4	0	0
T151	0	2	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2135	0	0
T2	19005	104	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	35	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	36	0	0
T41	0	36	0	0
T44	0	12	0	0
T45	0	72	0	0
T49	0	16	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T150	0	164	0	0
T151	0	74	0	0
T179	0	59	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777753	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1	0	0
T167	10213	0	0	0
T189	1108	1	0	0
T204	511	0	0	0
T205	402	0	0	0
T206	978	0	0	0
T207	522	0	0	0
T208	993	0	0	0
T209	5582	0	0	0
T210	129153	0	0	0
T211	469	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2614	0	0
T2	19005	161	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	74	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	104	0	0
T41	0	44	0	0
T45	0	34	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	169	0	0
T150	0	348	0	0
T151	0	50	0	0
T152	0	39	0	0
T179	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	36	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0
T179	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7636580	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7638793	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	41	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T49	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	37	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	36	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0
T179	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	36	0	0
T2	19005	2	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	1	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0
T179	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2558	0	0
T2	19005	157	0	0
T3	831	0	0	0
T7	6439	0	0	0
T8	731	72	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T39	0	101	0	0
T41	0	43	0	0
T45	0	33	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T143	0	166	0	0
T150	0	345	0	0
T151	0	49	0	0
T152	0	37	0	0
T179	0	21	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	6008	0	0
T1	8442	25	0	0
T2	0	63	0	0
T5	529	5	0	0
T6	421	2	0	0
T14	421	1	0	0
T15	503	6	0	0
T16	963	0	0	0
T17	2839	15	0	0
T18	21599	20	0	0
T19	528	3	0	0
T20	495	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	15	0	0
T36	12707	0	0	0
T38	9998	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	771	1	0	0
T66	491	0	0	0
T67	493	0	0	0
T77	0	1	0	0
T80	2188	0	0	0
T94	522	0	0	0
T95	548	0	0	0
T96	423	0	0	0
T97	523	0	0	0
T132	0	1	0	0
T143	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T179	0	1	0	0
T189	0	1	0	0