Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T40,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T11
1	0	Covered	T5,T6,T1
1	1	Covered	T8,T11,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T40,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T40,T45
0	1	Covered	T39,T43,T41
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T40,T45
1	-	Covered	T39,T43,T41

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T40
DetectSt	168	Covered	T11,T40,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T40,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T40,T45
DebounceSt->IdleSt	163	Covered	T8,T39,T49
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T40,T45
IdleSt->DebounceSt	148	Covered	T8,T11,T40
StableSt->IdleSt	206	Covered	T40,T39,T43

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T40
0	1	Covered	T8,T11,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T11,T40,T45
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T40,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T39,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T40,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T43,T41
StableSt	-	-	-	-	-	-	0	Covered	T11,T40,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	114	0	0
CntIncr_A	8421531	132019	0	0
CntNoWrap_A	8421531	7777716	0	0
DetectStDropOut_A	8421531	0	0	0
DetectedOut_A	8421531	4707	0	0
DetectedPulseOut_A	8421531	53	0	0
DisabledIdleSt_A	8421531	7372477	0	0
DisabledNoDetection_A	8421531	7374689	0	0
EnterDebounceSt_A	8421531	61	0	0
EnterDetectSt_A	8421531	53	0	0
EnterStableSt_A	8421531	53	0	0
PulseIsPulse_A	8421531	53	0	0
StayInStableSt	8421531	4635	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	33	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8421531	114
T8	731	2
T9	952	0
T10	17392	0
T11	682	2
T12	835	0
T13	6874	0
T39	0	3
T40	0	2
T41	0	6
T43	0	2
T45	0	2
T49	0	1
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T150	0	4
T179	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8421531	132019
T8	731	70
T9	952	0
T10	17392	0
T11	682	95
T12	835	0
T13	6874	0
T39	0	36
T40	0	30
T41	0	108
T43	0	54
T45	0	36
T49	0	14
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T150	0	164
T179	0	59

CntNoWrap_A

Name	Attempts	Real Successes
Total	8421531	7777716
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8421531	4707
T11	682	177
T12	835	0
T13	6874	0
T39	0	41
T40	0	230
T41	0	65
T43	0	17
T45	0	276
T46	621	0
T62	1681	0
T64	2628	0
T68	526	0
T79	0	50
T120	405	0
T121	651	0
T122	426	0
T150	0	349
T151	0	160
T179	0	124

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8421531	53
T11	682	1
T12	835	0
T13	6874	0
T39	0	1
T40	0	1
T41	0	3
T43	0	1
T45	0	1
T46	621	0
T62	1681	0
T64	2628	0
T68	526	0
T79	0	1
T120	405	0
T121	651	0
T122	426	0
T150	0	2
T151	0	1
T179	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8421531	7372477
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8421531	7374689
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8421531	61
T8	731	2
T9	952	0
T10	17392	0
T11	682	1
T12	835	0
T13	6874	0
T39	0	2
T40	0	1
T41	0	3
T43	0	1
T45	0	1
T49	0	1
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T150	0	2
T179	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8421531	53
T11	682	1
T12	835	0
T13	6874	0
T39	0	1
T40	0	1
T41	0	3
T43	0	1
T45	0	1
T46	621	0
T62	1681	0
T64	2628	0
T68	526	0
T79	0	1
T120	405	0
T121	651	0
T122	426	0
T150	0	2
T151	0	1
T179	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8421531	53
T11	682	1
T12	835	0
T13	6874	0
T39	0	1
T40	0	1
T41	0	3
T43	0	1
T45	0	1
T46	621	0
T62	1681	0
T64	2628	0
T68	526	0
T79	0	1
T120	405	0
T121	651	0
T122	426	0
T150	0	2
T151	0	1
T179	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8421531	53
T11	682	1
T12	835	0
T13	6874	0
T39	0	1
T40	0	1
T41	0	3
T43	0	1
T45	0	1
T46	621	0
T62	1681	0
T64	2628	0
T68	526	0
T79	0	1
T120	405	0
T121	651	0
T122	426	0
T150	0	2
T151	0	1
T179	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8421531	4635
T11	682	175
T12	835	0
T13	6874	0
T39	0	40
T40	0	228
T41	0	62
T43	0	16
T45	0	274
T46	621	0
T62	1681	0
T64	2628	0
T68	526	0
T79	0	48
T120	405	0
T121	651	0
T122	426	0
T150	0	346
T151	0	159
T179	0	122

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8421531	7780089
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8421531	33
T39	621	1
T41	0	3
T43	0	1
T47	506	0
T48	13740	0
T54	3113	0
T111	406	0
T112	404	0
T132	0	3
T146	0	1
T149	0	2
T150	0	1
T151	0	1
T177	0	1
T178	0	1
T212	426	0
T213	425	0
T214	423	0
T215	494	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T49,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T49,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T64
1	0	Covered	T5,T6,T1
1	1	Covered	T8,T49,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T43,T44
0	1	Covered	T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T43,T44
0	1	Covered	T8,T203,T146
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T43,T44
1	-	Covered	T8,T203,T146

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T49,T43
DetectSt	168	Covered	T8,T43,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T43,T44
DebounceSt->IdleSt	163	Covered	T49,T209
DetectSt->IdleSt	186	Covered	T155
DetectSt->StableSt	191	Covered	T8,T43,T44
IdleSt->DebounceSt	148	Covered	T8,T49,T43
StableSt->IdleSt	206	Covered	T8,T43,T44

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T49,T43
0	1	Covered	T8,T49,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T43,T44
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T49,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T43,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T209
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T49,T43
DetectSt	-	-	-	-	1	-	-	Covered	T155
DetectSt	-	-	-	-	0	1	-	Covered	T8,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T203,T146
StableSt	-	-	-	-	-	-	0	Covered	T8,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	72	0	0
CntIncr_A	8421531	65052	0	0
CntNoWrap_A	8421531	7777758	0	0
DetectStDropOut_A	8421531	1	0	0
DetectedOut_A	8421531	2605	0	0
DetectedPulseOut_A	8421531	34	0	0
DisabledIdleSt_A	8421531	7635513	0	0
DisabledNoDetection_A	8421531	7637721	0	0
EnterDebounceSt_A	8421531	37	0	0
EnterDetectSt_A	8421531	35	0	0
EnterStableSt_A	8421531	34	0	0
PulseIsPulse_A	8421531	34	0	0
StayInStableSt	8421531	2553	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	5966	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	15	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8421531	72
T8	731	4
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	2
T44	0	2
T49	0	1
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	2
T144	0	2
T146	0	6
T153	0	2
T178	0	2
T203	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	8421531	65052
T8	731	70
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	54
T44	0	12
T49	0	16
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	93
T144	0	17
T146	0	225
T153	0	53
T178	0	60
T203	0	32

CntNoWrap_A

Name	Attempts	Real Successes
Total	8421531	7777758
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8421531	1
T155	543	1
T216	2920	0
T217	5849	0
T218	503	0
T219	502	0
T220	402	0
T221	502	0
T222	35821	0
T223	1343	0
T224	502	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8421531	2605
T8	731	81
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	40
T44	0	39
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	42
T144	0	126
T146	0	121
T153	0	201
T178	0	26
T189	0	8
T203	0	99

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8421531	34
T8	731	2
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	1
T44	0	1
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	1
T144	0	1
T146	0	3
T153	0	1
T178	0	1
T189	0	1
T203	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8421531	7635513
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8421531	7637721
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8421531	37
T8	731	2
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	1
T44	0	1
T49	0	1
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	1
T144	0	1
T146	0	3
T153	0	1
T178	0	1
T203	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8421531	35
T8	731	2
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	1
T44	0	1
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	1
T144	0	1
T146	0	3
T153	0	1
T178	0	1
T189	0	1
T203	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	8421531	34
T8	731	2
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	1
T44	0	1
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	1
T144	0	1
T146	0	3
T153	0	1
T178	0	1
T189	0	1
T203	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8421531	34
T8	731	2
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	1
T44	0	1
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	1
T144	0	1
T146	0	3
T153	0	1
T178	0	1
T189	0	1
T203	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	8421531	2553
T8	731	78
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T43	0	38
T44	0	37
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	41
T144	0	124
T146	0	117
T153	0	199
T178	0	25
T189	0	7
T203	0	96

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8421531	5966
T1	8442	21
T2	0	60
T5	529	4
T6	421	2
T14	421	1
T15	503	5
T16	963	0
T17	2839	10
T18	21599	35
T19	528	5
T20	495	7

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8421531	7780089
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8421531	15
T8	731	1
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T62	1681	0
T68	526	0
T120	405	0
T121	651	0
T132	0	1
T146	0	2
T178	0	1
T189	0	1
T191	0	1
T192	0	1
T203	0	1
T206	0	1
T225	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T77,T166,T191
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T8,T70,T45
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T11
1	-	Covered	T8,T70,T45

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T9
DetectSt	168	Covered	T8,T9,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T11
DebounceSt->IdleSt	163	Covered	T2,T49,T203
DetectSt->IdleSt	186	Covered	T77,T166,T191
DetectSt->StableSt	191	Covered	T8,T9,T11
IdleSt->DebounceSt	148	Covered	T2,T8,T9
StableSt->IdleSt	206	Covered	T8,T64,T70

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T9
0	1	Covered	T2,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T11
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T203,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T77,T166,T191
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T70,T45
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	108	0	0
CntIncr_A	8421531	3213	0	0
CntNoWrap_A	8421531	7777722	0	0
DetectStDropOut_A	8421531	3	0	0
DetectedOut_A	8421531	4815	0	0
DetectedPulseOut_A	8421531	48	0	0
DisabledIdleSt_A	8421531	7636667	0	0
DisabledNoDetection_A	8421531	7638882	0	0
EnterDebounceSt_A	8421531	57	0	0
EnterDetectSt_A	8421531	51	0	0
EnterStableSt_A	8421531	48	0	0
PulseIsPulse_A	8421531	48	0	0
StayInStableSt	8421531	4745	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	25	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8421531	108
T2	19005	1
T3	831	0
T7	6439	0
T8	731	2
T9	0	2
T11	0	2
T25	1734	0
T26	9572	0
T38	0	2
T39	0	2
T45	0	4
T49	0	1
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T64	0	2
T70	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8421531	3213
T2	19005	10
T3	831	0
T7	6439	0
T8	731	35
T9	0	99
T11	0	95
T25	1734	0
T26	9572	0
T38	0	61
T39	0	18
T45	0	72
T49	0	15
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T64	0	14
T70	0	82

CntNoWrap_A

Name	Attempts	Real Successes
Total	8421531	7777722
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8421531	3
T77	958	1
T86	21392	0
T149	8300	0
T166	0	1
T178	797	0
T191	0	1
T226	17086	0
T227	493	0
T228	12189	0
T229	422	0
T230	29718	0
T231	493	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8421531	4815
T8	731	102
T9	952	443
T10	17392	0
T11	682	177
T12	835	0
T13	6874	0
T38	0	40
T39	0	61
T45	0	47
T62	1681	0
T64	0	69
T68	526	0
T70	0	67
T73	0	215
T120	405	0
T121	651	0
T142	0	11

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8421531	48
T8	731	1
T9	952	1
T10	17392	0
T11	682	1
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T45	0	2
T62	1681	0
T64	0	1
T68	526	0
T70	0	1
T73	0	3
T120	405	0
T121	651	0
T142	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8421531	7636667
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8421531	7638882
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8421531	57
T2	19005	1
T3	831	0
T7	6439	0
T8	731	1
T9	0	1
T11	0	1
T25	1734	0
T26	9572	0
T38	0	1
T39	0	1
T45	0	2
T49	0	1
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T64	0	1
T70	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8421531	51
T8	731	1
T9	952	1
T10	17392	0
T11	682	1
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T45	0	2
T62	1681	0
T64	0	1
T68	526	0
T70	0	1
T73	0	3
T120	405	0
T121	651	0
T142	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8421531	48
T8	731	1
T9	952	1
T10	17392	0
T11	682	1
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T45	0	2
T62	1681	0
T64	0	1
T68	526	0
T70	0	1
T73	0	3
T120	405	0
T121	651	0
T142	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8421531	48
T8	731	1
T9	952	1
T10	17392	0
T11	682	1
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T45	0	2
T62	1681	0
T64	0	1
T68	526	0
T70	0	1
T73	0	3
T120	405	0
T121	651	0
T142	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8421531	4745
T8	731	101
T9	952	441
T10	17392	0
T11	682	175
T12	835	0
T13	6874	0
T38	0	38
T39	0	60
T45	0	45
T62	1681	0
T64	0	67
T68	526	0
T70	0	66
T73	0	210
T120	405	0
T121	651	0
T142	0	10

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8421531	7780089
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8421531	25
T8	731	1
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T39	0	1
T45	0	2
T62	1681	0
T68	526	0
T70	0	1
T73	0	1
T120	405	0
T121	651	0
T142	0	1
T143	0	2
T177	0	1
T203	0	1
T232	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T49,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T40,T49,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T5,T6,T1
1	1	Covered	T40,T49,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T40,T44,T143
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T41,T42
1	-	Covered	T40,T44,T143

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T49,T41
DetectSt	168	Covered	T40,T41,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T40,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T41,T42
DebounceSt->IdleSt	163	Covered	T49,T151
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T41,T42
IdleSt->DebounceSt	148	Covered	T40,T49,T41
StableSt->IdleSt	206	Covered	T40,T44,T143

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T49,T41
0	1	Covered	T40,T49,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T49,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T151
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T49,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T44,T143
StableSt	-	-	-	-	-	-	0	Covered	T40,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	64	0	0
CntIncr_A	8421531	117847	0	0
CntNoWrap_A	8421531	7777766	0	0
DetectStDropOut_A	8421531	0	0	0
DetectedOut_A	8421531	53493	0	0
DetectedPulseOut_A	8421531	31	0	0
DisabledIdleSt_A	8421531	7294272	0	0
DisabledNoDetection_A	8421531	7296483	0	0
EnterDebounceSt_A	8421531	33	0	0
EnterDetectSt_A	8421531	31	0	0
EnterStableSt_A	8421531	31	0	0
PulseIsPulse_A	8421531	31	0	0
StayInStableSt	8421531	53444	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	5950	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	12	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8421531	64
T35	12511	0
T36	12707	0
T40	7952	4
T41	0	2
T42	0	2
T44	0	2
T45	771	0
T49	0	1
T52	33796	0
T66	491	0
T80	2188	0
T94	522	0
T95	548	0
T143	0	4
T144	0	2
T151	0	1
T177	0	2
T203	0	4
T233	1012	0

CntIncr_A

Name	Attempts	Real Successes
Total	8421531	117847
T35	12511	0
T36	12707	0
T40	7952	60
T41	0	36
T42	0	59
T44	0	12
T45	771	0
T49	0	15
T52	33796	0
T66	491	0
T80	2188	0
T94	522	0
T95	548	0
T143	0	42
T144	0	17
T151	0	70
T177	0	71
T203	0	32
T233	1012	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	8421531	7777766
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8421531	53493
T35	12511	0
T36	12707	0
T40	7952	80
T41	0	100
T42	0	51
T44	0	1
T45	771	0
T52	33796	0
T66	491	0
T77	0	127
T80	2188	0
T94	522	0
T95	548	0
T143	0	99
T144	0	85
T146	0	1
T177	0	40
T203	0	162
T233	1012	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8421531	31
T35	12511	0
T36	12707	0
T40	7952	2
T41	0	1
T42	0	1
T44	0	1
T45	771	0
T52	33796	0
T66	491	0
T77	0	3
T80	2188	0
T94	522	0
T95	548	0
T143	0	2
T144	0	1
T146	0	1
T177	0	1
T203	0	2
T233	1012	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8421531	7294272
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8421531	7296483
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8421531	33
T35	12511	0
T36	12707	0
T40	7952	2
T41	0	1
T42	0	1
T44	0	1
T45	771	0
T49	0	1
T52	33796	0
T66	491	0
T80	2188	0
T94	522	0
T95	548	0
T143	0	2
T144	0	1
T151	0	1
T177	0	1
T203	0	2
T233	1012	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8421531	31
T35	12511	0
T36	12707	0
T40	7952	2
T41	0	1
T42	0	1
T44	0	1
T45	771	0
T52	33796	0
T66	491	0
T77	0	3
T80	2188	0
T94	522	0
T95	548	0
T143	0	2
T144	0	1
T146	0	1
T177	0	1
T203	0	2
T233	1012	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	8421531	31
T35	12511	0
T36	12707	0
T40	7952	2
T41	0	1
T42	0	1
T44	0	1
T45	771	0
T52	33796	0
T66	491	0
T77	0	3
T80	2188	0
T94	522	0
T95	548	0
T143	0	2
T144	0	1
T146	0	1
T177	0	1
T203	0	2
T233	1012	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8421531	31
T35	12511	0
T36	12707	0
T40	7952	2
T41	0	1
T42	0	1
T44	0	1
T45	771	0
T52	33796	0
T66	491	0
T77	0	3
T80	2188	0
T94	522	0
T95	548	0
T143	0	2
T144	0	1
T146	0	1
T177	0	1
T203	0	2
T233	1012	0

StayInStableSt

Name	Attempts	Real Successes
Total	8421531	53444
T35	12511	0
T36	12707	0
T40	7952	77
T41	0	98
T42	0	49
T45	771	0
T52	33796	0
T66	491	0
T77	0	123
T80	2188	0
T94	522	0
T95	548	0
T132	0	125
T143	0	96
T144	0	84
T147	0	98
T177	0	38
T203	0	159
T233	1012	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8421531	5950
T1	8442	28
T2	0	60
T5	529	4
T6	421	3
T14	421	1
T15	503	3
T16	963	0
T17	2839	14
T18	21599	29
T19	528	4
T20	495	11

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8421531	7780089
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8421531	12
T35	12511	0
T36	12707	0
T40	7952	1
T44	0	1
T45	771	0
T52	33796	0
T66	491	0
T77	0	2
T80	2188	0
T94	522	0
T95	548	0
T132	0	2
T141	0	1
T143	0	1
T144	0	1
T146	0	1
T166	0	1
T203	0	1
T233	1012	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T5,T6,T1
1	1	Covered	T2,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T2,T3,T70
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T11
1	-	Covered	T2,T3,T70

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T11
DetectSt	168	Covered	T2,T3,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T11
DebounceSt->IdleSt	163	Covered	T49
DetectSt->IdleSt	186	Covered	T78
DetectSt->StableSt	191	Covered	T2,T3,T11
IdleSt->DebounceSt	148	Covered	T2,T3,T11
StableSt->IdleSt	206	Covered	T2,T3,T70

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T11
0	1	Covered	T2,T3,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T11
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T70
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	135	0	0
CntIncr_A	8421531	134226	0	0
CntNoWrap_A	8421531	7777695	0	0
DetectStDropOut_A	8421531	1	0	0
DetectedOut_A	8421531	4972	0	0
DetectedPulseOut_A	8421531	66	0	0
DisabledIdleSt_A	8421531	7500294	0	0
DisabledNoDetection_A	8421531	7502503	0	0
EnterDebounceSt_A	8421531	68	0	0
EnterDetectSt_A	8421531	67	0	0
EnterStableSt_A	8421531	66	0	0
PulseIsPulse_A	8421531	66	0	0
StayInStableSt	8421531	4881	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	40	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8421531	135
T2	19005	6
T3	831	4
T7	6439	0
T8	731	0
T11	0	2
T25	1734	0
T26	9572	0
T38	0	2
T39	0	4
T40	0	2
T45	0	6
T46	0	2
T49	0	1
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8421531	134226
T2	19005	114
T3	831	142
T7	6439	0
T8	731	0
T11	0	95
T25	1734	0
T26	9572	0
T38	0	61
T39	0	36
T40	0	30
T45	0	108
T46	0	95
T49	0	14
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	82

CntNoWrap_A

Name	Attempts	Real Successes
Total	8421531	7777695
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8421531	1
T78	908	1
T234	898	0
T235	753	0
T236	505	0
T237	122100	0
T238	19888	0
T239	505	0
T240	1983	0
T241	2340	0
T242	6776	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8421531	4972
T2	19005	124
T3	831	168
T7	6439	0
T8	731	0
T11	0	45
T25	1734	0
T26	9572	0
T38	0	46
T39	0	81
T40	0	157
T45	0	120
T46	0	117
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	68
T73	0	102

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8421531	66
T2	19005	3
T3	831	2
T7	6439	0
T8	731	0
T11	0	1
T25	1734	0
T26	9572	0
T38	0	1
T39	0	2
T40	0	1
T45	0	3
T46	0	1
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	1
T73	0	3

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8421531	7500294
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8421531	7502503
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8421531	68
T2	19005	3
T3	831	2
T7	6439	0
T8	731	0
T11	0	1
T25	1734	0
T26	9572	0
T38	0	1
T39	0	2
T40	0	1
T45	0	3
T46	0	1
T49	0	1
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8421531	67
T2	19005	3
T3	831	2
T7	6439	0
T8	731	0
T11	0	1
T25	1734	0
T26	9572	0
T38	0	1
T39	0	2
T40	0	1
T45	0	3
T46	0	1
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	1
T73	0	3

EnterStableSt_A

Name	Attempts	Real Successes
Total	8421531	66
T2	19005	3
T3	831	2
T7	6439	0
T8	731	0
T11	0	1
T25	1734	0
T26	9572	0
T38	0	1
T39	0	2
T40	0	1
T45	0	3
T46	0	1
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	1
T73	0	3

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8421531	66
T2	19005	3
T3	831	2
T7	6439	0
T8	731	0
T11	0	1
T25	1734	0
T26	9572	0
T38	0	1
T39	0	2
T40	0	1
T45	0	3
T46	0	1
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	1
T73	0	3

StayInStableSt

Name	Attempts	Real Successes
Total	8421531	4881
T2	19005	120
T3	831	165
T7	6439	0
T8	731	0
T11	0	43
T25	1734	0
T26	9572	0
T38	0	45
T39	0	78
T40	0	156
T45	0	116
T46	0	115
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	67
T73	0	98

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8421531	7780089
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8421531	40
T2	19005	2
T3	831	1
T7	6439	0
T8	731	0
T25	1734	0
T26	9572	0
T38	0	1
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T45	0	2
T56	628	0
T57	404	0
T58	521	0
T59	522	0
T70	0	1
T73	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T5,T6,T1
1	1	Covered	T8,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T38,T39
0	1	Covered	T8,T39,T179
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T38,T39
1	-	Covered	T8,T39,T179

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T38,T39
DetectSt	168	Covered	T8,T38,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T38,T39
DebounceSt->IdleSt	163	Covered	T49,T234,T165
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T38,T39
IdleSt->DebounceSt	148	Covered	T8,T38,T39
StableSt->IdleSt	206	Covered	T8,T38,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T38,T39
0	1	Covered	T8,T38,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T38,T39
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T234,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T38,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T39,T179
StableSt	-	-	-	-	-	-	0	Covered	T8,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	65	0	0
CntIncr_A	8421531	195356	0	0
CntNoWrap_A	8421531	7777765	0	0
DetectStDropOut_A	8421531	0	0	0
DetectedOut_A	8421531	1784	0	0
DetectedPulseOut_A	8421531	31	0	0
DisabledIdleSt_A	8421531	7376191	0	0
DisabledNoDetection_A	8421531	7378408	0	0
EnterDebounceSt_A	8421531	34	0	0
EnterDetectSt_A	8421531	31	0	0
EnterStableSt_A	8421531	31	0	0
PulseIsPulse_A	8421531	31	0	0
StayInStableSt	8421531	1739	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8421531	6773	0	0
gen_low_level_sva.LowLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	16	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8421531	65
T8	731	2
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	2
T39	0	2
T41	0	2
T44	0	2
T49	0	1
T62	1681	0
T68	526	0
T73	0	2
T79	0	2
T120	405	0
T121	651	0
T144	0	2
T179	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8421531	195356
T8	731	35
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	61
T39	0	18
T41	0	36
T44	0	12
T49	0	15
T62	1681	0
T68	526	0
T73	0	71
T79	0	13
T120	405	0
T121	651	0
T144	0	17
T179	0	59

CntNoWrap_A

Name	Attempts	Real Successes
Total	8421531	7777765
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8421531	1784
T8	731	94
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	40
T39	0	64
T41	0	40
T44	0	38
T62	1681	0
T68	526	0
T73	0	37
T79	0	49
T120	405	0
T121	651	0
T144	0	63
T153	0	41
T179	0	39

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8421531	31
T8	731	1
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T41	0	1
T44	0	1
T62	1681	0
T68	526	0
T73	0	1
T79	0	1
T120	405	0
T121	651	0
T144	0	1
T153	0	1
T179	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8421531	7376191
T1	8442	8039
T4	493	92
T5	529	128
T6	421	20
T14	421	20
T15	503	102
T16	963	562
T17	2839	434
T18	21599	21198
T19	528	127

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8421531	7378408
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8421531	34
T8	731	1
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T41	0	1
T44	0	1
T49	0	1
T62	1681	0
T68	526	0
T73	0	1
T79	0	1
T120	405	0
T121	651	0
T144	0	1
T179	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8421531	31
T8	731	1
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T41	0	1
T44	0	1
T62	1681	0
T68	526	0
T73	0	1
T79	0	1
T120	405	0
T121	651	0
T144	0	1
T153	0	1
T179	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8421531	31
T8	731	1
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T41	0	1
T44	0	1
T62	1681	0
T68	526	0
T73	0	1
T79	0	1
T120	405	0
T121	651	0
T144	0	1
T153	0	1
T179	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8421531	31
T8	731	1
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	1
T39	0	1
T41	0	1
T44	0	1
T62	1681	0
T68	526	0
T73	0	1
T79	0	1
T120	405	0
T121	651	0
T144	0	1
T153	0	1
T179	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8421531	1739
T8	731	93
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T38	0	38
T39	0	63
T41	0	38
T44	0	36
T62	1681	0
T68	526	0
T73	0	35
T79	0	47
T120	405	0
T121	651	0
T144	0	62
T153	0	40
T179	0	38

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8421531	6773
T1	8442	28
T5	529	6
T6	421	1
T14	421	4
T15	503	6
T16	963	0
T17	2839	18
T18	21599	32
T19	528	6
T20	495	8
T21	0	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8421531	7780089
T1	8442	8041
T4	493	93
T5	529	129
T6	421	21
T14	421	21
T15	503	103
T16	963	563
T17	2839	439
T18	21599	21199
T19	528	128

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8421531	16
T8	731	1
T9	952	0
T10	17392	0
T11	682	0
T12	835	0
T13	6874	0
T39	0	1
T62	1681	0
T68	526	0
T78	0	2
T120	405	0
T121	651	0
T141	0	1
T144	0	1
T148	0	1
T153	0	1
T179	0	1
T206	0	1
T209	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr