Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T26
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T26
1	0	Covered	T1,T18,T26
1	1	Covered	T1,T18,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T26
0	1	Covered	T18,T26,T13
1	0	Covered	T1,T18,T26

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T48,T37
0	1	Covered	T48,T37,T49
1	0	Covered	T49,T76,T243

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T48,T37
1	-	Covered	T48,T37,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T26
DetectSt	168	Covered	T1,T18,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T47,T48,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T26
DebounceSt->IdleSt	163	Covered	T49,T244,T245
DetectSt->IdleSt	186	Covered	T1,T18,T26
DetectSt->StableSt	191	Covered	T47,T48,T37
IdleSt->DebounceSt	148	Covered	T1,T18,T26
StableSt->IdleSt	206	Covered	T48,T37,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T26
0	1	Covered	T1,T18,T26
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T18,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T244,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T26
DetectSt	-	-	-	-	1	-	-	Covered	T1,T18,T26
DetectSt	-	-	-	-	0	1	-	Covered	T47,T48,T37
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T26
StableSt	-	-	-	-	-	-	1	Covered	T48,T37,T49
StableSt	-	-	-	-	-	-	0	Covered	T47,T48,T37
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	2896	0	0
CntIncr_A	8421531	106915	0	0
CntNoWrap_A	8421531	7774934	0	0
DetectStDropOut_A	8421531	466	0	0
DetectedOut_A	8421531	63955	0	0
DetectedPulseOut_A	8421531	782	0	0
DisabledIdleSt_A	8421531	7318790	0	0
DisabledNoDetection_A	8421531	7320886	0	0
EnterDebounceSt_A	8421531	1473	0	0
EnterDetectSt_A	8421531	1423	0	0
EnterStableSt_A	8421531	782	0	0
PulseIsPulse_A	8421531	782	0	0
StayInStableSt	8421531	63098	0	0
gen_high_event_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	663	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2896	0	0
T1	8442	14	0	0
T2	19005	0	0	0
T13	0	16	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	24	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	28	0	0
T37	0	52	0	0
T47	0	2	0	0
T48	0	46	0	0
T50	0	6	0	0
T51	0	42	0	0
T71	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	106915	0	0
T1	8442	349	0	0
T2	19005	0	0	0
T13	0	464	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	3760	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	1017	0	0
T37	0	1040	0	0
T47	0	21	0	0
T48	0	1472	0	0
T50	0	148	0	0
T51	0	786	0	0
T71	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7774934	0	0
T1	8442	8025	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21174	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	466	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T13	0	4	0	0
T18	21599	4	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T26	0	12	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	17	0	0
T56	628	0	0	0
T57	404	0	0	0
T246	0	24	0	0
T247	0	12	0	0
T248	0	20	0	0
T249	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	63955	0	0
T37	30300	3121	0	0
T47	506	81	0	0
T48	13740	2724	0	0
T49	0	285	0	0
T71	0	74	0	0
T106	38375	0	0	0
T109	0	662	0	0
T110	0	1504	0	0
T111	406	0	0	0
T112	404	0	0	0
T113	649	0	0	0
T114	423	0	0	0
T116	521	0	0	0
T182	0	4640	0	0
T250	0	2321	0	0
T251	0	1995	0	0
T252	449	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	782	0	0
T37	30300	26	0	0
T47	506	1	0	0
T48	13740	23	0	0
T49	0	5	0	0
T71	0	1	0	0
T106	38375	0	0	0
T109	0	6	0	0
T110	0	24	0	0
T111	406	0	0	0
T112	404	0	0	0
T113	649	0	0	0
T114	423	0	0	0
T116	521	0	0	0
T182	0	26	0	0
T250	0	25	0	0
T251	0	22	0	0
T252	449	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7318790	0	0
T1	8442	5375	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	5338	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7320886	0	0
T1	8442	5376	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	5338	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1473	0	0
T1	8442	7	0	0
T2	19005	0	0	0
T13	0	8	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	12	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	14	0	0
T37	0	26	0	0
T47	0	1	0	0
T48	0	23	0	0
T50	0	3	0	0
T51	0	21	0	0
T71	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1423	0	0
T1	8442	7	0	0
T2	19005	0	0	0
T13	0	8	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	12	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	14	0	0
T37	0	26	0	0
T47	0	1	0	0
T48	0	23	0	0
T50	0	3	0	0
T51	0	21	0	0
T71	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	782	0	0
T37	30300	26	0	0
T47	506	1	0	0
T48	13740	23	0	0
T49	0	5	0	0
T71	0	1	0	0
T106	38375	0	0	0
T109	0	6	0	0
T110	0	24	0	0
T111	406	0	0	0
T112	404	0	0	0
T113	649	0	0	0
T114	423	0	0	0
T116	521	0	0	0
T182	0	26	0	0
T250	0	25	0	0
T251	0	22	0	0
T252	449	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	782	0	0
T37	30300	26	0	0
T47	506	1	0	0
T48	13740	23	0	0
T49	0	5	0	0
T71	0	1	0	0
T106	38375	0	0	0
T109	0	6	0	0
T110	0	24	0	0
T111	406	0	0	0
T112	404	0	0	0
T113	649	0	0	0
T114	423	0	0	0
T116	521	0	0	0
T182	0	26	0	0
T250	0	25	0	0
T251	0	22	0	0
T252	449	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	63098	0	0
T37	30300	3084	0	0
T47	506	79	0	0
T48	13740	2699	0	0
T49	0	280	0	0
T71	0	72	0	0
T106	38375	0	0	0
T109	0	656	0	0
T110	0	1479	0	0
T111	406	0	0	0
T112	404	0	0	0
T113	649	0	0	0
T114	423	0	0	0
T116	521	0	0	0
T182	0	4613	0	0
T250	0	2294	0	0
T251	0	1972	0	0
T252	449	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	663	0	0
T37	30300	15	0	0
T48	13740	21	0	0
T49	0	4	0	0
T106	38375	0	0	0
T109	0	6	0	0
T110	0	23	0	0
T111	406	0	0	0
T112	404	0	0	0
T113	649	0	0	0
T114	423	0	0	0
T116	521	0	0	0
T182	0	25	0	0
T250	0	23	0	0
T251	0	21	0	0
T252	449	0	0	0
T253	0	8	0	0
T254	0	13	0	0
T255	435	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T10
1	0	Covered	T1,T17,T18
1	1	Covered	T2,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T31
0	1	Covered	T49,T81,T82
1	0	Covered	T49,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T31
0	1	Covered	T7,T10,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T31
1	-	Covered	T7,T10,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T10
DetectSt	168	Covered	T7,T10,T31
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T10,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T31
DebounceSt->IdleSt	163	Covered	T2,T10,T35
DetectSt->IdleSt	186	Covered	T49,T81,T82
DetectSt->StableSt	191	Covered	T7,T10,T31
IdleSt->DebounceSt	148	Covered	T2,T7,T10
StableSt->IdleSt	206	Covered	T7,T10,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T10
0	1	Covered	T2,T7,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T31
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T10,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T49,T81,T82
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T31
DetectSt	-	-	-	-	0	0	-	Covered	T7,T10,T31
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T31
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	894	0	0
CntIncr_A	8421531	45122	0	0
CntNoWrap_A	8421531	7776936	0	0
DetectStDropOut_A	8421531	56	0	0
DetectedOut_A	8421531	13148	0	0
DetectedPulseOut_A	8421531	348	0	0
DisabledIdleSt_A	8421531	7417734	0	0
DisabledNoDetection_A	8421531	7419293	0	0
EnterDebounceSt_A	8421531	490	0	0
EnterDetectSt_A	8421531	407	0	0
EnterStableSt_A	8421531	348	0	0
PulseIsPulse_A	8421531	348	0	0
StayInStableSt	8421531	12776	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	321	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	894	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	12	0	0
T8	731	0	0	0
T10	0	7	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T31	0	2	0	0
T35	0	3	0	0
T36	0	5	0	0
T47	0	2	0	0
T48	0	2	0	0
T52	0	4	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T80	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	45122	0	0
T2	19005	20	0	0
T3	831	0	0	0
T7	6439	558	0	0
T8	731	0	0	0
T10	0	95	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T31	0	25	0	0
T35	0	298	0	0
T36	0	134	0	0
T38	0	20	0	0
T47	0	25	0	0
T52	0	234	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T80	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7776936	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	56	0	0
T49	5832	1	0	0
T73	8079	0	0	0
T81	0	6	0	0
T82	0	4	0	0
T83	0	1	0	0
T84	0	9	0	0
T86	0	8	0	0
T88	0	3	0	0
T89	0	3	0	0
T90	0	1	0	0
T91	0	1	0	0
T98	422	0	0	0
T99	422	0	0	0
T100	523	0	0	0
T101	23131	0	0	0
T102	576	0	0	0
T103	796	0	0	0
T104	504	0	0	0
T105	2341	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	13148	0	0
T7	6439	232	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	9	0	0
T11	682	0	0	0
T26	9572	0	0	0
T31	0	3	0	0
T35	0	7	0	0
T36	0	7	0	0
T37	0	344	0	0
T47	0	3	0	0
T48	0	53	0	0
T52	0	166	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T106	0	874	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	348	0	0
T7	6439	6	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	3	0	0
T11	682	0	0	0
T26	9572	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	6	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T106	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7417734	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21198	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7419293	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	490	0	0
T2	19005	1	0	0
T3	831	0	0	0
T7	6439	6	0	0
T8	731	0	0	0
T10	0	4	0	0
T25	1734	0	0	0
T26	9572	0	0	0
T31	0	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T38	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T80	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	407	0	0
T7	6439	6	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	3	0	0
T11	682	0	0	0
T26	9572	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	6	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T106	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	348	0	0
T7	6439	6	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	3	0	0
T11	682	0	0	0
T26	9572	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	6	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T106	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	348	0	0
T7	6439	6	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	3	0	0
T11	682	0	0	0
T26	9572	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	6	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T106	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	12776	0	0
T7	6439	226	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	6	0	0
T11	682	0	0	0
T26	9572	0	0	0
T31	0	2	0	0
T35	0	6	0	0
T36	0	5	0	0
T37	0	338	0	0
T47	0	2	0	0
T48	0	51	0	0
T52	0	164	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T106	0	864	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	321	0	0
T7	6439	6	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	3	0	0
T11	682	0	0	0
T26	9572	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	6	0	0
T47	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T71	0	1	0	0
T106	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T26
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T26
1	0	Covered	T1,T18,T26
1	1	Covered	T1,T18,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T26
0	1	Covered	T1,T26,T50
1	0	Covered	T1,T26,T13

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T48,T49
0	1	Covered	T18,T48,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T48,T49
1	-	Covered	T18,T48,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T26
DetectSt	168	Covered	T1,T18,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T18,T48,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T26
DebounceSt->IdleSt	163	Covered	T49,T244,T245
DetectSt->IdleSt	186	Covered	T1,T26,T13
DetectSt->StableSt	191	Covered	T18,T48,T49
IdleSt->DebounceSt	148	Covered	T1,T18,T26
StableSt->IdleSt	206	Covered	T18,T48,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T26
0	1	Covered	T1,T18,T26
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T18,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T244,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T26
DetectSt	-	-	-	-	1	-	-	Covered	T1,T26,T13
DetectSt	-	-	-	-	0	1	-	Covered	T18,T48,T49
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T26
StableSt	-	-	-	-	-	-	1	Covered	T18,T48,T49
StableSt	-	-	-	-	-	-	0	Covered	T18,T48,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	2563	0	0
CntIncr_A	8421531	110249	0	0
CntNoWrap_A	8421531	7775267	0	0
DetectStDropOut_A	8421531	388	0	0
DetectedOut_A	8421531	66079	0	0
DetectedPulseOut_A	8421531	731	0	0
DisabledIdleSt_A	8421531	7310454	0	0
DisabledNoDetection_A	8421531	7312545	0	0
EnterDebounceSt_A	8421531	1306	0	0
EnterDetectSt_A	8421531	1257	0	0
EnterStableSt_A	8421531	731	0	0
PulseIsPulse_A	8421531	731	0	0
StayInStableSt	8421531	65268	0	0
gen_high_event_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	651	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2563	0	0
T1	8442	36	0	0
T2	19005	0	0	0
T13	0	4	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	18	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	28	0	0
T37	0	8	0	0
T48	0	44	0	0
T49	0	16	0	0
T50	0	26	0	0
T51	0	42	0	0
T72	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	110249	0	0
T1	8442	895	0	0
T2	19005	0	0	0
T13	0	117	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	2169	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	1018	0	0
T37	0	222	0	0
T48	0	1804	0	0
T49	0	258	0	0
T50	0	644	0	0
T51	0	786	0	0
T72	0	521	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7775267	0	0
T1	8442	8003	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21180	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	388	0	0
T1	8442	5	0	0
T2	19005	0	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	0	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	11	0	0
T49	0	1	0	0
T50	0	13	0	0
T51	0	17	0	0
T72	0	6	0	0
T246	0	15	0	0
T247	0	23	0	0
T248	0	2	0	0
T249	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	66079	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T18	21599	3889	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T48	0	715	0	0
T49	0	252	0	0
T56	628	0	0	0
T57	404	0	0	0
T109	0	988	0	0
T110	0	1864	0	0
T182	0	2268	0	0
T250	0	2140	0	0
T251	0	102	0	0
T253	0	1039	0	0
T256	0	2965	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	731	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T18	21599	9	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T48	0	22	0	0
T49	0	5	0	0
T56	628	0	0	0
T57	404	0	0	0
T109	0	11	0	0
T110	0	24	0	0
T182	0	18	0	0
T250	0	20	0	0
T251	0	3	0	0
T253	0	25	0	0
T256	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7310454	0	0
T1	8442	5375	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	2093	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7312545	0	0
T1	8442	5376	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	2093	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1306	0	0
T1	8442	18	0	0
T2	19005	0	0	0
T13	0	2	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	9	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	14	0	0
T37	0	4	0	0
T48	0	22	0	0
T49	0	9	0	0
T50	0	13	0	0
T51	0	21	0	0
T72	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1257	0	0
T1	8442	18	0	0
T2	19005	0	0	0
T13	0	2	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	9	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	14	0	0
T37	0	4	0	0
T48	0	22	0	0
T49	0	7	0	0
T50	0	13	0	0
T51	0	21	0	0
T72	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	731	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T18	21599	9	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T48	0	22	0	0
T49	0	5	0	0
T56	628	0	0	0
T57	404	0	0	0
T109	0	11	0	0
T110	0	24	0	0
T182	0	18	0	0
T250	0	20	0	0
T251	0	3	0	0
T253	0	25	0	0
T256	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	731	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T18	21599	9	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T48	0	22	0	0
T49	0	5	0	0
T56	628	0	0	0
T57	404	0	0	0
T109	0	11	0	0
T110	0	24	0	0
T182	0	18	0	0
T250	0	20	0	0
T251	0	3	0	0
T253	0	25	0	0
T256	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	65268	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T18	21599	3880	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T48	0	692	0	0
T49	0	247	0	0
T56	628	0	0	0
T57	404	0	0	0
T109	0	975	0	0
T110	0	1839	0	0
T182	0	2250	0	0
T250	0	2118	0	0
T251	0	99	0	0
T253	0	1014	0	0
T256	0	2931	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	651	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T18	21599	9	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T48	0	21	0	0
T49	0	5	0	0
T56	628	0	0	0
T57	404	0	0	0
T109	0	9	0	0
T110	0	23	0	0
T182	0	18	0	0
T250	0	18	0	0
T251	0	3	0	0
T253	0	25	0	0
T256	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T18,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T7,T10
1	0	Covered	T1,T17,T18
1	1	Covered	T18,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T7,T10
0	1	Covered	T7,T36,T101
1	0	Covered	T49,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T10,T52
0	1	Covered	T18,T10,T52
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T10,T52
1	-	Covered	T18,T10,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T7,T10
DetectSt	168	Covered	T18,T7,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T18,T10,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T7,T10
DebounceSt->IdleSt	163	Covered	T35,T36,T106
DetectSt->IdleSt	186	Covered	T7,T36,T49
DetectSt->StableSt	191	Covered	T18,T10,T52
IdleSt->DebounceSt	148	Covered	T18,T7,T10
StableSt->IdleSt	206	Covered	T18,T10,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T7,T10
0	1	Covered	T18,T7,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T7,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T36,T106
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T7,T36,T49
DetectSt	-	-	-	-	0	1	-	Covered	T18,T10,T52
DetectSt	-	-	-	-	0	0	-	Covered	T18,T7,T10
StableSt	-	-	-	-	-	-	1	Covered	T18,T10,T52
StableSt	-	-	-	-	-	-	0	Covered	T18,T10,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	783	0	0
CntIncr_A	8421531	47468	0	0
CntNoWrap_A	8421531	7777047	0	0
DetectStDropOut_A	8421531	39	0	0
DetectedOut_A	8421531	13609	0	0
DetectedPulseOut_A	8421531	323	0	0
DisabledIdleSt_A	8421531	7424551	0	0
DisabledNoDetection_A	8421531	7426180	0	0
EnterDebounceSt_A	8421531	417	0	0
EnterDetectSt_A	8421531	367	0	0
EnterStableSt_A	8421531	323	0	0
PulseIsPulse_A	8421531	323	0	0
StayInStableSt	8421531	13256	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	291	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	783	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	2	0	0
T10	0	4	0	0
T18	21599	4	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	18	0	0
T35	0	1	0	0
T36	0	3	0	0
T38	0	2	0	0
T48	0	2	0	0
T52	0	20	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	47468	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	131	0	0
T10	0	238	0	0
T18	21599	526	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	1080	0	0
T35	0	99	0	0
T36	0	256	0	0
T38	0	83	0	0
T48	0	68	0	0
T52	0	1810	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	2044	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7777047	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21194	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	39	0	0
T7	6439	1	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	0	0	0
T11	682	0	0	0
T26	9572	0	0	0
T36	0	1	0	0
T56	628	0	0	0
T57	404	0	0	0
T58	521	0	0	0
T59	522	0	0	0
T83	0	3	0	0
T101	0	1	0	0
T169	0	1	0	0
T257	0	3	0	0
T258	0	6	0	0
T259	0	1	0	0
T260	0	6	0	0
T261	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	13609	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	174	0	0
T18	21599	111	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	121	0	0
T33	0	22	0	0
T34	0	298	0	0
T38	0	26	0	0
T48	0	71	0	0
T49	0	76	0	0
T52	0	193	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	474	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	323	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	2	0	0
T18	21599	2	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	6	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	10	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7424551	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	17309	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7426180	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	17310	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	417	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	1	0	0
T10	0	2	0	0
T18	21599	2	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	9	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T48	0	1	0	0
T52	0	10	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	367	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	1	0	0
T10	0	2	0	0
T18	21599	2	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	9	0	0
T36	0	1	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T52	0	10	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	323	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	2	0	0
T18	21599	2	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	6	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	10	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	323	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	2	0	0
T18	21599	2	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	6	0	0
T38	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	10	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	13256	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	172	0	0
T18	21599	109	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	112	0	0
T33	0	20	0	0
T34	0	292	0	0
T38	0	25	0	0
T48	0	69	0	0
T49	0	75	0	0
T52	0	183	0	0
T56	628	0	0	0
T57	404	0	0	0
T106	0	464	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	291	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	0	0	0
T10	0	2	0	0
T18	21599	2	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	6	0	0
T38	0	1	0	0
T52	0	10	0	0
T56	628	0	0	0
T57	404	0	0	0
T81	0	2	0	0
T106	0	10	0	0
T262	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T26
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T26
1	0	Covered	T1,T18,T13
1	1	Covered	T1,T18,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T26
0	1	Covered	T13,T50,T49
1	0	Covered	T13,T49,T109

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T26
0	1	Covered	T1,T18,T26
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T18,T26
1	-	Covered	T1,T18,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T26
DetectSt	168	Covered	T1,T18,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T18,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T26
DebounceSt->IdleSt	163	Covered	T49,T244,T245
DetectSt->IdleSt	186	Covered	T13,T50,T49
DetectSt->StableSt	191	Covered	T1,T18,T26
IdleSt->DebounceSt	148	Covered	T1,T18,T26
StableSt->IdleSt	206	Covered	T1,T18,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T26
0	1	Covered	T1,T18,T26
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T18,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T244,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T26
DetectSt	-	-	-	-	1	-	-	Covered	T13,T50,T49
DetectSt	-	-	-	-	0	1	-	Covered	T1,T18,T26
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T26
StableSt	-	-	-	-	-	-	0	Covered	T1,T18,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	2990	0	0
CntIncr_A	8421531	108772	0	0
CntNoWrap_A	8421531	7774840	0	0
DetectStDropOut_A	8421531	492	0	0
DetectedOut_A	8421531	80699	0	0
DetectedPulseOut_A	8421531	804	0	0
DisabledIdleSt_A	8421531	7302468	0	0
DisabledNoDetection_A	8421531	7304562	0	0
EnterDebounceSt_A	8421531	1513	0	0
EnterDetectSt_A	8421531	1477	0	0
EnterStableSt_A	8421531	804	0	0
PulseIsPulse_A	8421531	804	0	0
StayInStableSt	8421531	79819	0	0
gen_high_event_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	727	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2990	0	0
T1	8442	50	0	0
T2	19005	0	0	0
T13	0	22	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	40	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	14	0	0
T37	0	4	0	0
T48	0	24	0	0
T49	0	16	0	0
T50	0	18	0	0
T51	0	14	0	0
T72	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	108772	0	0
T1	8442	1050	0	0
T2	19005	0	0	0
T13	0	638	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	4920	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	434	0	0
T37	0	106	0	0
T48	0	792	0	0
T49	0	322	0	0
T50	0	444	0	0
T51	0	259	0	0
T72	0	780	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7774840	0	0
T1	8442	7989	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21158	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	492	0	0
T13	6874	7	0	0
T46	621	0	0	0
T49	0	1	0	0
T50	0	9	0	0
T64	2628	0	0	0
T68	526	0	0	0
T69	522	0	0	0
T109	0	16	0	0
T120	405	0	0	0
T121	651	0	0	0
T122	426	0	0	0
T123	443	0	0	0
T246	0	30	0	0
T247	0	25	0	0
T249	0	5	0	0
T253	0	8	0	0
T263	0	20	0	0
T264	0	21	0	0
T265	819	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	80699	0	0
T1	8442	1501	0	0
T2	19005	0	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	4620	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	3378	0	0
T37	0	140	0	0
T48	0	637	0	0
T49	0	226	0	0
T51	0	699	0	0
T72	0	1252	0	0
T110	0	1744	0	0
T248	0	1073	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	804	0	0
T1	8442	25	0	0
T2	19005	0	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	20	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	7	0	0
T37	0	2	0	0
T48	0	12	0	0
T49	0	5	0	0
T51	0	7	0	0
T72	0	15	0	0
T110	0	24	0	0
T248	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7302468	0	0
T1	8442	4040	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	2056	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7304562	0	0
T1	8442	4040	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	2056	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1513	0	0
T1	8442	25	0	0
T2	19005	0	0	0
T13	0	11	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	20	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	7	0	0
T37	0	2	0	0
T48	0	12	0	0
T49	0	9	0	0
T50	0	9	0	0
T51	0	7	0	0
T72	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1477	0	0
T1	8442	25	0	0
T2	19005	0	0	0
T13	0	11	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	20	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	7	0	0
T37	0	2	0	0
T48	0	12	0	0
T49	0	7	0	0
T50	0	9	0	0
T51	0	7	0	0
T72	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	804	0	0
T1	8442	25	0	0
T2	19005	0	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	20	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	7	0	0
T37	0	2	0	0
T48	0	12	0	0
T49	0	5	0	0
T51	0	7	0	0
T72	0	15	0	0
T110	0	24	0	0
T248	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	804	0	0
T1	8442	25	0	0
T2	19005	0	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	20	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	7	0	0
T37	0	2	0	0
T48	0	12	0	0
T49	0	5	0	0
T51	0	7	0	0
T72	0	15	0	0
T110	0	24	0	0
T248	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	79819	0	0
T1	8442	1475	0	0
T2	19005	0	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	4600	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	3371	0	0
T37	0	137	0	0
T48	0	624	0	0
T49	0	221	0	0
T51	0	692	0	0
T72	0	1234	0	0
T110	0	1719	0	0
T248	0	1062	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	727	0	0
T1	8442	24	0	0
T2	19005	0	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	20	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	7	0	0
T37	0	1	0	0
T48	0	11	0	0
T49	0	5	0	0
T51	0	7	0	0
T72	0	12	0	0
T110	0	23	0	0
T248	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T18,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T18,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T7
0	1	Covered	T10,T32,T257
1	0	Covered	T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T7
0	1	Covered	T1,T18,T7
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T18,T7
1	-	Covered	T1,T18,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T7
DetectSt	168	Covered	T1,T18,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T18,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T7
DebounceSt->IdleSt	163	Covered	T7,T26,T106
DetectSt->IdleSt	186	Covered	T10,T32,T49
DetectSt->StableSt	191	Covered	T1,T18,T7
IdleSt->DebounceSt	148	Covered	T1,T18,T7
StableSt->IdleSt	206	Covered	T1,T18,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T18,T7
0	1	Covered	T1,T18,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T26,T106
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T7
DetectSt	-	-	-	-	1	-	-	Covered	T10,T32,T49
DetectSt	-	-	-	-	0	1	-	Covered	T1,T18,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T18,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	857	0	0
CntIncr_A	8421531	49838	0	0
CntNoWrap_A	8421531	7776973	0	0
DetectStDropOut_A	8421531	84	0	0
DetectedOut_A	8421531	13403	0	0
DetectedPulseOut_A	8421531	317	0	0
DisabledIdleSt_A	8421531	7410696	0	0
DisabledNoDetection_A	8421531	7412330	0	0
EnterDebounceSt_A	8421531	454	0	0
EnterDetectSt_A	8421531	405	0	0
EnterStableSt_A	8421531	317	0	0
PulseIsPulse_A	8421531	317	0	0
StayInStableSt	8421531	13069	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	293	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	857	0	0
T1	8442	2	0	0
T2	19005	0	0	0
T7	0	16	0	0
T10	0	4	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	10	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	1	0	0
T35	0	6	0	0
T36	0	4	0	0
T38	0	2	0	0
T51	0	8	0	0
T52	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	49838	0	0
T1	8442	50	0	0
T2	19005	0	0	0
T7	0	956	0	0
T10	0	411	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	1165	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	44	0	0
T35	0	336	0	0
T36	0	288	0	0
T38	0	98	0	0
T51	0	232	0	0
T52	0	561	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7776973	0	0
T1	8442	8037	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21188	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	84	0	0
T10	17392	2	0	0
T11	682	0	0	0
T12	835	0	0	0
T13	6874	0	0	0
T32	0	5	0	0
T46	621	0	0	0
T62	1681	0	0	0
T64	2628	0	0	0
T68	526	0	0	0
T82	0	4	0	0
T86	0	6	0	0
T88	0	2	0	0
T89	0	2	0	0
T120	405	0	0	0
T121	651	0	0	0
T257	0	6	0	0
T266	0	7	0	0
T267	0	4	0	0
T268	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	13403	0	0
T1	8442	62	0	0
T2	19005	0	0	0
T7	0	56	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	432	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T35	0	280	0	0
T36	0	57	0	0
T37	0	74	0	0
T38	0	11	0	0
T51	0	142	0	0
T52	0	36	0	0
T106	0	281	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	317	0	0
T1	8442	1	0	0
T2	19005	0	0	0
T7	0	7	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T51	0	4	0	0
T52	0	3	0	0
T106	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7410696	0	0
T1	8442	6539	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	16578	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7412330	0	0
T1	8442	6540	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	16579	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	454	0	0
T1	8442	1	0	0
T2	19005	0	0	0
T7	0	9	0	0
T10	0	2	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	1	0	0
T35	0	3	0	0
T36	0	2	0	0
T38	0	1	0	0
T51	0	4	0	0
T52	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	405	0	0
T1	8442	1	0	0
T2	19005	0	0	0
T7	0	7	0	0
T10	0	2	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T51	0	4	0	0
T52	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	317	0	0
T1	8442	1	0	0
T2	19005	0	0	0
T7	0	7	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T51	0	4	0	0
T52	0	3	0	0
T106	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	317	0	0
T1	8442	1	0	0
T2	19005	0	0	0
T7	0	7	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T51	0	4	0	0
T52	0	3	0	0
T106	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	13069	0	0
T1	8442	61	0	0
T2	19005	0	0	0
T7	0	49	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	427	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T35	0	277	0	0
T36	0	55	0	0
T37	0	73	0	0
T38	0	10	0	0
T51	0	138	0	0
T52	0	33	0	0
T106	0	274	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	293	0	0
T1	8442	1	0	0
T2	19005	0	0	0
T7	0	7	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T52	0	3	0	0
T72	0	1	0	0
T106	0	7	0	0