Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T26
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T26
1	0	Covered	T1,T18,T26
1	1	Covered	T1,T18,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T26
0	1	Covered	T26,T50,T51
1	0	Covered	T26,T51,T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T13
0	1	Covered	T1,T18,T13
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T18,T13
1	-	Covered	T1,T18,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T26
DetectSt	168	Covered	T1,T18,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T18,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T26
DebounceSt->IdleSt	163	Covered	T49,T244,T245
DetectSt->IdleSt	186	Covered	T26,T50,T51
DetectSt->StableSt	191	Covered	T1,T18,T13
IdleSt->DebounceSt	148	Covered	T1,T18,T26
StableSt->IdleSt	206	Covered	T1,T18,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T26
0	1	Covered	T1,T18,T26
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T18,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T244,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T50,T51
DetectSt	-	-	-	-	0	1	-	Covered	T1,T18,T13
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T13
StableSt	-	-	-	-	-	-	0	Covered	T1,T18,T13
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	2767	0	0
CntIncr_A	8421531	101576	0	0
CntNoWrap_A	8421531	7775063	0	0
DetectStDropOut_A	8421531	473	0	0
DetectedOut_A	8421531	74343	0	0
DetectedPulseOut_A	8421531	775	0	0
DisabledIdleSt_A	8421531	7308749	0	0
DisabledNoDetection_A	8421531	7310830	0	0
EnterDebounceSt_A	8421531	1405	0	0
EnterDetectSt_A	8421531	1362	0	0
EnterStableSt_A	8421531	775	0	0
PulseIsPulse_A	8421531	775	0	0
StayInStableSt	8421531	73479	0	0
gen_high_event_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	686	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	2767	0	0
T1	8442	16	0	0
T2	19005	0	0	0
T13	0	56	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	38	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	54	0	0
T37	0	52	0	0
T48	0	2	0	0
T49	0	16	0	0
T50	0	20	0	0
T51	0	6	0	0
T72	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	101576	0	0
T1	8442	216	0	0
T2	19005	0	0	0
T13	0	1372	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	4826	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	1974	0	0
T37	0	988	0	0
T48	0	62	0	0
T49	0	321	0	0
T50	0	494	0	0
T51	0	111	0	0
T72	0	1288	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7775063	0	0
T1	8442	8023	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21160	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	473	0	0
T8	731	0	0	0
T9	952	0	0	0
T10	17392	0	0	0
T11	682	0	0	0
T12	835	0	0	0
T13	6874	0	0	0
T26	9572	24	0	0
T49	0	1	0	0
T50	0	10	0	0
T51	0	1	0	0
T58	521	0	0	0
T59	522	0	0	0
T62	1681	0	0	0
T110	0	14	0	0
T247	0	5	0	0
T249	0	26	0	0
T263	0	18	0	0
T264	0	23	0	0
T269	0	22	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	74343	0	0
T1	8442	198	0	0
T2	19005	0	0	0
T13	0	1596	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	4402	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T37	0	3173	0	0
T48	0	45	0	0
T49	0	270	0	0
T72	0	2071	0	0
T109	0	370	0	0
T248	0	1717	0	0
T270	0	2116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	775	0	0
T1	8442	8	0	0
T2	19005	0	0	0
T13	0	28	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	19	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T37	0	26	0	0
T48	0	1	0	0
T49	0	5	0	0
T72	0	23	0	0
T109	0	10	0	0
T248	0	13	0	0
T270	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7308749	0	0
T1	8442	5355	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	2057	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7310830	0	0
T1	8442	5356	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	2057	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1405	0	0
T1	8442	8	0	0
T2	19005	0	0	0
T13	0	28	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	19	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	27	0	0
T37	0	26	0	0
T48	0	1	0	0
T49	0	9	0	0
T50	0	10	0	0
T51	0	3	0	0
T72	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	1362	0	0
T1	8442	8	0	0
T2	19005	0	0	0
T13	0	28	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	19	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T26	0	27	0	0
T37	0	26	0	0
T48	0	1	0	0
T49	0	7	0	0
T50	0	10	0	0
T51	0	3	0	0
T72	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	775	0	0
T1	8442	8	0	0
T2	19005	0	0	0
T13	0	28	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	19	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T37	0	26	0	0
T48	0	1	0	0
T49	0	5	0	0
T72	0	23	0	0
T109	0	10	0	0
T248	0	13	0	0
T270	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	775	0	0
T1	8442	8	0	0
T2	19005	0	0	0
T13	0	28	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	19	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T37	0	26	0	0
T48	0	1	0	0
T49	0	5	0	0
T72	0	23	0	0
T109	0	10	0	0
T248	0	13	0	0
T270	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	73479	0	0
T1	8442	190	0	0
T2	19005	0	0	0
T13	0	1568	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	4383	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T37	0	3136	0	0
T48	0	44	0	0
T49	0	265	0	0
T72	0	2044	0	0
T109	0	360	0	0
T248	0	1701	0	0
T270	0	2083	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	686	0	0
T1	8442	8	0	0
T2	19005	0	0	0
T13	0	28	0	0
T14	421	0	0	0
T15	503	0	0	0
T16	963	0	0	0
T17	2839	0	0	0
T18	21599	19	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T37	0	15	0	0
T48	0	1	0	0
T49	0	5	0	0
T72	0	19	0	0
T109	0	10	0	0
T248	0	10	0	0
T270	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T18,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T7,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T17,T18
1	1	Covered	T18,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T7,T13
0	1	Covered	T101,T34,T262
1	0	Covered	T49,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T7,T13
0	1	Covered	T18,T7,T13
1	0	Covered	T49,T60,T271

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T7,T13
1	-	Covered	T18,T7,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T7,T10
DetectSt	168	Covered	T18,T7,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T18,T7,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T7,T13
DebounceSt->IdleSt	163	Covered	T7,T10,T35
DetectSt->IdleSt	186	Covered	T49,T101,T34
DetectSt->StableSt	191	Covered	T18,T7,T13
IdleSt->DebounceSt	148	Covered	T18,T7,T10
StableSt->IdleSt	206	Covered	T18,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T7,T10
0	1	Covered	T18,T7,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T7,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T7,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T10,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T49,T101,T34
DetectSt	-	-	-	-	0	1	-	Covered	T18,T7,T13
DetectSt	-	-	-	-	0	0	-	Covered	T18,T7,T13
StableSt	-	-	-	-	-	-	1	Covered	T18,T7,T13
StableSt	-	-	-	-	-	-	0	Covered	T18,T7,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8421531	831	0	0
CntIncr_A	8421531	47199	0	0
CntNoWrap_A	8421531	7776999	0	0
DetectStDropOut_A	8421531	68	0	0
DetectedOut_A	8421531	12789	0	0
DetectedPulseOut_A	8421531	313	0	0
DisabledIdleSt_A	8421531	7420085	0	0
DisabledNoDetection_A	8421531	7421707	0	0
EnterDebounceSt_A	8421531	446	0	0
EnterDetectSt_A	8421531	387	0	0
EnterStableSt_A	8421531	313	0	0
PulseIsPulse_A	8421531	313	0	0
StayInStableSt	8421531	12455	0	0
gen_high_level_sva.HighLevelEvent_A	8421531	7780089	0	0
gen_not_sticky_sva.StableStDropOut_A	8421531	288	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	831	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	7	0	0
T10	0	1	0	0
T13	0	8	0	0
T18	21599	10	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	24	0	0
T35	0	1	0	0
T37	0	20	0	0
T52	0	4	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	8	0	0
T106	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	47199	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	254	0	0
T10	0	66	0	0
T13	0	196	0	0
T18	21599	1305	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	1519	0	0
T35	0	99	0	0
T37	0	690	0	0
T52	0	276	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	348	0	0
T106	0	990	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7776999	0	0
T1	8442	8039	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	21188	0	0
T19	528	127	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	68	0	0
T33	12540	0	0	0
T34	0	6	0	0
T81	0	9	0	0
T101	23131	4	0	0
T102	576	0	0	0
T103	796	0	0	0
T104	504	0	0	0
T105	2341	0	0	0
T183	0	1	0	0
T257	0	3	0	0
T258	0	5	0	0
T260	0	4	0	0
T262	0	5	0	0
T272	0	6	0	0
T273	0	2	0	0
T274	765	0	0	0
T275	259123	0	0	0
T276	503	0	0	0
T277	993	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	12789	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	184	0	0
T13	0	284	0	0
T18	21599	292	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	143	0	0
T33	0	118	0	0
T37	0	510	0	0
T49	0	75	0	0
T52	0	122	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	191	0	0
T106	0	32	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	313	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	3	0	0
T13	0	4	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	11	0	0
T33	0	2	0	0
T37	0	10	0	0
T49	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	4	0	0
T106	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7420085	0	0
T1	8442	7841	0	0
T4	493	92	0	0
T5	529	128	0	0
T6	421	20	0	0
T14	421	20	0	0
T15	503	102	0	0
T16	963	562	0	0
T17	2839	434	0	0
T18	21599	16796	0	0
T19	528	127	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7421707	0	0
T1	8442	7843	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	16797	0	0
T19	528	128	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	446	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	4	0	0
T10	0	1	0	0
T13	0	4	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	13	0	0
T35	0	1	0	0
T37	0	10	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	4	0	0
T106	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	387	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	3	0	0
T13	0	4	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	11	0	0
T37	0	10	0	0
T49	0	3	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	4	0	0
T101	0	4	0	0
T106	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	313	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	3	0	0
T13	0	4	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	11	0	0
T33	0	2	0	0
T37	0	10	0	0
T49	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	4	0	0
T106	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	313	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	3	0	0
T13	0	4	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	11	0	0
T33	0	2	0	0
T37	0	10	0	0
T49	0	1	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	4	0	0
T106	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	12455	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	181	0	0
T13	0	280	0	0
T18	21599	287	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	132	0	0
T33	0	116	0	0
T37	0	500	0	0
T49	0	74	0	0
T52	0	120	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	187	0	0
T106	0	29	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	7780089	0	0
T1	8442	8041	0	0
T4	493	93	0	0
T5	529	129	0	0
T6	421	21	0	0
T14	421	21	0	0
T15	503	103	0	0
T16	963	563	0	0
T17	2839	439	0	0
T18	21599	21199	0	0
T19	528	128	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8421531	288	0	0
T2	19005	0	0	0
T3	831	0	0	0
T7	6439	3	0	0
T13	0	4	0	0
T18	21599	5	0	0
T19	528	0	0	0
T20	495	0	0	0
T21	766	0	0	0
T25	1734	0	0	0
T32	0	11	0	0
T33	0	2	0	0
T37	0	10	0	0
T52	0	2	0	0
T56	628	0	0	0
T57	404	0	0	0
T72	0	4	0	0
T106	0	3	0	0
T266	0	1	0	0