Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1132050342	12840	0	0
auto_block_debounce_ctl_rd_A	1132050342	1567	0	0
auto_block_out_ctl_rd_A	1132050342	2195	0	0
com_det_ctl_0_rd_A	1132050342	3397	0	0
com_det_ctl_1_rd_A	1132050342	3436	0	0
com_det_ctl_2_rd_A	1132050342	3294	0	0
com_det_ctl_3_rd_A	1132050342	3403	0	0
com_out_ctl_0_rd_A	1132050342	3813	0	0
com_out_ctl_1_rd_A	1132050342	3648	0	0
com_out_ctl_2_rd_A	1132050342	4061	0	0
com_out_ctl_3_rd_A	1132050342	3928	0	0
com_pre_det_ctl_0_rd_A	1132050342	999	0	0
com_pre_det_ctl_1_rd_A	1132050342	1118	0	0
com_pre_det_ctl_2_rd_A	1132050342	1061	0	0
com_pre_det_ctl_3_rd_A	1132050342	1001	0	0
com_pre_sel_ctl_0_rd_A	1132050342	3956	0	0
com_pre_sel_ctl_1_rd_A	1132050342	3949	0	0
com_pre_sel_ctl_2_rd_A	1132050342	4030	0	0
com_pre_sel_ctl_3_rd_A	1132050342	4053	0	0
com_sel_ctl_0_rd_A	1132050342	4064	0	0
com_sel_ctl_1_rd_A	1132050342	4346	0	0
com_sel_ctl_2_rd_A	1132050342	4175	0	0
com_sel_ctl_3_rd_A	1132050342	4116	0	0
ec_rst_ctl_rd_A	1132050342	1948	0	0
intr_enable_rd_A	1132050342	1499	0	0
key_intr_ctl_rd_A	1132050342	3937	0	0
key_intr_debounce_ctl_rd_A	1132050342	1018	0	0
key_invert_ctl_rd_A	1132050342	4974	0	0
pin_allowed_ctl_rd_A	1132050342	4838	0	0
pin_out_ctl_rd_A	1132050342	3266	0	0
pin_out_value_rd_A	1132050342	3150	0	0
regwen_rd_A	1132050342	1371	0	0
ulp_ac_debounce_ctl_rd_A	1132050342	1240	0	0
ulp_ctl_rd_A	1132050342	1232	0	0
ulp_lid_debounce_ctl_rd_A	1132050342	1172	0	0
ulp_pwrb_debounce_ctl_rd_A	1132050342	1142	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	12840	0	0
T2	914966	11	0	0
T3	391015	0	0	0
T7	933717	0	0	0
T8	284314	0	0	0
T10	0	14	0	0
T25	211279	0	0	0
T26	191431	0	0	0
T33	0	5	0	0
T36	0	1	0	0
T38	0	5	0	0
T40	0	6	0	0
T44	0	9	0	0
T56	75487	0	0	0
T57	97077	0	0	0
T58	253350	0	0	0
T59	253502	0	0	0
T73	0	7	0	0
T79	0	9	0	0
T298	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1567	0	0
T33	0	8	0	0
T35	292217	24	0	0
T36	144661	0	0	0
T38	0	44	0	0
T45	161932	0	0	0
T66	118098	0	0	0
T67	118296	0	0	0
T80	109450	0	0	0
T94	247808	0	0	0
T95	254881	0	0	0
T96	97431	0	0	0
T97	128185	0	0	0
T107	0	10	0	0
T108	0	11	0	0
T298	0	34	0	0
T299	0	10	0	0
T300	0	13	0	0
T301	0	31	0	0
T302	0	11	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	2195	0	0
T33	0	8	0	0
T35	292217	13	0	0
T36	144661	0	0	0
T38	0	32	0	0
T45	161932	0	0	0
T66	118098	0	0	0
T67	118296	0	0	0
T80	109450	0	0	0
T94	247808	0	0	0
T95	254881	0	0	0
T96	97431	0	0	0
T97	128185	0	0	0
T107	0	7	0	0
T108	0	7	0	0
T298	0	10	0	0
T299	0	15	0	0
T300	0	4	0	0
T301	0	41	0	0
T302	0	14	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3397	0	0
T1	422128	55	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	37	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	16	0	0
T35	0	80	0	0
T37	0	102	0	0
T38	0	42	0	0
T72	0	31	0	0
T81	0	63	0	0
T106	0	64	0	0
T262	0	70	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3436	0	0
T1	422128	25	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	33	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	11	0	0
T35	0	64	0	0
T37	0	72	0	0
T38	0	35	0	0
T72	0	17	0	0
T81	0	75	0	0
T106	0	75	0	0
T262	0	63	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3294	0	0
T1	422128	44	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	15	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	16	0	0
T35	0	83	0	0
T37	0	79	0	0
T38	0	44	0	0
T72	0	34	0	0
T81	0	72	0	0
T106	0	60	0	0
T262	0	91	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3403	0	0
T1	422128	53	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	37	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	16	0	0
T35	0	62	0	0
T37	0	96	0	0
T38	0	27	0	0
T72	0	34	0	0
T81	0	72	0	0
T106	0	91	0	0
T262	0	67	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3813	0	0
T1	422128	37	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	13	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	11	0	0
T35	0	58	0	0
T37	0	76	0	0
T38	0	39	0	0
T72	0	57	0	0
T81	0	78	0	0
T106	0	47	0	0
T262	0	56	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3648	0	0
T1	422128	51	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	19	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	8	0	0
T35	0	75	0	0
T37	0	58	0	0
T38	0	44	0	0
T72	0	25	0	0
T81	0	88	0	0
T106	0	70	0	0
T262	0	72	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4061	0	0
T1	422128	36	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	23	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	17	0	0
T35	0	84	0	0
T37	0	85	0	0
T38	0	37	0	0
T72	0	17	0	0
T81	0	78	0	0
T106	0	68	0	0
T262	0	46	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3928	0	0
T1	422128	49	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	18	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	12	0	0
T35	0	78	0	0
T37	0	113	0	0
T38	0	35	0	0
T72	0	46	0	0
T81	0	62	0	0
T106	0	59	0	0
T262	0	62	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	999	0	0
T33	0	5	0	0
T38	481170	37	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	11	0	0
T166	0	6	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T278	0	3	0	0
T285	0	5	0	0
T291	98955	0	0	0
T298	0	52	0	0
T301	0	24	0	0
T302	0	11	0	0
T303	0	23	0	0
T304	240207	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1118	0	0
T33	0	10	0	0
T38	481170	39	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	33	0	0
T166	0	8	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T278	0	3	0	0
T285	0	10	0	0
T291	98955	0	0	0
T298	0	22	0	0
T301	0	20	0	0
T302	0	9	0	0
T303	0	9	0	0
T304	240207	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1061	0	0
T38	481170	45	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	39	0	0
T166	0	2	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T278	0	15	0	0
T285	0	12	0	0
T291	98955	0	0	0
T298	0	28	0	0
T301	0	32	0	0
T302	0	4	0	0
T303	0	17	0	0
T304	240207	0	0	0
T305	0	6	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1001	0	0
T33	0	3	0	0
T38	481170	40	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	32	0	0
T166	0	22	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T285	0	6	0	0
T288	0	17	0	0
T291	98955	0	0	0
T298	0	23	0	0
T301	0	36	0	0
T302	0	10	0	0
T303	0	10	0	0
T304	240207	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3956	0	0
T1	422128	54	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	13	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	15	0	0
T35	0	50	0	0
T37	0	63	0	0
T38	0	31	0	0
T72	0	52	0	0
T81	0	60	0	0
T106	0	86	0	0
T262	0	68	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3949	0	0
T1	422128	40	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	23	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	17	0	0
T35	0	76	0	0
T37	0	78	0	0
T38	0	48	0	0
T72	0	38	0	0
T81	0	84	0	0
T106	0	69	0	0
T262	0	60	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4030	0	0
T1	422128	37	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	16	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	11	0	0
T35	0	61	0	0
T37	0	93	0	0
T38	0	28	0	0
T72	0	43	0	0
T81	0	68	0	0
T106	0	62	0	0
T262	0	72	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4053	0	0
T1	422128	52	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	22	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	8	0	0
T35	0	97	0	0
T37	0	95	0	0
T38	0	25	0	0
T72	0	26	0	0
T81	0	77	0	0
T106	0	82	0	0
T262	0	54	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4064	0	0
T1	422128	36	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	19	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	11	0	0
T35	0	80	0	0
T37	0	86	0	0
T38	0	29	0	0
T72	0	29	0	0
T81	0	61	0	0
T106	0	58	0	0
T262	0	77	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4346	0	0
T1	422128	42	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	28	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	17	0	0
T35	0	79	0	0
T37	0	94	0	0
T38	0	39	0	0
T72	0	31	0	0
T81	0	73	0	0
T106	0	82	0	0
T262	0	55	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4175	0	0
T1	422128	38	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	30	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	18	0	0
T35	0	70	0	0
T37	0	76	0	0
T38	0	37	0	0
T72	0	22	0	0
T81	0	71	0	0
T106	0	72	0	0
T262	0	78	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4116	0	0
T1	422128	48	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	9	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T33	0	7	0	0
T35	0	65	0	0
T37	0	85	0	0
T38	0	62	0	0
T72	0	35	0	0
T81	0	61	0	0
T106	0	51	0	0
T262	0	57	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1948	0	0
T1	422128	2	0	0
T2	914966	0	0	0
T14	204529	0	0	0
T15	115804	0	0	0
T16	240883	0	0	0
T17	132444	0	0	0
T18	259195	7	0	0
T19	36970	0	0	0
T20	71833	0	0	0
T21	95742	0	0	0
T35	0	5	0	0
T37	0	30	0	0
T38	0	61	0	0
T62	0	2	0	0
T106	0	61	0	0
T113	0	3	0	0
T121	0	2	0	0
T304	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1499	0	0
T33	0	5	0	0
T38	481170	40	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T141	0	14	0	0
T153	0	42	0	0
T166	0	28	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T291	98955	0	0	0
T298	0	25	0	0
T301	0	50	0	0
T302	0	11	0	0
T304	240207	0	0	0
T306	0	22	0	0
T307	0	10	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3937	0	0
T31	116884	0	0	0
T33	0	5	0	0
T38	0	54	0	0
T40	871366	0	0	0
T51	261513	0	0	0
T52	828028	0	0	0
T65	123427	0	0	0
T70	340268	2	0	0
T153	0	22	0	0
T166	0	9	0	0
T206	0	6	0	0
T232	0	8	0	0
T233	111399	0	0	0
T279	640321	0	0	0
T298	0	14	0	0
T301	0	34	0	0
T302	0	20	0	0
T308	59474	0	0	0
T309	207249	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1018	0	0
T33	0	9	0	0
T38	481170	33	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	36	0	0
T166	0	14	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T278	0	24	0	0
T285	0	11	0	0
T291	98955	0	0	0
T298	0	19	0	0
T301	0	13	0	0
T302	0	10	0	0
T303	0	6	0	0
T304	240207	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4974	0	0
T2	914966	0	0	0
T3	391015	0	0	0
T7	933717	0	0	0
T20	71833	38	0	0
T21	95742	0	0	0
T25	211279	0	0	0
T26	191431	0	0	0
T33	0	147	0	0
T38	0	104	0	0
T56	75487	0	0	0
T57	97077	0	0	0
T58	253350	0	0	0
T215	0	81	0	0
T298	0	15	0	0
T306	0	61	0	0
T310	0	75	0	0
T311	0	66	0	0
T312	0	22	0	0
T313	0	39	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	4838	0	0
T33	0	8	0	0
T38	481170	66	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	16	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T240	0	37	0	0
T291	98955	0	0	0
T298	0	16	0	0
T301	0	87	0	0
T302	0	78	0	0
T304	240207	0	0	0
T307	0	52	0	0
T312	0	51	0	0
T314	0	50	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3266	0	0
T33	0	1	0	0
T38	481170	61	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	33	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T240	0	45	0	0
T291	98955	0	0	0
T298	0	26	0	0
T301	0	95	0	0
T302	0	79	0	0
T304	240207	0	0	0
T307	0	62	0	0
T312	0	57	0	0
T314	0	65	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	3150	0	0
T33	0	5	0	0
T38	481170	81	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	28	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T240	0	76	0	0
T291	98955	0	0	0
T298	0	16	0	0
T301	0	95	0	0
T302	0	94	0	0
T304	240207	0	0	0
T307	0	76	0	0
T312	0	51	0	0
T314	0	71	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1371	0	0
T33	0	12	0	0
T38	481170	28	0	0
T39	77448	0	0	0
T53	336805	0	0	0
T54	349868	0	0	0
T63	47065	0	0	0
T153	0	30	0	0
T166	0	18	0	0
T212	53282	0	0	0
T213	51093	0	0	0
T214	67739	0	0	0
T278	0	6	0	0
T285	0	2	0	0
T291	98955	0	0	0
T298	0	18	0	0
T301	0	30	0	0
T302	0	19	0	0
T303	0	14	0	0
T304	240207	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1240	0	0
T7	933717	0	0	0
T8	284314	0	0	0
T9	109518	0	0	0
T10	214059	0	0	0
T25	211279	6	0	0
T26	191431	0	0	0
T33	0	4	0	0
T35	0	5	0	0
T38	0	20	0	0
T56	75487	0	0	0
T57	97077	0	0	0
T58	253350	0	0	0
T59	253502	0	0	0
T61	0	2	0	0
T63	0	9	0	0
T298	0	27	0	0
T301	0	40	0	0
T302	0	19	0	0
T307	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1232	0	0
T7	933717	0	0	0
T8	284314	0	0	0
T9	109518	0	0	0
T10	214059	0	0	0
T25	211279	5	0	0
T26	191431	0	0	0
T33	0	18	0	0
T35	0	2	0	0
T38	0	33	0	0
T56	75487	0	0	0
T57	97077	0	0	0
T58	253350	0	0	0
T59	253502	0	0	0
T61	0	9	0	0
T63	0	9	0	0
T298	0	19	0	0
T301	0	24	0	0
T302	0	8	0	0
T307	0	3	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1172	0	0
T7	933717	0	0	0
T8	284314	0	0	0
T9	109518	0	0	0
T10	214059	0	0	0
T25	211279	13	0	0
T26	191431	0	0	0
T33	0	12	0	0
T35	0	4	0	0
T38	0	39	0	0
T56	75487	0	0	0
T57	97077	0	0	0
T58	253350	0	0	0
T59	253502	0	0	0
T61	0	5	0	0
T63	0	8	0	0
T298	0	12	0	0
T301	0	42	0	0
T302	0	12	0	0
T307	0	9	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132050342	1142	0	0
T7	933717	0	0	0
T8	284314	0	0	0
T9	109518	0	0	0
T10	214059	0	0	0
T25	211279	7	0	0
T26	191431	0	0	0
T33	0	21	0	0
T35	0	2	0	0
T38	0	29	0	0
T56	75487	0	0	0
T57	97077	0	0	0
T58	253350	0	0	0
T59	253502	0	0	0
T61	0	7	0	0
T63	0	7	0	0
T298	0	8	0	0
T301	0	34	0	0
T302	0	13	0	0
T307	0	4	0	0