Line Coverage for Instance : tb.dut.u_reg.u_intr_state
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 6 | 85.71 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
0 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state
| Total | Covered | Percent |
|---|
| Conditions | 2 | 1 | 50.00 |
| Logical | 2 | 1 | 50.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
3 |
60.00 |
| TERNARY |
64 |
2 |
1 |
50.00 |
| IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_regwen
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_regwen
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T27,T28,T29 |
Branch Coverage for Instance : tb.dut.u_reg.u_regwen
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T28,T29 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T27,T28,T29 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T16 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T1,T16 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T2,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T2,T25 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T2,T25 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T2,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T2,T25 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T2,T25 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T2,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T2,T25 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T2,T25 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T25,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T25,T10 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T2,T25,T10 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_status
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T10,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T10,T12 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T2,T10,T12 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_status
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T17,T20,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T20,T2 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T17,T20,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T1 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T1 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T1 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T1 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T1 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T1 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T1 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T1 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_bat_disable
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_bat_disable
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_bat_disable
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key0_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key0_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key0_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key1_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key1_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key1_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key2_out
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key2_out
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key2_out
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T15,T17 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T15,T17 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T5,T15,T17 |
| 0 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 6 | 85.71 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
0 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in
| Total | Covered | Percent |
|---|
| Conditions | 2 | 1 | 50.00 |
| Logical | 2 | 1 | 50.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
3 |
60.00 |
| TERNARY |
64 |
2 |
1 |
50.00 |
| IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 6 | 85.71 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
0 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in
| Total | Covered | Percent |
|---|
| Conditions | 2 | 1 | 50.00 |
| Logical | 2 | 1 | 50.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
3 |
60.00 |
| TERNARY |
64 |
2 |
1 |
50.00 |
| IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 6 | 85.71 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
0 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in
| Total | Covered | Percent |
|---|
| Conditions | 2 | 1 | 50.00 |
| Logical | 2 | 1 | 50.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
3 |
60.00 |
| TERNARY |
64 |
2 |
1 |
50.00 |
| IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 6 | 85.71 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
0 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in
| Total | Covered | Percent |
|---|
| Conditions | 2 | 1 | 50.00 |
| Logical | 2 | 1 | 50.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
3 |
60.00 |
| TERNARY |
64 |
2 |
1 |
50.00 |
| IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 6 | 85.71 |
| ALWAYS | 56 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 56 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
| 64 |
1 |
1 |
| 65 |
0 |
1 |
| 72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open
| Total | Covered | Percent |
|---|
| Conditions | 2 | 1 | 50.00 |
| Logical | 2 | 1 | 50.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
3 |
60.00 |
| TERNARY |
64 |
2 |
1 |
50.00 |
| IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Not Covered |
|
