Module Definition
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Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.16 92.00 86.05 82.61 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sysrst_ctrl_intr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T4,T5,T6
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 2147483647 3173 0 0
SyncReqAckHoldReq 17079389 2318 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 3173 0 0
T1 844256 3 0 0
T2 1829932 14 0 0
T3 0 8 0 0
T7 0 21 0 0
T8 0 7 0 0
T9 0 5 0 0
T10 0 9 0 0
T11 0 3 0 0
T12 0 8 0 0
T13 0 12 0 0
T14 409058 0 0 0
T15 231608 0 0 0
T16 481766 0 0 0
T17 264888 0 0 0
T18 518390 0 0 0
T19 73940 0 0 0
T20 143666 0 0 0
T21 191484 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 17079389 2318 0 0
T1 16884 2 0 0
T2 38010 14 0 0
T3 0 8 0 0
T7 0 21 0 0
T8 0 7 0 0
T9 0 5 0 0
T10 0 9 0 0
T11 0 3 0 0
T12 0 8 0 0
T13 0 12 0 0
T14 842 0 0 0
T15 1006 0 0 0
T16 1926 0 0 0
T17 5678 0 0 0
T18 43198 0 0 0
T19 1056 0 0 0
T20 990 0 0 0
T21 1532 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T7
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T4,T5,T6
ODD - 1 Covered T1,T2,T7
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1132050342 1917 0 0
SyncReqAckHoldReq 8657858 1062 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1132050342 1917 0 0
T1 422128 2 0 0
T2 914966 4 0 0
T3 0 1 0 0
T7 0 12 0 0
T8 0 1 0 0
T9 0 1 0 0
T10 0 5 0 0
T11 0 1 0 0
T12 0 4 0 0
T13 0 8 0 0
T14 204529 0 0 0
T15 115804 0 0 0
T16 240883 0 0 0
T17 132444 0 0 0
T18 259195 0 0 0
T19 36970 0 0 0
T20 71833 0 0 0
T21 95742 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 8657858 1062 0 0
T1 8442 1 0 0
T2 19005 4 0 0
T3 0 1 0 0
T7 0 12 0 0
T8 0 1 0 0
T9 0 1 0 0
T10 0 5 0 0
T11 0 1 0 0
T12 0 4 0 0
T13 0 8 0 0
T14 421 0 0 0
T15 503 0 0 0
T16 963 0 0 0
T17 2839 0 0 0
T18 21599 0 0 0
T19 528 0 0 0
T20 495 0 0 0
T21 766 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T2,T3,T7
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T4,T5,T6
ODD - 1 Covered T2,T3,T7
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1078009109 1256 0 0
SyncReqAckHoldReq 8421531 1256 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1078009109 1256 0 0
T1 422128 1 0 0
T2 914966 10 0 0
T3 0 7 0 0
T7 0 9 0 0
T8 0 6 0 0
T9 0 4 0 0
T10 0 4 0 0
T11 0 2 0 0
T12 0 4 0 0
T13 0 4 0 0
T14 204529 0 0 0
T15 115804 0 0 0
T16 240883 0 0 0
T17 132444 0 0 0
T18 259195 0 0 0
T19 36970 0 0 0
T20 71833 0 0 0
T21 95742 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 8421531 1256 0 0
T1 8442 1 0 0
T2 19005 10 0 0
T3 0 7 0 0
T7 0 9 0 0
T8 0 6 0 0
T9 0 4 0 0
T10 0 4 0 0
T11 0 2 0 0
T12 0 4 0 0
T13 0 4 0 0
T14 421 0 0 0
T15 503 0 0 0
T16 963 0 0 0
T17 2839 0 0 0
T18 21599 0 0 0
T19 528 0 0 0
T20 495 0 0 0
T21 766 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%