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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.35 96.71 100.00 96.79 98.82 99.52 93.38


Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T27 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2426380751 Jul 22 04:42:13 PM PDT 24 Jul 22 04:42:25 PM PDT 24 4030249220 ps
T28 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1470033105 Jul 22 04:42:39 PM PDT 24 Jul 22 04:42:55 PM PDT 24 22276639079 ps
T795 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2406719773 Jul 22 04:43:36 PM PDT 24 Jul 22 04:43:40 PM PDT 24 2023170478 ps
T22 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.4170238337 Jul 22 04:42:23 PM PDT 24 Jul 22 04:42:36 PM PDT 24 4934125570 ps
T29 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4274599467 Jul 22 04:43:03 PM PDT 24 Jul 22 04:43:06 PM PDT 24 2108741579 ps
T30 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2893110318 Jul 22 04:42:07 PM PDT 24 Jul 22 04:42:13 PM PDT 24 2051230883 ps
T284 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2095211697 Jul 22 04:42:42 PM PDT 24 Jul 22 04:42:44 PM PDT 24 2112175646 ps
T338 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2137262360 Jul 22 04:42:40 PM PDT 24 Jul 22 04:42:43 PM PDT 24 2054926356 ps
T339 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3559488453 Jul 22 04:42:49 PM PDT 24 Jul 22 04:42:53 PM PDT 24 2043099406 ps
T285 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3861023782 Jul 22 04:42:33 PM PDT 24 Jul 22 04:42:40 PM PDT 24 2054123373 ps
T294 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153285065 Jul 22 04:43:11 PM PDT 24 Jul 22 04:43:16 PM PDT 24 2076896382 ps
T796 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2619113378 Jul 22 04:43:12 PM PDT 24 Jul 22 04:43:18 PM PDT 24 2016922335 ps
T797 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.4224616505 Jul 22 04:43:12 PM PDT 24 Jul 22 04:43:18 PM PDT 24 2009778318 ps
T286 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1958171492 Jul 22 04:42:18 PM PDT 24 Jul 22 04:42:49 PM PDT 24 39582875032 ps
T282 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.842942499 Jul 22 04:42:50 PM PDT 24 Jul 22 04:43:45 PM PDT 24 22200048235 ps
T798 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4173739045 Jul 22 04:42:51 PM PDT 24 Jul 22 04:42:54 PM PDT 24 2038184461 ps
T23 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.731043262 Jul 22 04:42:36 PM PDT 24 Jul 22 04:42:56 PM PDT 24 7914501646 ps
T278 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.527556011 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:39 PM PDT 24 2283143433 ps
T283 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2656401860 Jul 22 04:42:31 PM PDT 24 Jul 22 04:43:32 PM PDT 24 22209484188 ps
T799 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.235026864 Jul 22 04:43:02 PM PDT 24 Jul 22 04:43:04 PM PDT 24 2092251841 ps
T326 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1901871408 Jul 22 04:42:08 PM PDT 24 Jul 22 04:43:02 PM PDT 24 38716213105 ps
T305 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1406341992 Jul 22 04:42:06 PM PDT 24 Jul 22 04:42:09 PM PDT 24 2096108289 ps
T800 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3131607430 Jul 22 04:43:13 PM PDT 24 Jul 22 04:43:15 PM PDT 24 2051027639 ps
T287 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1008056296 Jul 22 04:42:24 PM PDT 24 Jul 22 04:42:28 PM PDT 24 2624329040 ps
T801 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.661248498 Jul 22 04:42:18 PM PDT 24 Jul 22 04:42:20 PM PDT 24 2028518205 ps
T289 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2124516792 Jul 22 04:42:52 PM PDT 24 Jul 22 04:42:58 PM PDT 24 2092241313 ps
T802 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1951052070 Jul 22 04:42:49 PM PDT 24 Jul 22 04:42:54 PM PDT 24 2015841121 ps
T803 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.210875555 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:37 PM PDT 24 2043429165 ps
T288 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3701072080 Jul 22 04:42:30 PM PDT 24 Jul 22 04:42:38 PM PDT 24 2127450647 ps
T293 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1724838599 Jul 22 04:42:07 PM PDT 24 Jul 22 04:42:10 PM PDT 24 2236743813 ps
T290 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2094858258 Jul 22 04:42:31 PM PDT 24 Jul 22 04:42:39 PM PDT 24 2075203443 ps
T375 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4161475263 Jul 22 04:42:13 PM PDT 24 Jul 22 04:42:38 PM PDT 24 42519640383 ps
T381 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.318868057 Jul 22 04:42:49 PM PDT 24 Jul 22 04:42:51 PM PDT 24 2062056586 ps
T804 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4167577500 Jul 22 04:43:04 PM PDT 24 Jul 22 04:43:06 PM PDT 24 2034818645 ps
T24 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1217903356 Jul 22 04:43:02 PM PDT 24 Jul 22 04:43:09 PM PDT 24 8009846390 ps
T327 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1878447954 Jul 22 04:42:49 PM PDT 24 Jul 22 04:42:53 PM PDT 24 2040868191 ps
T805 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2512884180 Jul 22 04:43:17 PM PDT 24 Jul 22 04:43:26 PM PDT 24 3021295409 ps
T806 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2651293043 Jul 22 04:42:16 PM PDT 24 Jul 22 04:42:27 PM PDT 24 2670749781 ps
T378 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2155250785 Jul 22 04:42:41 PM PDT 24 Jul 22 04:43:13 PM PDT 24 22315514670 ps
T295 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2480646369 Jul 22 04:42:16 PM PDT 24 Jul 22 04:42:20 PM PDT 24 2474022788 ps
T328 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.481112 Jul 22 04:42:24 PM PDT 24 Jul 22 04:42:30 PM PDT 24 3317609291 ps
T807 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2089122279 Jul 22 04:43:13 PM PDT 24 Jul 22 04:43:15 PM PDT 24 2085835210 ps
T329 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2440668965 Jul 22 04:43:14 PM PDT 24 Jul 22 04:43:18 PM PDT 24 2051424814 ps
T340 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4257609671 Jul 22 04:42:07 PM PDT 24 Jul 22 04:42:11 PM PDT 24 4068611008 ps
T808 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1109578478 Jul 22 04:43:11 PM PDT 24 Jul 22 04:43:18 PM PDT 24 2014318146 ps
T809 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2892181727 Jul 22 04:43:02 PM PDT 24 Jul 22 04:43:07 PM PDT 24 2010129960 ps
T810 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1378537104 Jul 22 04:43:04 PM PDT 24 Jul 22 04:43:08 PM PDT 24 2015001816 ps
T811 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1818441776 Jul 22 04:43:46 PM PDT 24 Jul 22 04:43:52 PM PDT 24 2018286041 ps
T812 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.732396835 Jul 22 04:42:23 PM PDT 24 Jul 22 04:42:30 PM PDT 24 2318179113 ps
T813 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3544958887 Jul 22 04:42:23 PM PDT 24 Jul 22 04:42:28 PM PDT 24 2510897523 ps
T814 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2796336024 Jul 22 04:42:35 PM PDT 24 Jul 22 04:42:38 PM PDT 24 2075350725 ps
T815 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.310849528 Jul 22 04:43:25 PM PDT 24 Jul 22 04:43:28 PM PDT 24 2231624701 ps
T816 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2929950635 Jul 22 04:42:25 PM PDT 24 Jul 22 04:42:29 PM PDT 24 2019198920 ps
T330 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3116738834 Jul 22 04:42:49 PM PDT 24 Jul 22 04:42:55 PM PDT 24 2053124918 ps
T817 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3764883803 Jul 22 04:42:41 PM PDT 24 Jul 22 04:42:45 PM PDT 24 5299583355 ps
T818 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4169052070 Jul 22 04:42:34 PM PDT 24 Jul 22 04:42:37 PM PDT 24 2047926589 ps
T376 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3447296377 Jul 22 04:42:24 PM PDT 24 Jul 22 04:42:55 PM PDT 24 22314319512 ps
T819 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1079041860 Jul 22 04:42:36 PM PDT 24 Jul 22 04:42:43 PM PDT 24 2060023378 ps
T331 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2874846105 Jul 22 04:43:33 PM PDT 24 Jul 22 04:43:39 PM PDT 24 2038760494 ps
T820 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3346747499 Jul 22 04:43:10 PM PDT 24 Jul 22 04:43:13 PM PDT 24 2039866436 ps
T821 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3589612927 Jul 22 04:42:09 PM PDT 24 Jul 22 04:42:25 PM PDT 24 7491294564 ps
T822 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.178849035 Jul 22 04:42:24 PM PDT 24 Jul 22 04:42:28 PM PDT 24 2025337152 ps
T332 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1209085861 Jul 22 04:42:15 PM PDT 24 Jul 22 04:42:26 PM PDT 24 4014319192 ps
T823 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.909865305 Jul 22 04:42:05 PM PDT 24 Jul 22 04:43:04 PM PDT 24 22229684740 ps
T377 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2061240764 Jul 22 04:43:01 PM PDT 24 Jul 22 04:43:27 PM PDT 24 42614456462 ps
T824 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4110577352 Jul 22 04:42:31 PM PDT 24 Jul 22 04:42:34 PM PDT 24 2445129490 ps
T333 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2848036683 Jul 22 04:42:21 PM PDT 24 Jul 22 04:42:30 PM PDT 24 3111721709 ps
T334 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1113268224 Jul 22 04:42:25 PM PDT 24 Jul 22 04:42:31 PM PDT 24 2077758200 ps
T335 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3749450079 Jul 22 04:42:07 PM PDT 24 Jul 22 04:42:19 PM PDT 24 13520886331 ps
T825 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2205632245 Jul 22 04:43:05 PM PDT 24 Jul 22 04:43:10 PM PDT 24 2010986638 ps
T826 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2660410643 Jul 22 04:43:03 PM PDT 24 Jul 22 04:43:06 PM PDT 24 2039773993 ps
T827 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1187133954 Jul 22 04:42:53 PM PDT 24 Jul 22 04:43:17 PM PDT 24 5518951205 ps
T828 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.905325999 Jul 22 04:43:13 PM PDT 24 Jul 22 04:43:19 PM PDT 24 2012573028 ps
T829 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2244502050 Jul 22 04:42:31 PM PDT 24 Jul 22 04:42:38 PM PDT 24 9868491131 ps
T830 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4258202807 Jul 22 04:42:40 PM PDT 24 Jul 22 04:42:42 PM PDT 24 2112167083 ps
T831 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2471195580 Jul 22 04:42:25 PM PDT 24 Jul 22 04:42:29 PM PDT 24 2086061461 ps
T832 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2575628683 Jul 22 04:42:49 PM PDT 24 Jul 22 04:42:54 PM PDT 24 2089198379 ps
T833 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3096376315 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:36 PM PDT 24 2199585188 ps
T834 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1837767289 Jul 22 04:42:08 PM PDT 24 Jul 22 04:42:13 PM PDT 24 2205792567 ps
T835 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1605965923 Jul 22 04:42:08 PM PDT 24 Jul 22 04:42:15 PM PDT 24 10514991443 ps
T836 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1899466915 Jul 22 04:43:10 PM PDT 24 Jul 22 04:43:11 PM PDT 24 2107861184 ps
T837 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3963766882 Jul 22 04:43:11 PM PDT 24 Jul 22 04:43:13 PM PDT 24 2031695483 ps
T838 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.17928048 Jul 22 04:42:31 PM PDT 24 Jul 22 04:42:33 PM PDT 24 2031632729 ps
T839 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2739865782 Jul 22 04:42:42 PM PDT 24 Jul 22 04:42:45 PM PDT 24 2390929013 ps
T840 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.4155089686 Jul 22 04:42:23 PM PDT 24 Jul 22 04:42:34 PM PDT 24 4905081137 ps
T841 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3880278186 Jul 22 04:42:48 PM PDT 24 Jul 22 04:42:56 PM PDT 24 2076942111 ps
T842 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3953608499 Jul 22 04:43:02 PM PDT 24 Jul 22 04:43:08 PM PDT 24 2017767324 ps
T379 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3405347646 Jul 22 04:42:51 PM PDT 24 Jul 22 04:43:21 PM PDT 24 42500993359 ps
T380 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1755239120 Jul 22 04:42:34 PM PDT 24 Jul 22 04:44:13 PM PDT 24 42467114385 ps
T843 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2861752638 Jul 22 04:42:51 PM PDT 24 Jul 22 04:43:00 PM PDT 24 10183138662 ps
T844 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1810852496 Jul 22 04:42:06 PM PDT 24 Jul 22 04:42:12 PM PDT 24 2016656198 ps
T336 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3996348362 Jul 22 04:42:50 PM PDT 24 Jul 22 04:42:52 PM PDT 24 2088330847 ps
T845 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.951065578 Jul 22 04:42:31 PM PDT 24 Jul 22 04:42:46 PM PDT 24 22318063627 ps
T846 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1685486657 Jul 22 04:43:57 PM PDT 24 Jul 22 04:43:59 PM PDT 24 2144879589 ps
T847 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3112635031 Jul 22 04:42:41 PM PDT 24 Jul 22 04:42:55 PM PDT 24 9733218975 ps
T848 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.63595009 Jul 22 04:43:04 PM PDT 24 Jul 22 04:43:10 PM PDT 24 2016459517 ps
T849 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.576088982 Jul 22 04:42:34 PM PDT 24 Jul 22 04:42:51 PM PDT 24 22302325767 ps
T850 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4172783467 Jul 22 04:42:35 PM PDT 24 Jul 22 04:42:37 PM PDT 24 2080509595 ps
T851 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1066042099 Jul 22 04:42:41 PM PDT 24 Jul 22 04:42:54 PM PDT 24 22699733584 ps
T852 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.603420229 Jul 22 04:43:46 PM PDT 24 Jul 22 04:43:53 PM PDT 24 10044706448 ps
T853 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1395500153 Jul 22 04:42:42 PM PDT 24 Jul 22 04:42:46 PM PDT 24 2020001777 ps
T854 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.643904316 Jul 22 04:43:09 PM PDT 24 Jul 22 04:43:11 PM PDT 24 2081533474 ps
T855 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.230903379 Jul 22 04:43:09 PM PDT 24 Jul 22 04:43:12 PM PDT 24 2027679183 ps
T856 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.486750819 Jul 22 04:42:40 PM PDT 24 Jul 22 04:42:43 PM PDT 24 2094894498 ps
T857 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1865920071 Jul 22 04:42:41 PM PDT 24 Jul 22 04:42:51 PM PDT 24 10324380188 ps
T858 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153797278 Jul 22 04:42:23 PM PDT 24 Jul 22 04:42:31 PM PDT 24 2066763588 ps
T859 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3242244778 Jul 22 04:42:30 PM PDT 24 Jul 22 04:42:36 PM PDT 24 2062184683 ps
T860 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2885096565 Jul 22 04:42:42 PM PDT 24 Jul 22 04:42:45 PM PDT 24 2039631457 ps
T861 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2573211067 Jul 22 04:42:18 PM PDT 24 Jul 22 04:42:22 PM PDT 24 2084744924 ps
T337 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3825754130 Jul 22 04:42:50 PM PDT 24 Jul 22 04:42:56 PM PDT 24 2054590630 ps
T862 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3711759868 Jul 22 04:42:06 PM PDT 24 Jul 22 04:42:12 PM PDT 24 2012347618 ps
T863 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3147532142 Jul 22 04:43:04 PM PDT 24 Jul 22 04:43:10 PM PDT 24 2017739894 ps
T864 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1011758458 Jul 22 04:43:11 PM PDT 24 Jul 22 04:43:13 PM PDT 24 2069039471 ps
T865 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1229552233 Jul 22 04:42:16 PM PDT 24 Jul 22 04:42:40 PM PDT 24 22231512056 ps
T866 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4138338698 Jul 22 04:42:07 PM PDT 24 Jul 22 04:42:18 PM PDT 24 2670283644 ps
T867 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3366718197 Jul 22 04:42:18 PM PDT 24 Jul 22 04:42:33 PM PDT 24 22304364494 ps
T868 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2277765146 Jul 22 04:42:18 PM PDT 24 Jul 22 04:42:22 PM PDT 24 2389091679 ps
T869 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1499483704 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:38 PM PDT 24 4430211881 ps
T870 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3505470678 Jul 22 04:42:22 PM PDT 24 Jul 22 04:44:17 PM PDT 24 42480316709 ps
T871 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.460085399 Jul 22 04:43:15 PM PDT 24 Jul 22 04:43:18 PM PDT 24 2021126740 ps
T872 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.500292608 Jul 22 04:42:48 PM PDT 24 Jul 22 04:42:51 PM PDT 24 5554625122 ps
T873 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3993975486 Jul 22 04:42:25 PM PDT 24 Jul 22 04:42:37 PM PDT 24 42893380697 ps
T874 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3084121643 Jul 22 04:42:42 PM PDT 24 Jul 22 04:43:15 PM PDT 24 42491814491 ps
T875 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3405546602 Jul 22 04:42:48 PM PDT 24 Jul 22 04:42:55 PM PDT 24 2041176652 ps
T876 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.706839329 Jul 22 04:43:02 PM PDT 24 Jul 22 04:43:09 PM PDT 24 2023168645 ps
T877 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1685698393 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:39 PM PDT 24 2053240294 ps
T878 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2037720137 Jul 22 04:42:40 PM PDT 24 Jul 22 04:42:43 PM PDT 24 2068122909 ps
T879 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1418790751 Jul 22 04:42:09 PM PDT 24 Jul 22 04:42:14 PM PDT 24 2085833123 ps
T880 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.445103497 Jul 22 04:42:21 PM PDT 24 Jul 22 04:42:33 PM PDT 24 4913599760 ps
T881 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1126824707 Jul 22 04:42:25 PM PDT 24 Jul 22 04:42:28 PM PDT 24 2111043557 ps
T882 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3049961898 Jul 22 04:42:23 PM PDT 24 Jul 22 04:42:29 PM PDT 24 2044773286 ps
T883 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1619180418 Jul 22 04:42:51 PM PDT 24 Jul 22 04:42:53 PM PDT 24 2405883246 ps
T884 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1067868648 Jul 22 04:42:06 PM PDT 24 Jul 22 04:42:09 PM PDT 24 2154904414 ps
T885 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1760418237 Jul 22 04:42:48 PM PDT 24 Jul 22 04:42:51 PM PDT 24 3022130459 ps
T886 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.794673103 Jul 22 04:43:03 PM PDT 24 Jul 22 04:43:10 PM PDT 24 2017838819 ps
T887 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3330288525 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:39 PM PDT 24 2048584966 ps
T888 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1709665447 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:39 PM PDT 24 2010881134 ps
T889 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2774561304 Jul 22 04:42:16 PM PDT 24 Jul 22 04:42:28 PM PDT 24 4012208962 ps
T341 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2935742404 Jul 22 04:42:24 PM PDT 24 Jul 22 04:42:29 PM PDT 24 6104170524 ps
T890 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.186088935 Jul 22 04:42:36 PM PDT 24 Jul 22 04:42:38 PM PDT 24 2038870598 ps
T891 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1009105138 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:48 PM PDT 24 10684484354 ps
T892 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1568022058 Jul 22 04:42:31 PM PDT 24 Jul 22 04:42:34 PM PDT 24 2041987069 ps
T893 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2319251394 Jul 22 04:42:32 PM PDT 24 Jul 22 04:42:35 PM PDT 24 2057042819 ps
T894 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3311251129 Jul 22 04:42:39 PM PDT 24 Jul 22 04:42:42 PM PDT 24 2513896814 ps
T895 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2769079762 Jul 22 04:43:57 PM PDT 24 Jul 22 04:45:53 PM PDT 24 42432050966 ps
T896 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1312703889 Jul 22 04:42:24 PM PDT 24 Jul 22 04:42:28 PM PDT 24 2017060239 ps
T897 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1360552638 Jul 22 04:42:51 PM PDT 24 Jul 22 04:42:56 PM PDT 24 2013683523 ps
T898 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2161537094 Jul 22 04:42:17 PM PDT 24 Jul 22 04:42:24 PM PDT 24 2063085542 ps
T899 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.626662780 Jul 22 04:42:53 PM PDT 24 Jul 22 04:42:59 PM PDT 24 2013963223 ps
T900 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1364651590 Jul 22 04:43:57 PM PDT 24 Jul 22 04:44:04 PM PDT 24 2014158792 ps
T901 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.4036238667 Jul 22 04:43:34 PM PDT 24 Jul 22 04:43:39 PM PDT 24 8357339493 ps
T902 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3126470513 Jul 22 04:43:10 PM PDT 24 Jul 22 04:43:17 PM PDT 24 2015273157 ps
T903 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2694257552 Jul 22 04:42:41 PM PDT 24 Jul 22 04:42:43 PM PDT 24 2060751712 ps
T904 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1726641312 Jul 22 04:42:19 PM PDT 24 Jul 22 04:42:23 PM PDT 24 2324287657 ps
T905 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3978845175 Jul 22 04:43:02 PM PDT 24 Jul 22 04:43:04 PM PDT 24 2036865014 ps
T906 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1924284911 Jul 22 04:43:12 PM PDT 24 Jul 22 04:43:14 PM PDT 24 2037884188 ps
T907 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3228803574 Jul 22 04:43:11 PM PDT 24 Jul 22 04:43:28 PM PDT 24 9146016057 ps
T908 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2821194941 Jul 22 04:43:02 PM PDT 24 Jul 22 04:43:08 PM PDT 24 2035011786 ps
T909 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2218809531 Jul 22 04:42:33 PM PDT 24 Jul 22 04:42:36 PM PDT 24 2102460820 ps
T910 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.616045570 Jul 22 04:42:24 PM PDT 24 Jul 22 04:43:14 PM PDT 24 38830468093 ps
T911 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1642716297 Jul 22 04:43:03 PM PDT 24 Jul 22 04:43:05 PM PDT 24 2037221640 ps
T912 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1261177099 Jul 22 04:42:21 PM PDT 24 Jul 22 04:42:28 PM PDT 24 2011231785 ps
T913 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1707146487 Jul 22 04:42:34 PM PDT 24 Jul 22 04:42:47 PM PDT 24 4855945052 ps
T914 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3184182215 Jul 22 04:42:32 PM PDT 24 Jul 22 04:43:05 PM PDT 24 42486282702 ps

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2852635464
Short name T18
Test name
Test status
Simulation time 107998906573 ps
CPU time 66.43 seconds
Started Jul 22 04:53:15 PM PDT 24
Finished Jul 22 04:54:22 PM PDT 24
Peak memory 201224 kb
Host smart-acad7792-c3ec-496f-a446-a72cddb2ffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852635464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.2852635464
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2861384975
Short name T2
Test name
Test status
Simulation time 95026902024 ps
CPU time 26.58 seconds
Started Jul 22 04:50:10 PM PDT 24
Finished Jul 22 04:50:37 PM PDT 24
Peak memory 214472 kb
Host smart-3ad40462-3f62-4897-8aa0-92e699674ae0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861384975 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.2861384975
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3314692811
Short name T49
Test name
Test status
Simulation time 29161517290 ps
CPU time 42.44 seconds
Started Jul 22 04:47:59 PM PDT 24
Finished Jul 22 04:48:42 PM PDT 24
Peak memory 201008 kb
Host smart-739e5c61-023f-4b0f-928a-bf8086e76d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314692811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3314692811
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3636137535
Short name T44
Test name
Test status
Simulation time 31673619106 ps
CPU time 38.03 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:51:25 PM PDT 24
Peak memory 209604 kb
Host smart-f5f0d458-2fcd-4cb9-9c9e-7b88caa4ab2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636137535 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.3636137535
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.1940241538
Short name T35
Test name
Test status
Simulation time 62556861903 ps
CPU time 78.99 seconds
Started Jul 22 04:49:43 PM PDT 24
Finished Jul 22 04:51:03 PM PDT 24
Peak memory 201124 kb
Host smart-39fb38a2-c53c-406a-97ce-cfa5548de2ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940241538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.1940241538
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1464840510
Short name T166
Test name
Test status
Simulation time 95169655711 ps
CPU time 42.18 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:46 PM PDT 24
Peak memory 209648 kb
Host smart-e730adf9-9f7d-409b-93d7-bc0032ceed06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464840510 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1464840510
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.1501620045
Short name T39
Test name
Test status
Simulation time 3108471437 ps
CPU time 2.74 seconds
Started Jul 22 04:51:04 PM PDT 24
Finished Jul 22 04:51:07 PM PDT 24
Peak memory 200892 kb
Host smart-33b3203c-c879-4ee1-8fa4-6c97e2460d63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501620045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.1501620045
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.842942499
Short name T282
Test name
Test status
Simulation time 22200048235 ps
CPU time 54.28 seconds
Started Jul 22 04:42:50 PM PDT 24
Finished Jul 22 04:43:45 PM PDT 24
Peak memory 202028 kb
Host smart-74531c2d-0ddf-4363-b5c1-ee4d13483674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842942499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_tl_intg_err.842942499
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2299476261
Short name T32
Test name
Test status
Simulation time 182251610429 ps
CPU time 483.36 seconds
Started Jul 22 04:48:27 PM PDT 24
Finished Jul 22 04:56:31 PM PDT 24
Peak memory 201224 kb
Host smart-a8910445-57a8-41fa-bf02-978b9203800e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299476261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.2299476261
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2868618058
Short name T10
Test name
Test status
Simulation time 86962487960 ps
CPU time 55.29 seconds
Started Jul 22 04:48:23 PM PDT 24
Finished Jul 22 04:49:19 PM PDT 24
Peak memory 209668 kb
Host smart-d6832553-c283-4ba0-a56e-328721b4ce18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868618058 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2868618058
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.883325601
Short name T37
Test name
Test status
Simulation time 151500849784 ps
CPU time 377.82 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:57:04 PM PDT 24
Peak memory 201288 kb
Host smart-08f40a1a-e94a-44f7-acfa-610522e5cd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883325601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wi
th_pre_cond.883325601
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.165416695
Short name T323
Test name
Test status
Simulation time 69140767645 ps
CPU time 46.85 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:49:36 PM PDT 24
Peak memory 201200 kb
Host smart-f777525f-6d76-4c43-b3fb-ba5691700b64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165416695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.165416695
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.2175354037
Short name T279
Test name
Test status
Simulation time 22080288778 ps
CPU time 16.49 seconds
Started Jul 22 04:47:49 PM PDT 24
Finished Jul 22 04:48:06 PM PDT 24
Peak memory 220688 kb
Host smart-02fd330f-8fcd-4afb-9637-cc478419a9fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175354037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.2175354037
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2944740023
Short name T261
Test name
Test status
Simulation time 152958520666 ps
CPU time 174.52 seconds
Started Jul 22 04:49:51 PM PDT 24
Finished Jul 22 04:52:47 PM PDT 24
Peak memory 209588 kb
Host smart-c9b064e4-3273-4454-8e10-260a90c988e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944740023 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2944740023
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1901871408
Short name T326
Test name
Test status
Simulation time 38716213105 ps
CPU time 54.03 seconds
Started Jul 22 04:42:08 PM PDT 24
Finished Jul 22 04:43:02 PM PDT 24
Peak memory 202172 kb
Host smart-8c786346-2eb6-4650-a178-10eed7fa2e14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901871408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.1901871408
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1190362061
Short name T154
Test name
Test status
Simulation time 5129437517 ps
CPU time 2.26 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:49:42 PM PDT 24
Peak memory 200984 kb
Host smart-59d1947d-c594-4952-8537-a4e29aaea127
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190362061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.1190362061
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.837190619
Short name T267
Test name
Test status
Simulation time 64678839649 ps
CPU time 82.52 seconds
Started Jul 22 04:50:28 PM PDT 24
Finished Jul 22 04:51:52 PM PDT 24
Peak memory 201212 kb
Host smart-5b40e80c-8f9a-454f-8485-1181a8cce415
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837190619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_combo_detect.837190619
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.265477462
Short name T228
Test name
Test status
Simulation time 60944848718 ps
CPU time 163.16 seconds
Started Jul 22 04:52:10 PM PDT 24
Finished Jul 22 04:54:54 PM PDT 24
Peak memory 201204 kb
Host smart-c11b6c87-2cfe-40b1-9f1a-cf8d5e4b49b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265477462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_wi
th_pre_cond.265477462
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.41216448
Short name T189
Test name
Test status
Simulation time 5543835953 ps
CPU time 2.58 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:39 PM PDT 24
Peak memory 200948 kb
Host smart-18f880b3-7b28-4051-91dc-db6f21005953
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41216448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl
_edge_detect.41216448
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1008056296
Short name T287
Test name
Test status
Simulation time 2624329040 ps
CPU time 3.01 seconds
Started Jul 22 04:42:24 PM PDT 24
Finished Jul 22 04:42:28 PM PDT 24
Peak memory 202104 kb
Host smart-cc3620e4-d75d-420e-b507-5f277751a630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008056296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.1008056296
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2377080889
Short name T262
Test name
Test status
Simulation time 140713373850 ps
CPU time 28.17 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:51:14 PM PDT 24
Peak memory 201224 kb
Host smart-ef82f3be-b952-4d88-ad37-9176326da19c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377080889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.2377080889
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.4064325655
Short name T78
Test name
Test status
Simulation time 4546353263 ps
CPU time 2.43 seconds
Started Jul 22 04:50:28 PM PDT 24
Finished Jul 22 04:50:31 PM PDT 24
Peak memory 200912 kb
Host smart-29674998-4039-4271-9907-10ca108b608c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064325655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.4064325655
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.205493869
Short name T155
Test name
Test status
Simulation time 2716938858 ps
CPU time 7.63 seconds
Started Jul 22 04:51:45 PM PDT 24
Finished Jul 22 04:51:53 PM PDT 24
Peak memory 200960 kb
Host smart-776cc489-39ce-4afc-a040-c1b49bbd774e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205493869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctr
l_edge_detect.205493869
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2142985645
Short name T298
Test name
Test status
Simulation time 35540057028 ps
CPU time 88.37 seconds
Started Jul 22 04:48:50 PM PDT 24
Finished Jul 22 04:50:19 PM PDT 24
Peak memory 209532 kb
Host smart-933626e3-3462-4f55-8f61-fdc281e1bc43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142985645 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.2142985645
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1727433394
Short name T83
Test name
Test status
Simulation time 111129585522 ps
CPU time 130.89 seconds
Started Jul 22 04:53:07 PM PDT 24
Finished Jul 22 04:55:18 PM PDT 24
Peak memory 201140 kb
Host smart-beb4a953-dba0-44c4-b7c6-d781b16ee2af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727433394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.1727433394
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4107611655
Short name T182
Test name
Test status
Simulation time 105520383941 ps
CPU time 62.1 seconds
Started Jul 22 04:52:01 PM PDT 24
Finished Jul 22 04:53:03 PM PDT 24
Peak memory 201216 kb
Host smart-d93f9810-14b0-490f-b13d-8f9c540d2d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107611655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.4107611655
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1732538504
Short name T319
Test name
Test status
Simulation time 141326265058 ps
CPU time 94.57 seconds
Started Jul 22 04:55:00 PM PDT 24
Finished Jul 22 04:56:35 PM PDT 24
Peak memory 209576 kb
Host smart-44363cc4-7a03-40f5-96e4-7430ac9e106d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732538504 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1732538504
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2991994993
Short name T25
Test name
Test status
Simulation time 8671901000 ps
CPU time 6.31 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:50:26 PM PDT 24
Peak memory 201032 kb
Host smart-792aae4d-159b-4281-845e-b5e9629f51fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991994993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.2991994993
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1470033105
Short name T28
Test name
Test status
Simulation time 22276639079 ps
CPU time 15.9 seconds
Started Jul 22 04:42:39 PM PDT 24
Finished Jul 22 04:42:55 PM PDT 24
Peak memory 202136 kb
Host smart-0993b0d2-2fc1-4a8d-91c2-99848a09bfdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470033105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.1470033105
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3856580555
Short name T349
Test name
Test status
Simulation time 113667265990 ps
CPU time 75.42 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:53:25 PM PDT 24
Peak memory 201368 kb
Host smart-414e25e3-3b2b-474e-8d56-c0ad14e244e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856580555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.3856580555
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3978594623
Short name T60
Test name
Test status
Simulation time 34394858156 ps
CPU time 42.52 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:48:33 PM PDT 24
Peak memory 201008 kb
Host smart-a6705618-7b29-4d94-91e3-a6875ad0f856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978594623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.3978594623
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.232793220
Short name T143
Test name
Test status
Simulation time 42728019585 ps
CPU time 53.07 seconds
Started Jul 22 04:51:18 PM PDT 24
Finished Jul 22 04:52:11 PM PDT 24
Peak memory 217700 kb
Host smart-20abce57-f668-4ef1-a2a3-e67db422682f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232793220 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.232793220
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1611273173
Short name T291
Test name
Test status
Simulation time 2019501334 ps
CPU time 3.33 seconds
Started Jul 22 04:48:59 PM PDT 24
Finished Jul 22 04:49:02 PM PDT 24
Peak memory 201012 kb
Host smart-c6e99f21-5889-43eb-acbb-2e1e99cf5942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611273173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1611273173
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1217903356
Short name T24
Test name
Test status
Simulation time 8009846390 ps
CPU time 6.02 seconds
Started Jul 22 04:43:02 PM PDT 24
Finished Jul 22 04:43:09 PM PDT 24
Peak memory 202440 kb
Host smart-a0f89bbd-6478-41c4-9060-13d436d77d05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217903356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.1217903356
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3668330036
Short name T256
Test name
Test status
Simulation time 114625208281 ps
CPU time 71.62 seconds
Started Jul 22 04:50:18 PM PDT 24
Finished Jul 22 04:51:30 PM PDT 24
Peak memory 201256 kb
Host smart-0385c78e-1514-4224-8f70-1eed4d55bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668330036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.3668330036
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.6182763
Short name T168
Test name
Test status
Simulation time 367705210024 ps
CPU time 176.89 seconds
Started Jul 22 04:51:54 PM PDT 24
Finished Jul 22 04:54:52 PM PDT 24
Peak memory 209544 kb
Host smart-576be5f3-f671-4863-93d1-463e35d4b764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6182763 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.6182763
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3585532578
Short name T365
Test name
Test status
Simulation time 103792975102 ps
CPU time 259.47 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:53:08 PM PDT 24
Peak memory 201240 kb
Host smart-0a9134e6-eddb-4454-b1a1-fcd4d591a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585532578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.3585532578
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2243684240
Short name T72
Test name
Test status
Simulation time 78091380529 ps
CPU time 197.3 seconds
Started Jul 22 04:48:50 PM PDT 24
Finished Jul 22 04:52:08 PM PDT 24
Peak memory 201332 kb
Host smart-8c62d4c1-49b3-4f19-b4a9-96d55986b343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243684240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.2243684240
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2794482237
Short name T357
Test name
Test status
Simulation time 78855937601 ps
CPU time 207.72 seconds
Started Jul 22 04:48:20 PM PDT 24
Finished Jul 22 04:51:48 PM PDT 24
Peak memory 201288 kb
Host smart-065e9051-965b-4808-a0b1-f22948655685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794482237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.2794482237
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3988187762
Short name T73
Test name
Test status
Simulation time 40400451674 ps
CPU time 95.24 seconds
Started Jul 22 04:50:14 PM PDT 24
Finished Jul 22 04:51:59 PM PDT 24
Peak memory 209576 kb
Host smart-9b301b4e-24a3-4cd2-bbd2-303ae020b620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988187762 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3988187762
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3537750968
Short name T137
Test name
Test status
Simulation time 97405480836 ps
CPU time 217.14 seconds
Started Jul 22 04:50:10 PM PDT 24
Finished Jul 22 04:53:48 PM PDT 24
Peak memory 209640 kb
Host smart-c5512fd9-ff32-489a-be56-58a4a54ccb1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537750968 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.3537750968
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1361913845
Short name T369
Test name
Test status
Simulation time 66903246071 ps
CPU time 184.39 seconds
Started Jul 22 04:49:14 PM PDT 24
Finished Jul 22 04:52:19 PM PDT 24
Peak memory 201368 kb
Host smart-85f65e48-a656-40a7-bdff-9741c9565c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361913845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.1361913845
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.175214759
Short name T79
Test name
Test status
Simulation time 108279620209 ps
CPU time 15.53 seconds
Started Jul 22 04:51:28 PM PDT 24
Finished Jul 22 04:51:45 PM PDT 24
Peak memory 217700 kb
Host smart-8607645c-57fb-45ab-a992-a74a4b6e726e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175214759 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.175214759
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2124516792
Short name T289
Test name
Test status
Simulation time 2092241313 ps
CPU time 4.99 seconds
Started Jul 22 04:42:52 PM PDT 24
Finished Jul 22 04:42:58 PM PDT 24
Peak memory 202036 kb
Host smart-1f1d90b0-a0d9-4bde-bf3a-e405618967f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124516792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.2124516792
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1515185638
Short name T385
Test name
Test status
Simulation time 123126167881 ps
CPU time 297.75 seconds
Started Jul 22 04:49:38 PM PDT 24
Finished Jul 22 04:54:36 PM PDT 24
Peak memory 201260 kb
Host smart-b5ee819d-c38a-4d57-a5aa-b1f104bbc18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515185638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.1515185638
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.3205784283
Short name T169
Test name
Test status
Simulation time 278440646649 ps
CPU time 94.6 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:51:19 PM PDT 24
Peak memory 201160 kb
Host smart-644139c1-083d-4bd7-8552-00d826fcd468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205784283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.3205784283
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1132601335
Short name T363
Test name
Test status
Simulation time 46673935368 ps
CPU time 13.23 seconds
Started Jul 22 04:52:05 PM PDT 24
Finished Jul 22 04:52:19 PM PDT 24
Peak memory 201168 kb
Host smart-5a4f8fcc-0d41-4aa9-8f98-71f33618e55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132601335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.1132601335
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1998189491
Short name T234
Test name
Test status
Simulation time 4488815577 ps
CPU time 4.23 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:04 PM PDT 24
Peak memory 200920 kb
Host smart-1c06b6aa-963b-497c-8c4c-d0c412a145e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998189491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1998189491
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.696602919
Short name T172
Test name
Test status
Simulation time 5296183889 ps
CPU time 2.96 seconds
Started Jul 22 04:50:33 PM PDT 24
Finished Jul 22 04:50:36 PM PDT 24
Peak memory 200508 kb
Host smart-bb4aaa4f-70cb-443a-968b-c716175eebba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696602919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctr
l_edge_detect.696602919
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.402848368
Short name T209
Test name
Test status
Simulation time 27908592607 ps
CPU time 36.08 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:50:56 PM PDT 24
Peak memory 217688 kb
Host smart-99cbe4d4-a36c-4e28-a84d-a89cdd120435
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402848368 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.402848368
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1496201833
Short name T151
Test name
Test status
Simulation time 12489037189 ps
CPU time 8.53 seconds
Started Jul 22 04:50:57 PM PDT 24
Finished Jul 22 04:51:06 PM PDT 24
Peak memory 209520 kb
Host smart-0779b80d-566a-4ead-adae-8459dbbb1ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496201833 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.1496201833
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4161475263
Short name T375
Test name
Test status
Simulation time 42519640383 ps
CPU time 24.63 seconds
Started Jul 22 04:42:13 PM PDT 24
Finished Jul 22 04:42:38 PM PDT 24
Peak memory 202028 kb
Host smart-3ba20f77-7672-4b9a-a8ce-2132e48c917e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161475263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.4161475263
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4257609671
Short name T340
Test name
Test status
Simulation time 4068611008 ps
CPU time 3.42 seconds
Started Jul 22 04:42:07 PM PDT 24
Finished Jul 22 04:42:11 PM PDT 24
Peak memory 201824 kb
Host smart-10da4a8d-3f7d-4916-93ab-d95aef72cb01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257609671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.4257609671
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.197952420
Short name T133
Test name
Test status
Simulation time 41929543506 ps
CPU time 27.66 seconds
Started Jul 22 04:47:56 PM PDT 24
Finished Jul 22 04:48:24 PM PDT 24
Peak memory 209540 kb
Host smart-3a5c7494-4c9d-4d90-b0fb-02b0dbb63f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197952420 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.197952420
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1993997811
Short name T343
Test name
Test status
Simulation time 92852039743 ps
CPU time 247.84 seconds
Started Jul 22 04:48:47 PM PDT 24
Finished Jul 22 04:52:55 PM PDT 24
Peak memory 201152 kb
Host smart-262db52c-165e-4118-bcc7-0ee9a508488d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993997811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.1993997811
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4078557313
Short name T458
Test name
Test status
Simulation time 2558509423 ps
CPU time 1.42 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:50 PM PDT 24
Peak memory 200952 kb
Host smart-85c4d73f-6639-41bc-8885-a79bcfe82389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078557313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.4078557313
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.785967687
Short name T690
Test name
Test status
Simulation time 1454475849827 ps
CPU time 267.53 seconds
Started Jul 22 04:48:49 PM PDT 24
Finished Jul 22 04:53:17 PM PDT 24
Peak memory 201000 kb
Host smart-5cc7ef32-e2f3-4d07-bdc9-b80e513a8146
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785967687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ultra_low_pwr.785967687
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2818884735
Short name T352
Test name
Test status
Simulation time 76378239571 ps
CPU time 49.29 seconds
Started Jul 22 04:50:44 PM PDT 24
Finished Jul 22 04:51:34 PM PDT 24
Peak memory 200604 kb
Host smart-be180c30-907e-4c09-b4b2-767d43f001f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818884735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.2818884735
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.325123463
Short name T230
Test name
Test status
Simulation time 148591490638 ps
CPU time 95.12 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:51:15 PM PDT 24
Peak memory 201028 kb
Host smart-7733b0d0-f3f2-4f8a-bd3a-bf65f375b1f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325123463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_combo_detect.325123463
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3882840130
Short name T248
Test name
Test status
Simulation time 65287100283 ps
CPU time 39.08 seconds
Started Jul 22 04:50:38 PM PDT 24
Finished Jul 22 04:51:18 PM PDT 24
Peak memory 201224 kb
Host smart-3e820ee4-a59f-47c6-82aa-263ef474645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882840130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.3882840130
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3447875510
Short name T344
Test name
Test status
Simulation time 78461092323 ps
CPU time 53.54 seconds
Started Jul 22 04:51:16 PM PDT 24
Finished Jul 22 04:52:10 PM PDT 24
Peak memory 201152 kb
Host smart-9bd59185-6720-4af3-bede-8ab7cc7b17aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447875510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3447875510
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1696854593
Short name T384
Test name
Test status
Simulation time 252837884527 ps
CPU time 653.11 seconds
Started Jul 22 04:51:16 PM PDT 24
Finished Jul 22 05:02:10 PM PDT 24
Peak memory 201324 kb
Host smart-4d00a47b-03f6-43ad-8dae-7d960c544e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696854593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.1696854593
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.134354342
Short name T386
Test name
Test status
Simulation time 47955369616 ps
CPU time 16.39 seconds
Started Jul 22 04:51:33 PM PDT 24
Finished Jul 22 04:51:50 PM PDT 24
Peak memory 201216 kb
Host smart-dda7c98f-eafa-467c-b7ac-31dd3ca101c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134354342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.134354342
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.589627169
Short name T360
Test name
Test status
Simulation time 109617043915 ps
CPU time 252.05 seconds
Started Jul 22 04:52:00 PM PDT 24
Finished Jul 22 04:56:12 PM PDT 24
Peak memory 201204 kb
Host smart-c480742a-a506-44c1-ae4d-adbb87cba7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589627169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_wi
th_pre_cond.589627169
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.888200151
Short name T359
Test name
Test status
Simulation time 105389360810 ps
CPU time 273.96 seconds
Started Jul 22 04:48:38 PM PDT 24
Finished Jul 22 04:53:12 PM PDT 24
Peak memory 201184 kb
Host smart-9044a407-165e-40de-bd78-235812ec6ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888200151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wit
h_pre_cond.888200151
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.1912073645
Short name T17
Test name
Test status
Simulation time 14194340912 ps
CPU time 34.45 seconds
Started Jul 22 04:50:10 PM PDT 24
Finished Jul 22 04:50:45 PM PDT 24
Peak memory 200932 kb
Host smart-f0ec17a3-df85-4a47-9732-8135f1c99a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912073645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.1912073645
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1850003072
Short name T75
Test name
Test status
Simulation time 58789142732 ps
CPU time 135.54 seconds
Started Jul 22 04:49:48 PM PDT 24
Finished Jul 22 04:52:04 PM PDT 24
Peak memory 201272 kb
Host smart-031d23f6-e665-4ed2-9011-55e8e3f1f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850003072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.1850003072
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3139275441
Short name T51
Test name
Test status
Simulation time 26151375538 ps
CPU time 7.68 seconds
Started Jul 22 04:52:02 PM PDT 24
Finished Jul 22 04:52:11 PM PDT 24
Peak memory 201200 kb
Host smart-92fd0829-46d7-43c2-be81-807b554f33c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139275441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3139275441
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2512884180
Short name T805
Test name
Test status
Simulation time 3021295409 ps
CPU time 8.39 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:26 PM PDT 24
Peak memory 202144 kb
Host smart-1107714e-89b2-4f0b-9a18-46645bd44ab8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512884180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.2512884180
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3749450079
Short name T335
Test name
Test status
Simulation time 13520886331 ps
CPU time 10.62 seconds
Started Jul 22 04:42:07 PM PDT 24
Finished Jul 22 04:42:19 PM PDT 24
Peak memory 201992 kb
Host smart-150e22e3-a5e0-47b9-8367-70d470b025c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749450079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.3749450079
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2426380751
Short name T27
Test name
Test status
Simulation time 4030249220 ps
CPU time 11.51 seconds
Started Jul 22 04:42:13 PM PDT 24
Finished Jul 22 04:42:25 PM PDT 24
Peak memory 201824 kb
Host smart-668f22a8-0644-4098-8d4d-fb0422965d9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426380751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.2426380751
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1067868648
Short name T884
Test name
Test status
Simulation time 2154904414 ps
CPU time 2.36 seconds
Started Jul 22 04:42:06 PM PDT 24
Finished Jul 22 04:42:09 PM PDT 24
Peak memory 201948 kb
Host smart-f55e1e82-7b0a-45ce-8eee-3667e739eda8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067868648 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1067868648
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1406341992
Short name T305
Test name
Test status
Simulation time 2096108289 ps
CPU time 2.69 seconds
Started Jul 22 04:42:06 PM PDT 24
Finished Jul 22 04:42:09 PM PDT 24
Peak memory 201788 kb
Host smart-10315e9f-099f-4ddf-abda-3d5a30b22f61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406341992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1406341992
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3711759868
Short name T862
Test name
Test status
Simulation time 2012347618 ps
CPU time 5.3 seconds
Started Jul 22 04:42:06 PM PDT 24
Finished Jul 22 04:42:12 PM PDT 24
Peak memory 201756 kb
Host smart-6afe2e8b-5742-4557-8251-8c91c3b570e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711759868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.3711759868
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1605965923
Short name T835
Test name
Test status
Simulation time 10514991443 ps
CPU time 6.03 seconds
Started Jul 22 04:42:08 PM PDT 24
Finished Jul 22 04:42:15 PM PDT 24
Peak memory 202032 kb
Host smart-eae50106-062e-4a01-9ef4-79e0d01411a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605965923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.1605965923
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1837767289
Short name T834
Test name
Test status
Simulation time 2205792567 ps
CPU time 4.94 seconds
Started Jul 22 04:42:08 PM PDT 24
Finished Jul 22 04:42:13 PM PDT 24
Peak memory 202148 kb
Host smart-2afcc5b4-3f7a-41cb-9728-bc409f34a22e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837767289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.1837767289
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4138338698
Short name T866
Test name
Test status
Simulation time 2670283644 ps
CPU time 10.22 seconds
Started Jul 22 04:42:07 PM PDT 24
Finished Jul 22 04:42:18 PM PDT 24
Peak memory 201980 kb
Host smart-090005b4-0ca6-4ade-9ef8-a45c6a857b73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138338698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.4138338698
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1724838599
Short name T293
Test name
Test status
Simulation time 2236743813 ps
CPU time 2.09 seconds
Started Jul 22 04:42:07 PM PDT 24
Finished Jul 22 04:42:10 PM PDT 24
Peak memory 201932 kb
Host smart-2d718f9b-19d0-4cf5-9efc-0ac8c76bab45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724838599 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1724838599
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2893110318
Short name T30
Test name
Test status
Simulation time 2051230883 ps
CPU time 5.95 seconds
Started Jul 22 04:42:07 PM PDT 24
Finished Jul 22 04:42:13 PM PDT 24
Peak memory 202016 kb
Host smart-f8d7295d-e2ed-4a1c-9264-86eb5d0b77e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893110318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2893110318
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1810852496
Short name T844
Test name
Test status
Simulation time 2016656198 ps
CPU time 6.1 seconds
Started Jul 22 04:42:06 PM PDT 24
Finished Jul 22 04:42:12 PM PDT 24
Peak memory 201552 kb
Host smart-3dc25850-0c35-4079-a20e-10717f421153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810852496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1810852496
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3589612927
Short name T821
Test name
Test status
Simulation time 7491294564 ps
CPU time 15.24 seconds
Started Jul 22 04:42:09 PM PDT 24
Finished Jul 22 04:42:25 PM PDT 24
Peak memory 202060 kb
Host smart-ceb7b1eb-0484-4f13-b630-1cef574b5300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589612927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.3589612927
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1418790751
Short name T879
Test name
Test status
Simulation time 2085833123 ps
CPU time 4.98 seconds
Started Jul 22 04:42:09 PM PDT 24
Finished Jul 22 04:42:14 PM PDT 24
Peak memory 202036 kb
Host smart-bc2432d9-09b0-44ec-903c-13393e86b57a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418790751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.1418790751
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.909865305
Short name T823
Test name
Test status
Simulation time 22229684740 ps
CPU time 58.35 seconds
Started Jul 22 04:42:05 PM PDT 24
Finished Jul 22 04:43:04 PM PDT 24
Peak memory 202096 kb
Host smart-6a5daee5-6ce6-4a1f-a6e7-dbda9c8fe354
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909865305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_tl_intg_err.909865305
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1079041860
Short name T819
Test name
Test status
Simulation time 2060023378 ps
CPU time 6.24 seconds
Started Jul 22 04:42:36 PM PDT 24
Finished Jul 22 04:42:43 PM PDT 24
Peak memory 201828 kb
Host smart-e4c3575a-0863-4b61-bc11-fdb111d419c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079041860 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1079041860
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3330288525
Short name T887
Test name
Test status
Simulation time 2048584966 ps
CPU time 6.37 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:39 PM PDT 24
Peak memory 201832 kb
Host smart-0ec5c7aa-37a4-4625-b1e1-6727308ae2f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330288525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3330288525
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4169052070
Short name T818
Test name
Test status
Simulation time 2047926589 ps
CPU time 2 seconds
Started Jul 22 04:42:34 PM PDT 24
Finished Jul 22 04:42:37 PM PDT 24
Peak memory 201576 kb
Host smart-339f792c-4350-41c8-b617-b1004b5c96fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169052070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.4169052070
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2244502050
Short name T829
Test name
Test status
Simulation time 9868491131 ps
CPU time 7.13 seconds
Started Jul 22 04:42:31 PM PDT 24
Finished Jul 22 04:42:38 PM PDT 24
Peak memory 202076 kb
Host smart-dc022c53-1a0f-446f-b1a5-230a5ae2bb54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244502050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.2244502050
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2094858258
Short name T290
Test name
Test status
Simulation time 2075203443 ps
CPU time 7.1 seconds
Started Jul 22 04:42:31 PM PDT 24
Finished Jul 22 04:42:39 PM PDT 24
Peak memory 201944 kb
Host smart-c6b10661-a93d-4775-9bb0-5c5773013935
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094858258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.2094858258
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.576088982
Short name T849
Test name
Test status
Simulation time 22302325767 ps
CPU time 16.42 seconds
Started Jul 22 04:42:34 PM PDT 24
Finished Jul 22 04:42:51 PM PDT 24
Peak memory 202080 kb
Host smart-19853f88-959f-4301-b2a7-84950a3d9a54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576088982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_tl_intg_err.576088982
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4172783467
Short name T850
Test name
Test status
Simulation time 2080509595 ps
CPU time 2.25 seconds
Started Jul 22 04:42:35 PM PDT 24
Finished Jul 22 04:42:37 PM PDT 24
Peak memory 201820 kb
Host smart-08e068be-3981-4b9c-a35f-28b8b613db23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172783467 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4172783467
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.210875555
Short name T803
Test name
Test status
Simulation time 2043429165 ps
CPU time 3.66 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:37 PM PDT 24
Peak memory 201740 kb
Host smart-22617878-d998-44b6-aea8-84604eaadc65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210875555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_r
w.210875555
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.186088935
Short name T890
Test name
Test status
Simulation time 2038870598 ps
CPU time 1.88 seconds
Started Jul 22 04:42:36 PM PDT 24
Finished Jul 22 04:42:38 PM PDT 24
Peak memory 201520 kb
Host smart-abe8a9f5-bd62-40d0-89a1-4d5f32120dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186088935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.186088935
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1707146487
Short name T913
Test name
Test status
Simulation time 4855945052 ps
CPU time 12.52 seconds
Started Jul 22 04:42:34 PM PDT 24
Finished Jul 22 04:42:47 PM PDT 24
Peak memory 202048 kb
Host smart-dd41e418-0a3f-4115-bd1b-d82cbcbd3dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707146487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.1707146487
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.527556011
Short name T278
Test name
Test status
Simulation time 2283143433 ps
CPU time 5.29 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:39 PM PDT 24
Peak memory 201988 kb
Host smart-3a2d4c14-16b0-449c-bfe8-576ba5be72b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527556011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_error
s.527556011
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.951065578
Short name T845
Test name
Test status
Simulation time 22318063627 ps
CPU time 13.7 seconds
Started Jul 22 04:42:31 PM PDT 24
Finished Jul 22 04:42:46 PM PDT 24
Peak memory 202112 kb
Host smart-79a41799-0a63-4515-bf4c-943a1b0bc233
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951065578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_tl_intg_err.951065578
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.318868057
Short name T381
Test name
Test status
Simulation time 2062056586 ps
CPU time 2.3 seconds
Started Jul 22 04:42:49 PM PDT 24
Finished Jul 22 04:42:51 PM PDT 24
Peak memory 201756 kb
Host smart-0b1fd668-cce2-4651-8651-a00e040296c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318868057 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.318868057
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2037720137
Short name T878
Test name
Test status
Simulation time 2068122909 ps
CPU time 2.14 seconds
Started Jul 22 04:42:40 PM PDT 24
Finished Jul 22 04:42:43 PM PDT 24
Peak memory 201724 kb
Host smart-e2ea641d-512b-4b05-9946-d16fe85f987b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037720137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.2037720137
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2694257552
Short name T903
Test name
Test status
Simulation time 2060751712 ps
CPU time 1.41 seconds
Started Jul 22 04:42:41 PM PDT 24
Finished Jul 22 04:42:43 PM PDT 24
Peak memory 201488 kb
Host smart-f94205ee-75fe-4fc8-a358-15bbf9998aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694257552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2694257552
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1865920071
Short name T857
Test name
Test status
Simulation time 10324380188 ps
CPU time 9.22 seconds
Started Jul 22 04:42:41 PM PDT 24
Finished Jul 22 04:42:51 PM PDT 24
Peak memory 202132 kb
Host smart-2e71de88-35af-4f5a-a680-9b94903c84e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865920071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.1865920071
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.486750819
Short name T856
Test name
Test status
Simulation time 2094894498 ps
CPU time 2.85 seconds
Started Jul 22 04:42:40 PM PDT 24
Finished Jul 22 04:42:43 PM PDT 24
Peak memory 201924 kb
Host smart-b101eba0-9e3d-4944-9c3a-4f1e31a4e69b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486750819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_error
s.486750819
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3084121643
Short name T874
Test name
Test status
Simulation time 42491814491 ps
CPU time 32.59 seconds
Started Jul 22 04:42:42 PM PDT 24
Finished Jul 22 04:43:15 PM PDT 24
Peak memory 202172 kb
Host smart-b22d4114-39ed-4fe3-9538-052da8bef2f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084121643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.3084121643
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.310849528
Short name T815
Test name
Test status
Simulation time 2231624701 ps
CPU time 2.34 seconds
Started Jul 22 04:43:25 PM PDT 24
Finished Jul 22 04:43:28 PM PDT 24
Peak memory 202136 kb
Host smart-8cdf8b0d-4897-41d6-9648-5cc8026d5914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310849528 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.310849528
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1878447954
Short name T327
Test name
Test status
Simulation time 2040868191 ps
CPU time 3.23 seconds
Started Jul 22 04:42:49 PM PDT 24
Finished Jul 22 04:42:53 PM PDT 24
Peak memory 201796 kb
Host smart-060c6f0b-f194-48e1-9196-241f735ea0c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878447954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.1878447954
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1395500153
Short name T853
Test name
Test status
Simulation time 2020001777 ps
CPU time 2.93 seconds
Started Jul 22 04:42:42 PM PDT 24
Finished Jul 22 04:42:46 PM PDT 24
Peak memory 201528 kb
Host smart-1736a42a-6469-48ec-afbe-1fa00896eabc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395500153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.1395500153
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3764883803
Short name T817
Test name
Test status
Simulation time 5299583355 ps
CPU time 3.81 seconds
Started Jul 22 04:42:41 PM PDT 24
Finished Jul 22 04:42:45 PM PDT 24
Peak memory 202124 kb
Host smart-a38d3163-820d-4c08-851d-c12fb064b965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764883803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.3764883803
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2575628683
Short name T832
Test name
Test status
Simulation time 2089198379 ps
CPU time 4.46 seconds
Started Jul 22 04:42:49 PM PDT 24
Finished Jul 22 04:42:54 PM PDT 24
Peak memory 201948 kb
Host smart-4d440773-8794-4bb0-805a-6a14ac95bb0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575628683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.2575628683
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2095211697
Short name T284
Test name
Test status
Simulation time 2112175646 ps
CPU time 2.17 seconds
Started Jul 22 04:42:42 PM PDT 24
Finished Jul 22 04:42:44 PM PDT 24
Peak memory 201740 kb
Host smart-e3f56390-7597-44bc-bb4d-1c6d2bdd516c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095211697 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2095211697
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2137262360
Short name T338
Test name
Test status
Simulation time 2054926356 ps
CPU time 2.2 seconds
Started Jul 22 04:42:40 PM PDT 24
Finished Jul 22 04:42:43 PM PDT 24
Peak memory 201860 kb
Host smart-6307f46c-7ec3-4579-8e0a-9a17ac45a63e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137262360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.2137262360
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2885096565
Short name T860
Test name
Test status
Simulation time 2039631457 ps
CPU time 1.98 seconds
Started Jul 22 04:42:42 PM PDT 24
Finished Jul 22 04:42:45 PM PDT 24
Peak memory 201688 kb
Host smart-71ce2a35-7407-4837-bf2a-77ec17f35e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885096565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.2885096565
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.603420229
Short name T852
Test name
Test status
Simulation time 10044706448 ps
CPU time 6.63 seconds
Started Jul 22 04:43:46 PM PDT 24
Finished Jul 22 04:43:53 PM PDT 24
Peak memory 202108 kb
Host smart-656df0b0-c310-44c6-88d5-cbcfea879249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603420229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_same_csr_outstanding.603420229
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2739865782
Short name T839
Test name
Test status
Simulation time 2390929013 ps
CPU time 3.2 seconds
Started Jul 22 04:42:42 PM PDT 24
Finished Jul 22 04:42:45 PM PDT 24
Peak memory 202136 kb
Host smart-42ad7ccb-33d6-4d2f-a5c8-5d0778ed882a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739865782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2739865782
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1066042099
Short name T851
Test name
Test status
Simulation time 22699733584 ps
CPU time 12.8 seconds
Started Jul 22 04:42:41 PM PDT 24
Finished Jul 22 04:42:54 PM PDT 24
Peak memory 202224 kb
Host smart-3f447bba-5d14-4001-a0d9-61885c844e43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066042099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1066042099
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4258202807
Short name T830
Test name
Test status
Simulation time 2112167083 ps
CPU time 1.76 seconds
Started Jul 22 04:42:40 PM PDT 24
Finished Jul 22 04:42:42 PM PDT 24
Peak memory 201864 kb
Host smart-2ae1c33f-2dc2-45ee-a7b0-81a041d50547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258202807 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4258202807
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3559488453
Short name T339
Test name
Test status
Simulation time 2043099406 ps
CPU time 3.47 seconds
Started Jul 22 04:42:49 PM PDT 24
Finished Jul 22 04:42:53 PM PDT 24
Peak memory 201800 kb
Host smart-6f61f370-f56c-4057-abda-119a23a38e76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559488453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.3559488453
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1951052070
Short name T802
Test name
Test status
Simulation time 2015841121 ps
CPU time 4.84 seconds
Started Jul 22 04:42:49 PM PDT 24
Finished Jul 22 04:42:54 PM PDT 24
Peak memory 201508 kb
Host smart-c39f7711-96e5-4ac4-8fbc-6816c1ad511f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951052070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.1951052070
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3112635031
Short name T847
Test name
Test status
Simulation time 9733218975 ps
CPU time 13.38 seconds
Started Jul 22 04:42:41 PM PDT 24
Finished Jul 22 04:42:55 PM PDT 24
Peak memory 202084 kb
Host smart-cf0e31a7-d67a-4249-bdd6-07fb53c5db7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112635031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.3112635031
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3311251129
Short name T894
Test name
Test status
Simulation time 2513896814 ps
CPU time 2.57 seconds
Started Jul 22 04:42:39 PM PDT 24
Finished Jul 22 04:42:42 PM PDT 24
Peak memory 210244 kb
Host smart-c2e29f42-b442-41c7-9d9a-418163f3420a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311251129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3311251129
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2155250785
Short name T378
Test name
Test status
Simulation time 22315514670 ps
CPU time 31.11 seconds
Started Jul 22 04:42:41 PM PDT 24
Finished Jul 22 04:43:13 PM PDT 24
Peak memory 202096 kb
Host smart-10c94d9e-6189-4d46-91d2-801ee4941deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155250785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.2155250785
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3880278186
Short name T841
Test name
Test status
Simulation time 2076942111 ps
CPU time 6.66 seconds
Started Jul 22 04:42:48 PM PDT 24
Finished Jul 22 04:42:56 PM PDT 24
Peak memory 201840 kb
Host smart-2d7c8852-c446-4682-8355-2c9e8903c0da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880278186 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3880278186
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3825754130
Short name T337
Test name
Test status
Simulation time 2054590630 ps
CPU time 5.62 seconds
Started Jul 22 04:42:50 PM PDT 24
Finished Jul 22 04:42:56 PM PDT 24
Peak memory 201796 kb
Host smart-9a7c4f9f-a260-4e29-a031-fd906ed9c8c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825754130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3825754130
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4173739045
Short name T798
Test name
Test status
Simulation time 2038184461 ps
CPU time 1.77 seconds
Started Jul 22 04:42:51 PM PDT 24
Finished Jul 22 04:42:54 PM PDT 24
Peak memory 201748 kb
Host smart-705f4069-ed18-44a6-b336-d3c8eb8734cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173739045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.4173739045
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2861752638
Short name T843
Test name
Test status
Simulation time 10183138662 ps
CPU time 8.14 seconds
Started Jul 22 04:42:51 PM PDT 24
Finished Jul 22 04:43:00 PM PDT 24
Peak memory 202052 kb
Host smart-cc0234b4-d79e-4d8c-9b0f-e712bb2f9b97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861752638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2861752638
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1760418237
Short name T885
Test name
Test status
Simulation time 3022130459 ps
CPU time 2.9 seconds
Started Jul 22 04:42:48 PM PDT 24
Finished Jul 22 04:42:51 PM PDT 24
Peak memory 202080 kb
Host smart-2a37d97e-45ea-4927-81ec-4b4602cf4daa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760418237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1760418237
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3405347646
Short name T379
Test name
Test status
Simulation time 42500993359 ps
CPU time 29.7 seconds
Started Jul 22 04:42:51 PM PDT 24
Finished Jul 22 04:43:21 PM PDT 24
Peak memory 202152 kb
Host smart-e0f4e70e-ae8a-4aa6-b28c-6c2425f0b811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405347646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.3405347646
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1685486657
Short name T846
Test name
Test status
Simulation time 2144879589 ps
CPU time 1.96 seconds
Started Jul 22 04:43:57 PM PDT 24
Finished Jul 22 04:43:59 PM PDT 24
Peak memory 210176 kb
Host smart-685fbdaf-6243-4497-8524-2ecabcdb89e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685486657 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1685486657
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3996348362
Short name T336
Test name
Test status
Simulation time 2088330847 ps
CPU time 2.2 seconds
Started Jul 22 04:42:50 PM PDT 24
Finished Jul 22 04:42:52 PM PDT 24
Peak memory 201784 kb
Host smart-be5147b7-d58f-4b31-872b-b47618a4a495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996348362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.3996348362
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1360552638
Short name T897
Test name
Test status
Simulation time 2013683523 ps
CPU time 5.48 seconds
Started Jul 22 04:42:51 PM PDT 24
Finished Jul 22 04:42:56 PM PDT 24
Peak memory 201572 kb
Host smart-cbe36a04-225d-4be1-8995-61aca5e80227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360552638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.1360552638
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.500292608
Short name T872
Test name
Test status
Simulation time 5554625122 ps
CPU time 2.64 seconds
Started Jul 22 04:42:48 PM PDT 24
Finished Jul 22 04:42:51 PM PDT 24
Peak memory 202004 kb
Host smart-2fdf6040-12d7-4e34-8ff8-f788b78c6e68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500292608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.500292608
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2769079762
Short name T895
Test name
Test status
Simulation time 42432050966 ps
CPU time 115.26 seconds
Started Jul 22 04:43:57 PM PDT 24
Finished Jul 22 04:45:53 PM PDT 24
Peak memory 202060 kb
Host smart-d435662b-5b6d-4a49-8a7a-e722b5d530a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769079762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.2769079762
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1619180418
Short name T883
Test name
Test status
Simulation time 2405883246 ps
CPU time 1.65 seconds
Started Jul 22 04:42:51 PM PDT 24
Finished Jul 22 04:42:53 PM PDT 24
Peak memory 202020 kb
Host smart-7cffed6f-b771-4e1b-8ecd-5b959842741b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619180418 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1619180418
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3116738834
Short name T330
Test name
Test status
Simulation time 2053124918 ps
CPU time 5.88 seconds
Started Jul 22 04:42:49 PM PDT 24
Finished Jul 22 04:42:55 PM PDT 24
Peak memory 201796 kb
Host smart-72932276-007b-449d-a7ec-938392ebd786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116738834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.3116738834
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.626662780
Short name T899
Test name
Test status
Simulation time 2013963223 ps
CPU time 5.67 seconds
Started Jul 22 04:42:53 PM PDT 24
Finished Jul 22 04:42:59 PM PDT 24
Peak memory 201748 kb
Host smart-9c23f2d7-c486-4155-b08f-ed0fb7e0f901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626662780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_tes
t.626662780
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1187133954
Short name T827
Test name
Test status
Simulation time 5518951205 ps
CPU time 23.37 seconds
Started Jul 22 04:42:53 PM PDT 24
Finished Jul 22 04:43:17 PM PDT 24
Peak memory 202184 kb
Host smart-dbabce9c-4b54-427c-8b3d-0f30c5ff8658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187133954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.1187133954
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3405546602
Short name T875
Test name
Test status
Simulation time 2041176652 ps
CPU time 7.3 seconds
Started Jul 22 04:42:48 PM PDT 24
Finished Jul 22 04:42:55 PM PDT 24
Peak memory 201996 kb
Host smart-08990383-e0aa-4ec3-b99d-054d364d313d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405546602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.3405546602
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4274599467
Short name T29
Test name
Test status
Simulation time 2108741579 ps
CPU time 2.43 seconds
Started Jul 22 04:43:03 PM PDT 24
Finished Jul 22 04:43:06 PM PDT 24
Peak memory 201712 kb
Host smart-5f11a5ab-333a-4f2f-bd3e-bcd6b030f06f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274599467 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4274599467
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2821194941
Short name T908
Test name
Test status
Simulation time 2035011786 ps
CPU time 5.27 seconds
Started Jul 22 04:43:02 PM PDT 24
Finished Jul 22 04:43:08 PM PDT 24
Peak memory 201788 kb
Host smart-c48fd639-ecb0-4f30-a5b9-2ddbb097ad6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821194941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2821194941
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1818441776
Short name T811
Test name
Test status
Simulation time 2018286041 ps
CPU time 5.65 seconds
Started Jul 22 04:43:46 PM PDT 24
Finished Jul 22 04:43:52 PM PDT 24
Peak memory 201444 kb
Host smart-752ffb47-989c-434e-97f4-b9a5b5fa24f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818441776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.1818441776
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.706839329
Short name T876
Test name
Test status
Simulation time 2023168645 ps
CPU time 6.35 seconds
Started Jul 22 04:43:02 PM PDT 24
Finished Jul 22 04:43:09 PM PDT 24
Peak memory 201932 kb
Host smart-ba4e251c-fcce-4a0b-8f97-b9832ed98534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706839329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_error
s.706839329
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2061240764
Short name T377
Test name
Test status
Simulation time 42614456462 ps
CPU time 25.56 seconds
Started Jul 22 04:43:01 PM PDT 24
Finished Jul 22 04:43:27 PM PDT 24
Peak memory 202224 kb
Host smart-cd238169-aefa-48ea-b6dc-134c3e6ed8b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061240764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2061240764
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2651293043
Short name T806
Test name
Test status
Simulation time 2670749781 ps
CPU time 10.12 seconds
Started Jul 22 04:42:16 PM PDT 24
Finished Jul 22 04:42:27 PM PDT 24
Peak memory 202088 kb
Host smart-7b2cfcb7-26a3-490a-ad1f-cc1e2cc9cef7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651293043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.2651293043
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2848036683
Short name T333
Test name
Test status
Simulation time 3111721709 ps
CPU time 8.92 seconds
Started Jul 22 04:42:21 PM PDT 24
Finished Jul 22 04:42:30 PM PDT 24
Peak memory 202064 kb
Host smart-b8dfce2c-9d35-4c88-ad13-76512bc9b603
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848036683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.2848036683
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1209085861
Short name T332
Test name
Test status
Simulation time 4014319192 ps
CPU time 10.49 seconds
Started Jul 22 04:42:15 PM PDT 24
Finished Jul 22 04:42:26 PM PDT 24
Peak memory 201888 kb
Host smart-cb8e2dd0-23f8-456f-8bfa-50c0e49f1710
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209085861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.1209085861
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2161537094
Short name T898
Test name
Test status
Simulation time 2063085542 ps
CPU time 6.03 seconds
Started Jul 22 04:42:17 PM PDT 24
Finished Jul 22 04:42:24 PM PDT 24
Peak memory 217556 kb
Host smart-2366c582-3d2e-4e81-bc18-719eb76d2d47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161537094 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2161537094
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2573211067
Short name T861
Test name
Test status
Simulation time 2084744924 ps
CPU time 3.42 seconds
Started Jul 22 04:42:18 PM PDT 24
Finished Jul 22 04:42:22 PM PDT 24
Peak memory 201636 kb
Host smart-4dd42fb0-e2b7-4294-94ad-793c8e3c82ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573211067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.2573211067
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.661248498
Short name T801
Test name
Test status
Simulation time 2028518205 ps
CPU time 1.85 seconds
Started Jul 22 04:42:18 PM PDT 24
Finished Jul 22 04:42:20 PM PDT 24
Peak memory 201532 kb
Host smart-4c937a2e-4af5-4e85-a8a8-2f86919b2ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661248498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test
.661248498
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.445103497
Short name T880
Test name
Test status
Simulation time 4913599760 ps
CPU time 11.98 seconds
Started Jul 22 04:42:21 PM PDT 24
Finished Jul 22 04:42:33 PM PDT 24
Peak memory 202072 kb
Host smart-99435052-3c91-40a2-8a6b-8ac41cc3d408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445103497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
sysrst_ctrl_same_csr_outstanding.445103497
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2480646369
Short name T295
Test name
Test status
Simulation time 2474022788 ps
CPU time 4.03 seconds
Started Jul 22 04:42:16 PM PDT 24
Finished Jul 22 04:42:20 PM PDT 24
Peak memory 202048 kb
Host smart-43d55242-799c-4389-a661-2b294b3f074e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480646369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.2480646369
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1229552233
Short name T865
Test name
Test status
Simulation time 22231512056 ps
CPU time 23.88 seconds
Started Jul 22 04:42:16 PM PDT 24
Finished Jul 22 04:42:40 PM PDT 24
Peak memory 202140 kb
Host smart-d98e30c9-0c07-45ce-bc9a-173f85156951
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229552233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1229552233
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2205632245
Short name T825
Test name
Test status
Simulation time 2010986638 ps
CPU time 5.39 seconds
Started Jul 22 04:43:05 PM PDT 24
Finished Jul 22 04:43:10 PM PDT 24
Peak memory 201752 kb
Host smart-1f7aa832-43ca-4c06-922c-3c3c34f7447f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205632245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2205632245
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3147532142
Short name T863
Test name
Test status
Simulation time 2017739894 ps
CPU time 5.1 seconds
Started Jul 22 04:43:04 PM PDT 24
Finished Jul 22 04:43:10 PM PDT 24
Peak memory 201672 kb
Host smart-cd07cc06-c2f3-477f-830c-553e2f710971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147532142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.3147532142
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.794673103
Short name T886
Test name
Test status
Simulation time 2017838819 ps
CPU time 5.81 seconds
Started Jul 22 04:43:03 PM PDT 24
Finished Jul 22 04:43:10 PM PDT 24
Peak memory 201488 kb
Host smart-4f37c338-bbf2-4245-9b03-afa86f671548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794673103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_tes
t.794673103
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4167577500
Short name T804
Test name
Test status
Simulation time 2034818645 ps
CPU time 1.81 seconds
Started Jul 22 04:43:04 PM PDT 24
Finished Jul 22 04:43:06 PM PDT 24
Peak memory 201752 kb
Host smart-c4957626-e19b-426f-a5cd-86e3ff493c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167577500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.4167577500
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3978845175
Short name T905
Test name
Test status
Simulation time 2036865014 ps
CPU time 1.86 seconds
Started Jul 22 04:43:02 PM PDT 24
Finished Jul 22 04:43:04 PM PDT 24
Peak memory 201496 kb
Host smart-fa1bfcbe-16b2-49e5-aeae-7b28ffd0bfbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978845175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.3978845175
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.63595009
Short name T848
Test name
Test status
Simulation time 2016459517 ps
CPU time 5.16 seconds
Started Jul 22 04:43:04 PM PDT 24
Finished Jul 22 04:43:10 PM PDT 24
Peak memory 201672 kb
Host smart-292d5309-1024-461c-a7e9-e05f9b0bd13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63595009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test
.63595009
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1378537104
Short name T810
Test name
Test status
Simulation time 2015001816 ps
CPU time 3.07 seconds
Started Jul 22 04:43:04 PM PDT 24
Finished Jul 22 04:43:08 PM PDT 24
Peak memory 201556 kb
Host smart-71750de7-d76e-42a8-b890-f95f630ebad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378537104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.1378537104
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1642716297
Short name T911
Test name
Test status
Simulation time 2037221640 ps
CPU time 1.87 seconds
Started Jul 22 04:43:03 PM PDT 24
Finished Jul 22 04:43:05 PM PDT 24
Peak memory 201640 kb
Host smart-f008ade2-ddb2-463f-bb54-fb39e1ea7be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642716297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.1642716297
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3953608499
Short name T842
Test name
Test status
Simulation time 2017767324 ps
CPU time 5.83 seconds
Started Jul 22 04:43:02 PM PDT 24
Finished Jul 22 04:43:08 PM PDT 24
Peak memory 201692 kb
Host smart-52a7198f-bcd1-4214-82ca-f27ece1d0f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953608499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.3953608499
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1364651590
Short name T900
Test name
Test status
Simulation time 2014158792 ps
CPU time 5.92 seconds
Started Jul 22 04:43:57 PM PDT 24
Finished Jul 22 04:44:04 PM PDT 24
Peak memory 201660 kb
Host smart-5148239b-bb65-4fcd-aeb8-d37ef73a977f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364651590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.1364651590
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1726641312
Short name T904
Test name
Test status
Simulation time 2324287657 ps
CPU time 3.52 seconds
Started Jul 22 04:42:19 PM PDT 24
Finished Jul 22 04:42:23 PM PDT 24
Peak memory 201996 kb
Host smart-11476ada-df53-42ea-b2ef-0a2d17c3e04c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726641312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.1726641312
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1958171492
Short name T286
Test name
Test status
Simulation time 39582875032 ps
CPU time 30.26 seconds
Started Jul 22 04:42:18 PM PDT 24
Finished Jul 22 04:42:49 PM PDT 24
Peak memory 202152 kb
Host smart-0460c463-72fd-431b-8ae7-e86231deb173
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958171492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.1958171492
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2774561304
Short name T889
Test name
Test status
Simulation time 4012208962 ps
CPU time 11.13 seconds
Started Jul 22 04:42:16 PM PDT 24
Finished Jul 22 04:42:28 PM PDT 24
Peak memory 201736 kb
Host smart-f89ab0ce-3d76-45d6-bbc5-9757f8b2886b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774561304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.2774561304
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2471195580
Short name T831
Test name
Test status
Simulation time 2086061461 ps
CPU time 3.46 seconds
Started Jul 22 04:42:25 PM PDT 24
Finished Jul 22 04:42:29 PM PDT 24
Peak memory 210212 kb
Host smart-9d6d4646-e5a7-4487-9be2-af003f9b5aea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471195580 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2471195580
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2874846105
Short name T331
Test name
Test status
Simulation time 2038760494 ps
CPU time 5.67 seconds
Started Jul 22 04:43:33 PM PDT 24
Finished Jul 22 04:43:39 PM PDT 24
Peak memory 201656 kb
Host smart-f2fe8e8e-355e-4a9a-bfad-3abf20b9a841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874846105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.2874846105
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1261177099
Short name T912
Test name
Test status
Simulation time 2011231785 ps
CPU time 5.8 seconds
Started Jul 22 04:42:21 PM PDT 24
Finished Jul 22 04:42:28 PM PDT 24
Peak memory 201476 kb
Host smart-86fec8fb-873f-47fe-a979-7a9fae3d0718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261177099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1261177099
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.4036238667
Short name T901
Test name
Test status
Simulation time 8357339493 ps
CPU time 4.6 seconds
Started Jul 22 04:43:34 PM PDT 24
Finished Jul 22 04:43:39 PM PDT 24
Peak memory 202088 kb
Host smart-94961097-5a7c-40c8-bb92-03de5332671c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036238667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.4036238667
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2277765146
Short name T868
Test name
Test status
Simulation time 2389091679 ps
CPU time 3.6 seconds
Started Jul 22 04:42:18 PM PDT 24
Finished Jul 22 04:42:22 PM PDT 24
Peak memory 210280 kb
Host smart-8ef5ae91-aaba-4235-a633-9b4929d6c7a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277765146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.2277765146
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3366718197
Short name T867
Test name
Test status
Simulation time 22304364494 ps
CPU time 14.69 seconds
Started Jul 22 04:42:18 PM PDT 24
Finished Jul 22 04:42:33 PM PDT 24
Peak memory 202148 kb
Host smart-58f8c645-3313-4c49-a13e-4662e7ba845c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366718197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3366718197
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.235026864
Short name T799
Test name
Test status
Simulation time 2092251841 ps
CPU time 1.1 seconds
Started Jul 22 04:43:02 PM PDT 24
Finished Jul 22 04:43:04 PM PDT 24
Peak memory 201448 kb
Host smart-1de17ef8-11fa-4df3-87f5-76e0905b2797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235026864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_tes
t.235026864
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2660410643
Short name T826
Test name
Test status
Simulation time 2039773993 ps
CPU time 2.12 seconds
Started Jul 22 04:43:03 PM PDT 24
Finished Jul 22 04:43:06 PM PDT 24
Peak memory 201668 kb
Host smart-760e96b5-d9cf-4cfc-a669-48bef9e5c4a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660410643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2660410643
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2406719773
Short name T795
Test name
Test status
Simulation time 2023170478 ps
CPU time 3.05 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:43:40 PM PDT 24
Peak memory 201604 kb
Host smart-e3d8bc95-19a9-42a2-8eaa-dc3e5c72618b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406719773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.2406719773
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2149799675
Short name T794
Test name
Test status
Simulation time 2019524861 ps
CPU time 3.62 seconds
Started Jul 22 04:43:03 PM PDT 24
Finished Jul 22 04:43:07 PM PDT 24
Peak memory 201644 kb
Host smart-400fc7a8-dc44-48d6-9f2f-367c12d794ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149799675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2149799675
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2892181727
Short name T809
Test name
Test status
Simulation time 2010129960 ps
CPU time 4.82 seconds
Started Jul 22 04:43:02 PM PDT 24
Finished Jul 22 04:43:07 PM PDT 24
Peak memory 201524 kb
Host smart-58459d81-da57-4748-96e5-0f554ed99dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892181727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.2892181727
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3126470513
Short name T902
Test name
Test status
Simulation time 2015273157 ps
CPU time 5.89 seconds
Started Jul 22 04:43:10 PM PDT 24
Finished Jul 22 04:43:17 PM PDT 24
Peak memory 201592 kb
Host smart-07b5c79a-f335-4eb4-97ff-ee48fb14da4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126470513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.3126470513
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.643904316
Short name T854
Test name
Test status
Simulation time 2081533474 ps
CPU time 1.15 seconds
Started Jul 22 04:43:09 PM PDT 24
Finished Jul 22 04:43:11 PM PDT 24
Peak memory 201656 kb
Host smart-7e1137e5-b82a-4e9c-a1f1-421dbf3b0162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643904316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_tes
t.643904316
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.905325999
Short name T828
Test name
Test status
Simulation time 2012573028 ps
CPU time 5.5 seconds
Started Jul 22 04:43:13 PM PDT 24
Finished Jul 22 04:43:19 PM PDT 24
Peak memory 201680 kb
Host smart-c931f71d-feb4-4889-969e-67aa5ab06425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905325999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_tes
t.905325999
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3131607430
Short name T800
Test name
Test status
Simulation time 2051027639 ps
CPU time 1.56 seconds
Started Jul 22 04:43:13 PM PDT 24
Finished Jul 22 04:43:15 PM PDT 24
Peak memory 201692 kb
Host smart-f4a3da1d-19f7-46f2-9d00-06b416c3a396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131607430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.3131607430
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.230903379
Short name T855
Test name
Test status
Simulation time 2027679183 ps
CPU time 1.95 seconds
Started Jul 22 04:43:09 PM PDT 24
Finished Jul 22 04:43:12 PM PDT 24
Peak memory 201500 kb
Host smart-977df60e-abdb-4e1b-8056-ead959597f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230903379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_tes
t.230903379
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.481112
Short name T328
Test name
Test status
Simulation time 3317609291 ps
CPU time 4.97 seconds
Started Jul 22 04:42:24 PM PDT 24
Finished Jul 22 04:42:30 PM PDT 24
Peak memory 202148 kb
Host smart-3afb22c0-f578-4e01-a327-9b349cc3fa19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr
_aliasing.481112
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.616045570
Short name T910
Test name
Test status
Simulation time 38830468093 ps
CPU time 49.12 seconds
Started Jul 22 04:42:24 PM PDT 24
Finished Jul 22 04:43:14 PM PDT 24
Peak memory 202016 kb
Host smart-53aae559-2031-4e3d-8fef-c6f58699571e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616045570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_bit_bash.616045570
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2935742404
Short name T341
Test name
Test status
Simulation time 6104170524 ps
CPU time 4.33 seconds
Started Jul 22 04:42:24 PM PDT 24
Finished Jul 22 04:42:29 PM PDT 24
Peak memory 201780 kb
Host smart-9df45e5c-222f-44cc-9611-d409c814947e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935742404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.2935742404
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153797278
Short name T858
Test name
Test status
Simulation time 2066763588 ps
CPU time 6.68 seconds
Started Jul 22 04:42:23 PM PDT 24
Finished Jul 22 04:42:31 PM PDT 24
Peak memory 201776 kb
Host smart-3f1861e3-8056-4c39-8999-924ebd373ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153797278 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153797278
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2440668965
Short name T329
Test name
Test status
Simulation time 2051424814 ps
CPU time 3.51 seconds
Started Jul 22 04:43:14 PM PDT 24
Finished Jul 22 04:43:18 PM PDT 24
Peak memory 201808 kb
Host smart-22dce261-b7c4-49dd-a5db-27b755af1929
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440668965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.2440668965
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.178849035
Short name T822
Test name
Test status
Simulation time 2025337152 ps
CPU time 3.15 seconds
Started Jul 22 04:42:24 PM PDT 24
Finished Jul 22 04:42:28 PM PDT 24
Peak memory 201488 kb
Host smart-7834e5e6-73cb-4f6b-a266-9f7626af933c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178849035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test
.178849035
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.4170238337
Short name T22
Test name
Test status
Simulation time 4934125570 ps
CPU time 12.34 seconds
Started Jul 22 04:42:23 PM PDT 24
Finished Jul 22 04:42:36 PM PDT 24
Peak memory 202104 kb
Host smart-5d0fe2e3-4381-4ddc-8668-2ce7bf26c020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170238337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.4170238337
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3993975486
Short name T873
Test name
Test status
Simulation time 42893380697 ps
CPU time 11.34 seconds
Started Jul 22 04:42:25 PM PDT 24
Finished Jul 22 04:42:37 PM PDT 24
Peak memory 202160 kb
Host smart-9c4f338e-1d2a-4903-8a16-8a489c0682b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993975486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.3993975486
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3963766882
Short name T837
Test name
Test status
Simulation time 2031695483 ps
CPU time 1.78 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:13 PM PDT 24
Peak memory 201704 kb
Host smart-3f74d8b9-c1b7-4cdd-91c4-af82edd8e094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963766882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.3963766882
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1109578478
Short name T808
Test name
Test status
Simulation time 2014318146 ps
CPU time 5.83 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:18 PM PDT 24
Peak memory 201472 kb
Host smart-14ed2449-1b70-4737-8a69-b01c398c1385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109578478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.1109578478
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.4224616505
Short name T797
Test name
Test status
Simulation time 2009778318 ps
CPU time 5.72 seconds
Started Jul 22 04:43:12 PM PDT 24
Finished Jul 22 04:43:18 PM PDT 24
Peak memory 201436 kb
Host smart-5b3b4893-a149-4bf6-80c3-642f7cb7e476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224616505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.4224616505
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1924284911
Short name T906
Test name
Test status
Simulation time 2037884188 ps
CPU time 1.91 seconds
Started Jul 22 04:43:12 PM PDT 24
Finished Jul 22 04:43:14 PM PDT 24
Peak memory 201520 kb
Host smart-b624ab03-8849-49d9-8273-78f81415ba6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924284911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.1924284911
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2619113378
Short name T796
Test name
Test status
Simulation time 2016922335 ps
CPU time 5.64 seconds
Started Jul 22 04:43:12 PM PDT 24
Finished Jul 22 04:43:18 PM PDT 24
Peak memory 201476 kb
Host smart-57d3a74a-153b-4180-b29b-cbf9d5eab274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619113378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2619113378
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2089122279
Short name T807
Test name
Test status
Simulation time 2085835210 ps
CPU time 1.22 seconds
Started Jul 22 04:43:13 PM PDT 24
Finished Jul 22 04:43:15 PM PDT 24
Peak memory 201556 kb
Host smart-d47fd826-a334-4f5f-874d-7e652ac3a584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089122279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.2089122279
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1011758458
Short name T864
Test name
Test status
Simulation time 2069039471 ps
CPU time 1.46 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:13 PM PDT 24
Peak memory 201568 kb
Host smart-40bca77c-8bda-4442-83f1-c6ccb426ba81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011758458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1011758458
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.460085399
Short name T871
Test name
Test status
Simulation time 2021126740 ps
CPU time 3.15 seconds
Started Jul 22 04:43:15 PM PDT 24
Finished Jul 22 04:43:18 PM PDT 24
Peak memory 201504 kb
Host smart-4c109a84-33ea-4f8b-8202-67ece7d83128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460085399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_tes
t.460085399
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1899466915
Short name T836
Test name
Test status
Simulation time 2107861184 ps
CPU time 0.95 seconds
Started Jul 22 04:43:10 PM PDT 24
Finished Jul 22 04:43:11 PM PDT 24
Peak memory 201492 kb
Host smart-2f70a05f-96f3-4000-86b7-af930b9bdedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899466915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.1899466915
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3346747499
Short name T820
Test name
Test status
Simulation time 2039866436 ps
CPU time 1.7 seconds
Started Jul 22 04:43:10 PM PDT 24
Finished Jul 22 04:43:13 PM PDT 24
Peak memory 201584 kb
Host smart-6a9990da-7a87-43fd-a756-7e24472f1b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346747499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.3346747499
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3049961898
Short name T882
Test name
Test status
Simulation time 2044773286 ps
CPU time 5.56 seconds
Started Jul 22 04:42:23 PM PDT 24
Finished Jul 22 04:42:29 PM PDT 24
Peak memory 201928 kb
Host smart-1d9034f5-24bc-4cda-8ac8-9698da76313f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049961898 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3049961898
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1113268224
Short name T334
Test name
Test status
Simulation time 2077758200 ps
CPU time 4.94 seconds
Started Jul 22 04:42:25 PM PDT 24
Finished Jul 22 04:42:31 PM PDT 24
Peak memory 201860 kb
Host smart-9a010cc0-9c25-4e6c-b6cb-81e5426717c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113268224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.1113268224
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2929950635
Short name T816
Test name
Test status
Simulation time 2019198920 ps
CPU time 3.09 seconds
Started Jul 22 04:42:25 PM PDT 24
Finished Jul 22 04:42:29 PM PDT 24
Peak memory 201560 kb
Host smart-e35c14d5-388f-4ad6-a27d-1af165410b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929950635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.2929950635
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.4155089686
Short name T840
Test name
Test status
Simulation time 4905081137 ps
CPU time 10.56 seconds
Started Jul 22 04:42:23 PM PDT 24
Finished Jul 22 04:42:34 PM PDT 24
Peak memory 202112 kb
Host smart-d8a742b2-8de7-4192-87a8-5bcb44d44b12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155089686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.4155089686
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.732396835
Short name T812
Test name
Test status
Simulation time 2318179113 ps
CPU time 5.65 seconds
Started Jul 22 04:42:23 PM PDT 24
Finished Jul 22 04:42:30 PM PDT 24
Peak memory 202108 kb
Host smart-c5633462-b7c8-43dd-a82c-e9a97c3cf798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732396835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors
.732396835
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3447296377
Short name T376
Test name
Test status
Simulation time 22314319512 ps
CPU time 30.49 seconds
Started Jul 22 04:42:24 PM PDT 24
Finished Jul 22 04:42:55 PM PDT 24
Peak memory 202080 kb
Host smart-118624dd-0917-4f2a-b703-7de5da8ca60f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447296377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3447296377
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2218809531
Short name T909
Test name
Test status
Simulation time 2102460820 ps
CPU time 2.04 seconds
Started Jul 22 04:42:33 PM PDT 24
Finished Jul 22 04:42:36 PM PDT 24
Peak memory 201764 kb
Host smart-62ed181d-4c51-4c9d-a6cf-d0851e9bd593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218809531 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2218809531
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1126824707
Short name T881
Test name
Test status
Simulation time 2111043557 ps
CPU time 2.07 seconds
Started Jul 22 04:42:25 PM PDT 24
Finished Jul 22 04:42:28 PM PDT 24
Peak memory 201768 kb
Host smart-a9ea431d-67cf-4c6b-999d-717131cbcacb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126824707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.1126824707
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1312703889
Short name T896
Test name
Test status
Simulation time 2017060239 ps
CPU time 3.17 seconds
Started Jul 22 04:42:24 PM PDT 24
Finished Jul 22 04:42:28 PM PDT 24
Peak memory 201668 kb
Host smart-a9b346c9-0806-446f-861b-51a4f6b47168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312703889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.1312703889
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1499483704
Short name T869
Test name
Test status
Simulation time 4430211881 ps
CPU time 5.72 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:38 PM PDT 24
Peak memory 201904 kb
Host smart-d6a2e162-7f2b-429f-a516-4783fb2d94bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499483704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.1499483704
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3544958887
Short name T813
Test name
Test status
Simulation time 2510897523 ps
CPU time 4.19 seconds
Started Jul 22 04:42:23 PM PDT 24
Finished Jul 22 04:42:28 PM PDT 24
Peak memory 210172 kb
Host smart-b73afe5b-b1c8-4061-b204-6d72a5781802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544958887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.3544958887
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3505470678
Short name T870
Test name
Test status
Simulation time 42480316709 ps
CPU time 113.87 seconds
Started Jul 22 04:42:22 PM PDT 24
Finished Jul 22 04:44:17 PM PDT 24
Peak memory 202160 kb
Host smart-8a9d6b07-b1c5-4c8a-861a-5063484a271d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505470678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3505470678
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3096376315
Short name T833
Test name
Test status
Simulation time 2199585188 ps
CPU time 2.4 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:36 PM PDT 24
Peak memory 201956 kb
Host smart-8be9da9e-0937-4fa2-b777-83b36d9af202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096376315 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3096376315
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2796336024
Short name T814
Test name
Test status
Simulation time 2075350725 ps
CPU time 1.98 seconds
Started Jul 22 04:42:35 PM PDT 24
Finished Jul 22 04:42:38 PM PDT 24
Peak memory 201672 kb
Host smart-074fdd1a-9d8f-4977-9c1a-0e8cf2f1f54f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796336024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.2796336024
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1709665447
Short name T888
Test name
Test status
Simulation time 2010881134 ps
CPU time 5.95 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:39 PM PDT 24
Peak memory 201508 kb
Host smart-0bf9a9dc-a59e-4acf-9090-d16f58b67f80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709665447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.1709665447
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1009105138
Short name T891
Test name
Test status
Simulation time 10684484354 ps
CPU time 14.42 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:48 PM PDT 24
Peak memory 202100 kb
Host smart-b2a66905-0aaa-4612-948b-bf1ad14c1ab5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009105138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.1009105138
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3242244778
Short name T859
Test name
Test status
Simulation time 2062184683 ps
CPU time 4.79 seconds
Started Jul 22 04:42:30 PM PDT 24
Finished Jul 22 04:42:36 PM PDT 24
Peak memory 201996 kb
Host smart-e167dede-ad7a-45cc-8c05-3067ad77c52f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242244778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.3242244778
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3184182215
Short name T914
Test name
Test status
Simulation time 42486282702 ps
CPU time 31.56 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:43:05 PM PDT 24
Peak memory 202096 kb
Host smart-3ecbcf42-2ff3-417f-b274-cf74c5c3b619
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184182215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.3184182215
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1685698393
Short name T877
Test name
Test status
Simulation time 2053240294 ps
CPU time 6.24 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:39 PM PDT 24
Peak memory 201736 kb
Host smart-e4ce2a20-8436-41e2-bece-3ede4aa2a384
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685698393 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1685698393
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3861023782
Short name T285
Test name
Test status
Simulation time 2054123373 ps
CPU time 6.11 seconds
Started Jul 22 04:42:33 PM PDT 24
Finished Jul 22 04:42:40 PM PDT 24
Peak memory 201860 kb
Host smart-e0b8e013-5515-46b0-92b3-8d4ba11263bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861023782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3861023782
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1568022058
Short name T892
Test name
Test status
Simulation time 2041987069 ps
CPU time 1.83 seconds
Started Jul 22 04:42:31 PM PDT 24
Finished Jul 22 04:42:34 PM PDT 24
Peak memory 201744 kb
Host smart-74263302-2f69-4c2d-9010-a460f4a87ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568022058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.1568022058
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3228803574
Short name T907
Test name
Test status
Simulation time 9146016057 ps
CPU time 15.77 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:28 PM PDT 24
Peak memory 202056 kb
Host smart-26bd764d-6bb9-4d7f-857d-f3848b9d3e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228803574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.3228803574
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3701072080
Short name T288
Test name
Test status
Simulation time 2127450647 ps
CPU time 7.28 seconds
Started Jul 22 04:42:30 PM PDT 24
Finished Jul 22 04:42:38 PM PDT 24
Peak memory 210092 kb
Host smart-95ac2590-e8ba-405f-b2f6-f788298ff583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701072080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.3701072080
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1755239120
Short name T380
Test name
Test status
Simulation time 42467114385 ps
CPU time 99.07 seconds
Started Jul 22 04:42:34 PM PDT 24
Finished Jul 22 04:44:13 PM PDT 24
Peak memory 202128 kb
Host smart-b9862b62-0892-46d3-a493-797d5a7aedf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755239120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1755239120
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153285065
Short name T294
Test name
Test status
Simulation time 2076896382 ps
CPU time 3.61 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:16 PM PDT 24
Peak memory 201756 kb
Host smart-111316d1-8f02-4f76-ae66-2bbc9d4c9cb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153285065 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153285065
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2319251394
Short name T893
Test name
Test status
Simulation time 2057042819 ps
CPU time 1.97 seconds
Started Jul 22 04:42:32 PM PDT 24
Finished Jul 22 04:42:35 PM PDT 24
Peak memory 201780 kb
Host smart-9e2fd50c-d4dc-4125-a965-344e138e60c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319251394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.2319251394
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.17928048
Short name T838
Test name
Test status
Simulation time 2031632729 ps
CPU time 1.84 seconds
Started Jul 22 04:42:31 PM PDT 24
Finished Jul 22 04:42:33 PM PDT 24
Peak memory 201580 kb
Host smart-54602600-760d-4793-9fea-284cf679ca78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17928048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.17928048
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.731043262
Short name T23
Test name
Test status
Simulation time 7914501646 ps
CPU time 19.06 seconds
Started Jul 22 04:42:36 PM PDT 24
Finished Jul 22 04:42:56 PM PDT 24
Peak memory 202104 kb
Host smart-5880b4a0-f64a-489b-8aac-443bf4ef60a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731043262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
sysrst_ctrl_same_csr_outstanding.731043262
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4110577352
Short name T824
Test name
Test status
Simulation time 2445129490 ps
CPU time 3.04 seconds
Started Jul 22 04:42:31 PM PDT 24
Finished Jul 22 04:42:34 PM PDT 24
Peak memory 202100 kb
Host smart-3099384e-d22c-427e-a401-21f10a6cafc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110577352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.4110577352
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2656401860
Short name T283
Test name
Test status
Simulation time 22209484188 ps
CPU time 60.49 seconds
Started Jul 22 04:42:31 PM PDT 24
Finished Jul 22 04:43:32 PM PDT 24
Peak memory 202156 kb
Host smart-6ff9a75f-75e0-433f-8af7-f8bd5d6f28d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656401860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2656401860
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.359443905
Short name T641
Test name
Test status
Simulation time 2050268805 ps
CPU time 1.46 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:47:52 PM PDT 24
Peak memory 200856 kb
Host smart-a72cec5e-255c-4056-970f-2e971d8324c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359443905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.359443905
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2511135905
Short name T115
Test name
Test status
Simulation time 62085244063 ps
CPU time 40.35 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:48:31 PM PDT 24
Peak memory 201032 kb
Host smart-0229c52b-e1bc-481b-9d2c-41805a2e620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511135905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.2511135905
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.3413655612
Short name T581
Test name
Test status
Simulation time 144569280393 ps
CPU time 95.51 seconds
Started Jul 22 04:47:51 PM PDT 24
Finished Jul 22 04:49:27 PM PDT 24
Peak memory 201312 kb
Host smart-3df7e86c-926c-4acb-8c60-c798cbfa85ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413655612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.3413655612
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2538849067
Short name T553
Test name
Test status
Simulation time 2242378474 ps
CPU time 6.53 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:47:59 PM PDT 24
Peak memory 200952 kb
Host smart-07ba214d-28e1-4901-a961-3ed88ccf38a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538849067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2538849067
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.581650337
Short name T613
Test name
Test status
Simulation time 2551085937 ps
CPU time 2.36 seconds
Started Jul 22 04:47:48 PM PDT 24
Finished Jul 22 04:47:51 PM PDT 24
Peak memory 201012 kb
Host smart-4548eb60-f12a-4514-b1ea-6390ce761892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581650337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.581650337
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3878445931
Short name T777
Test name
Test status
Simulation time 27605837456 ps
CPU time 19.83 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:48:13 PM PDT 24
Peak memory 201296 kb
Host smart-59f437ed-00b0-4916-8318-75a1a960bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878445931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.3878445931
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1962186149
Short name T455
Test name
Test status
Simulation time 3927773828 ps
CPU time 3.12 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:47:54 PM PDT 24
Peak memory 201276 kb
Host smart-ac981348-a6d9-41f2-a02c-4cd416f1aa51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962186149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.1962186149
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1106673661
Short name T193
Test name
Test status
Simulation time 2791619004 ps
CPU time 2.32 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:47:53 PM PDT 24
Peak memory 200868 kb
Host smart-130679cf-627a-4eee-a150-0d269f28ccbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106673661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.1106673661
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1511111072
Short name T411
Test name
Test status
Simulation time 2614541107 ps
CPU time 7.03 seconds
Started Jul 22 04:48:33 PM PDT 24
Finished Jul 22 04:48:40 PM PDT 24
Peak memory 200940 kb
Host smart-383ab174-8d61-467b-a7d6-c165eca7eb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511111072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1511111072
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1715820345
Short name T631
Test name
Test status
Simulation time 2449556719 ps
CPU time 6.94 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:47:58 PM PDT 24
Peak memory 201020 kb
Host smart-5b44a13e-0fe6-4a09-b612-4b090aef70d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715820345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1715820345
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1602616293
Short name T456
Test name
Test status
Simulation time 2026676633 ps
CPU time 4.03 seconds
Started Jul 22 04:47:53 PM PDT 24
Finished Jul 22 04:47:58 PM PDT 24
Peak memory 200868 kb
Host smart-20b021d4-2542-4a33-b1a1-6114d5537215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602616293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1602616293
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3609375079
Short name T675
Test name
Test status
Simulation time 2515542461 ps
CPU time 7.16 seconds
Started Jul 22 04:48:16 PM PDT 24
Finished Jul 22 04:48:24 PM PDT 24
Peak memory 200908 kb
Host smart-bb45f3e0-635d-419d-9d46-f007bbc3e72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609375079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3609375079
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.623389431
Short name T617
Test name
Test status
Simulation time 2111517036 ps
CPU time 6.01 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:47:56 PM PDT 24
Peak memory 200828 kb
Host smart-7428fa8d-31ee-4ebe-8d39-895c000b1f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623389431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.623389431
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.3253870805
Short name T759
Test name
Test status
Simulation time 13039117774 ps
CPU time 29.94 seconds
Started Jul 22 04:47:51 PM PDT 24
Finished Jul 22 04:48:21 PM PDT 24
Peak memory 201060 kb
Host smart-d6717dee-6d70-4333-857a-18231f4b9924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253870805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.3253870805
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3569288482
Short name T516
Test name
Test status
Simulation time 4515556220 ps
CPU time 1.19 seconds
Started Jul 22 04:47:49 PM PDT 24
Finished Jul 22 04:47:50 PM PDT 24
Peak memory 200892 kb
Host smart-d3695834-060f-4779-a371-6e16be459655
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569288482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.3569288482
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.3059984938
Short name T324
Test name
Test status
Simulation time 2012585190 ps
CPU time 5.47 seconds
Started Jul 22 04:47:58 PM PDT 24
Finished Jul 22 04:48:05 PM PDT 24
Peak memory 200944 kb
Host smart-28432ea2-93ad-4992-a316-a70fe8afd2c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059984938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.3059984938
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2838969124
Short name T107
Test name
Test status
Simulation time 3106937505 ps
CPU time 2.75 seconds
Started Jul 22 04:47:58 PM PDT 24
Finished Jul 22 04:48:02 PM PDT 24
Peak memory 201004 kb
Host smart-ebd5e38b-c113-4244-981b-fb4da4d2639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838969124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.2838969124
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.52312358
Short name T740
Test name
Test status
Simulation time 90305602512 ps
CPU time 53.83 seconds
Started Jul 22 04:47:58 PM PDT 24
Finished Jul 22 04:48:53 PM PDT 24
Peak memory 201104 kb
Host smart-0f318db4-d274-42d9-b790-1c6585ef30cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52312358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_combo_detect.52312358
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1738862127
Short name T255
Test name
Test status
Simulation time 2178415074 ps
CPU time 6.04 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:47:57 PM PDT 24
Peak memory 200956 kb
Host smart-1ec56df1-d199-4c07-ac9e-2ddd2487fff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738862127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1738862127
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2454229539
Short name T684
Test name
Test status
Simulation time 2557475691 ps
CPU time 1.5 seconds
Started Jul 22 04:47:54 PM PDT 24
Finished Jul 22 04:47:56 PM PDT 24
Peak memory 200948 kb
Host smart-bc8c3b48-693c-4ffb-895a-113480ff3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454229539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2454229539
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3088023290
Short name T254
Test name
Test status
Simulation time 40552554949 ps
CPU time 28.22 seconds
Started Jul 22 04:47:58 PM PDT 24
Finished Jul 22 04:48:27 PM PDT 24
Peak memory 201304 kb
Host smart-936a8b93-18e3-45d0-b977-ace64c36819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088023290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.3088023290
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2340235315
Short name T277
Test name
Test status
Simulation time 4966770164 ps
CPU time 6.86 seconds
Started Jul 22 04:47:59 PM PDT 24
Finished Jul 22 04:48:06 PM PDT 24
Peak memory 200988 kb
Host smart-f74ce920-1cfc-4c06-865d-0ced07189788
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340235315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.2340235315
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.904843897
Short name T630
Test name
Test status
Simulation time 2618951075 ps
CPU time 3.59 seconds
Started Jul 22 04:47:49 PM PDT 24
Finished Jul 22 04:47:53 PM PDT 24
Peak memory 200952 kb
Host smart-b79a2ab0-ccab-41df-9985-e1dd5ea7b613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904843897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.904843897
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3512722469
Short name T311
Test name
Test status
Simulation time 2454350986 ps
CPU time 4.19 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:47:57 PM PDT 24
Peak memory 200952 kb
Host smart-6223d71d-6725-4c8a-bb1b-686984a4eed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512722469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3512722469
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3053208983
Short name T659
Test name
Test status
Simulation time 2218339256 ps
CPU time 1.95 seconds
Started Jul 22 04:47:49 PM PDT 24
Finished Jul 22 04:47:52 PM PDT 24
Peak memory 200884 kb
Host smart-1ca7011e-6e2d-4e9f-b1a0-508a6452cd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053208983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.3053208983
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3424866815
Short name T744
Test name
Test status
Simulation time 2509918730 ps
CPU time 7.06 seconds
Started Jul 22 04:47:51 PM PDT 24
Finished Jul 22 04:47:59 PM PDT 24
Peak memory 200940 kb
Host smart-7cdc95d8-f6d0-4281-9f12-caa2e8ef9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424866815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.3424866815
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2125864354
Short name T280
Test name
Test status
Simulation time 42252441701 ps
CPU time 16.06 seconds
Started Jul 22 04:48:08 PM PDT 24
Finished Jul 22 04:48:24 PM PDT 24
Peak memory 220584 kb
Host smart-ca8794c0-134f-4d1e-b519-c922d26355b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125864354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2125864354
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2024902306
Short name T229
Test name
Test status
Simulation time 2110871635 ps
CPU time 6.48 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:47:57 PM PDT 24
Peak memory 200932 kb
Host smart-c7e62772-225a-4793-9c17-014ed598bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024902306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2024902306
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.2975685185
Short name T652
Test name
Test status
Simulation time 12148567442 ps
CPU time 7.91 seconds
Started Jul 22 04:47:58 PM PDT 24
Finished Jul 22 04:48:06 PM PDT 24
Peak memory 200908 kb
Host smart-c9919750-6550-4cdb-bd13-eddf4bc7ddc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975685185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.2975685185
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3772360811
Short name T217
Test name
Test status
Simulation time 29247293715 ps
CPU time 69.29 seconds
Started Jul 22 04:47:59 PM PDT 24
Finished Jul 22 04:49:09 PM PDT 24
Peak memory 217756 kb
Host smart-9ea8f2e6-e2e4-4990-9f9d-a4494b9bf6ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772360811 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.3772360811
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1751181636
Short name T127
Test name
Test status
Simulation time 3012176978 ps
CPU time 6.67 seconds
Started Jul 22 04:47:59 PM PDT 24
Finished Jul 22 04:48:07 PM PDT 24
Peak memory 200968 kb
Host smart-2d34c286-26d5-43a2-be4a-5713f1770c0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751181636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.1751181636
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.3523611155
Short name T563
Test name
Test status
Simulation time 2021676290 ps
CPU time 3.28 seconds
Started Jul 22 04:48:50 PM PDT 24
Finished Jul 22 04:48:54 PM PDT 24
Peak memory 200920 kb
Host smart-3ca5cbc1-c869-44b1-a7be-a1e57aec0748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523611155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.3523611155
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1862489037
Short name T640
Test name
Test status
Simulation time 3313991553 ps
CPU time 2.72 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:52 PM PDT 24
Peak memory 201068 kb
Host smart-00055b44-c983-431e-a8e2-3b7e97d67668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862489037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.1
862489037
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2052593921
Short name T162
Test name
Test status
Simulation time 3493094142 ps
CPU time 1.51 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:06 PM PDT 24
Peak memory 200940 kb
Host smart-40a3d87c-6e91-42fe-a4c8-ef7be76cac87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052593921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.2052593921
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.3215752011
Short name T694
Test name
Test status
Simulation time 2966784753 ps
CPU time 2.54 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:51 PM PDT 24
Peak memory 200976 kb
Host smart-7b7c3b79-69bd-47f8-b1cb-deaa0d548cc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215752011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.3215752011
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2816034456
Short name T742
Test name
Test status
Simulation time 2624707921 ps
CPU time 2.55 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:52 PM PDT 24
Peak memory 200952 kb
Host smart-cb5abf20-e6a6-40cf-b6ea-951c3bfd5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816034456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2816034456
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2853858709
Short name T510
Test name
Test status
Simulation time 2455902851 ps
CPU time 4.33 seconds
Started Jul 22 04:48:46 PM PDT 24
Finished Jul 22 04:48:51 PM PDT 24
Peak memory 200940 kb
Host smart-7b419b73-ab4f-4475-89c4-08b81c2536ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853858709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.2853858709
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3107210322
Short name T775
Test name
Test status
Simulation time 2184741715 ps
CPU time 2.2 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:51 PM PDT 24
Peak memory 200916 kb
Host smart-20f643a9-6c08-4046-8104-26c992b26a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107210322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3107210322
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1081972751
Short name T314
Test name
Test status
Simulation time 2558626554 ps
CPU time 1.58 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:50 PM PDT 24
Peak memory 200936 kb
Host smart-28453c5b-7fea-45cc-886c-ca71818ab35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081972751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1081972751
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.3290204255
Short name T202
Test name
Test status
Simulation time 2118794748 ps
CPU time 3.25 seconds
Started Jul 22 04:50:09 PM PDT 24
Finished Jul 22 04:50:13 PM PDT 24
Peak memory 200864 kb
Host smart-21f587f1-591f-4f3a-ae93-54840fa13bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290204255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.3290204255
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.3521656444
Short name T734
Test name
Test status
Simulation time 11613140167 ps
CPU time 8.05 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:57 PM PDT 24
Peak memory 200944 kb
Host smart-ff34719e-6bb0-4a5a-9471-342f76c732b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521656444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.3521656444
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1763673474
Short name T292
Test name
Test status
Simulation time 48021754680 ps
CPU time 115.26 seconds
Started Jul 22 04:48:49 PM PDT 24
Finished Jul 22 04:50:45 PM PDT 24
Peak memory 214060 kb
Host smart-479d7f84-d501-4f93-b639-0635d11578ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763673474 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1763673474
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3798467716
Short name T783
Test name
Test status
Simulation time 15433950614 ps
CPU time 3.7 seconds
Started Jul 22 04:48:51 PM PDT 24
Finished Jul 22 04:48:55 PM PDT 24
Peak memory 200916 kb
Host smart-32a70170-9522-4289-8cd3-c4d894b3e31c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798467716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.3798467716
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1660291937
Short name T598
Test name
Test status
Simulation time 2028978416 ps
CPU time 1.93 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:38 PM PDT 24
Peak memory 200952 kb
Host smart-88866328-4081-4bcb-8794-1a6d5968a6ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660291937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1660291937
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2469284127
Short name T421
Test name
Test status
Simulation time 3426035892 ps
CPU time 2.18 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:51 PM PDT 24
Peak memory 201060 kb
Host smart-4d4fd6db-6be8-4740-bf09-837c67de0af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469284127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
469284127
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3340813323
Short name T491
Test name
Test status
Simulation time 3288831436 ps
CPU time 9.5 seconds
Started Jul 22 04:48:51 PM PDT 24
Finished Jul 22 04:49:01 PM PDT 24
Peak memory 200924 kb
Host smart-ece72178-8ea5-42ba-a091-9286dec0a6dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340813323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.3340813323
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3570217827
Short name T448
Test name
Test status
Simulation time 2628601639 ps
CPU time 2.56 seconds
Started Jul 22 04:48:49 PM PDT 24
Finished Jul 22 04:48:52 PM PDT 24
Peak memory 200968 kb
Host smart-26cc4a31-61db-4e53-b793-20e47dcea284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570217827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.3570217827
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3679431589
Short name T737
Test name
Test status
Simulation time 2469754574 ps
CPU time 7.08 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:56 PM PDT 24
Peak memory 201004 kb
Host smart-ef71e47f-e85f-40b8-90d5-efdb9bdb5799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679431589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3679431589
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.3051583097
Short name T612
Test name
Test status
Simulation time 2248474102 ps
CPU time 2.09 seconds
Started Jul 22 04:48:51 PM PDT 24
Finished Jul 22 04:48:54 PM PDT 24
Peak memory 200936 kb
Host smart-e7c92566-3b2a-49c6-99eb-b8c1d2d78aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051583097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.3051583097
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.1289180482
Short name T501
Test name
Test status
Simulation time 2113190241 ps
CPU time 4.14 seconds
Started Jul 22 04:48:49 PM PDT 24
Finished Jul 22 04:48:54 PM PDT 24
Peak memory 200948 kb
Host smart-4db567d5-b86f-4729-a5aa-2a0ca3006c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289180482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.1289180482
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.4036666164
Short name T241
Test name
Test status
Simulation time 11700762511 ps
CPU time 30.33 seconds
Started Jul 22 04:48:52 PM PDT 24
Finished Jul 22 04:49:23 PM PDT 24
Peak memory 200928 kb
Host smart-7914eea8-b8b1-417f-aa45-41b7ff7107a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036666164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.4036666164
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2372258185
Short name T132
Test name
Test status
Simulation time 328538300151 ps
CPU time 103.81 seconds
Started Jul 22 04:48:50 PM PDT 24
Finished Jul 22 04:50:35 PM PDT 24
Peak memory 209640 kb
Host smart-4cb6e462-14b0-4caf-83af-a4429a927ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372258185 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2372258185
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2353319423
Short name T643
Test name
Test status
Simulation time 3686807708 ps
CPU time 1.72 seconds
Started Jul 22 04:51:28 PM PDT 24
Finished Jul 22 04:51:31 PM PDT 24
Peak memory 200996 kb
Host smart-a01ffd38-9bb5-4c29-b2a7-7df9f543659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353319423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.2
353319423
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.3434966143
Short name T194
Test name
Test status
Simulation time 55055428746 ps
CPU time 35.94 seconds
Started Jul 22 04:48:56 PM PDT 24
Finished Jul 22 04:49:33 PM PDT 24
Peak memory 201108 kb
Host smart-195207e6-8665-4ac6-922a-38752461908d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434966143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.3434966143
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2702291374
Short name T525
Test name
Test status
Simulation time 74764712858 ps
CPU time 164.27 seconds
Started Jul 22 04:48:57 PM PDT 24
Finished Jul 22 04:51:42 PM PDT 24
Peak memory 201272 kb
Host smart-8add8a11-4a40-40ec-b074-b34f26dabc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702291374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.2702291374
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3877735737
Short name T113
Test name
Test status
Simulation time 3246653435 ps
CPU time 8.92 seconds
Started Jul 22 04:48:57 PM PDT 24
Finished Jul 22 04:49:06 PM PDT 24
Peak memory 200904 kb
Host smart-a358c422-e5b2-45da-ac32-144fa0534cea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877735737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.3877735737
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2331566635
Short name T660
Test name
Test status
Simulation time 2476261494 ps
CPU time 7.16 seconds
Started Jul 22 04:48:56 PM PDT 24
Finished Jul 22 04:49:03 PM PDT 24
Peak memory 200928 kb
Host smart-6c320daa-4c3c-4e9c-a2ab-09e129ca668f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331566635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.2331566635
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.1399560585
Short name T576
Test name
Test status
Simulation time 2609270899 ps
CPU time 7.09 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:44 PM PDT 24
Peak memory 200948 kb
Host smart-23b9f48b-2e81-424f-80a9-1e88712c9128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399560585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.1399560585
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1109185730
Short name T705
Test name
Test status
Simulation time 2472932073 ps
CPU time 2.07 seconds
Started Jul 22 04:49:11 PM PDT 24
Finished Jul 22 04:49:14 PM PDT 24
Peak memory 200968 kb
Host smart-f48b2cd1-523c-4034-a2d8-b1bb91e30716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109185730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.1109185730
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.2396289961
Short name T685
Test name
Test status
Simulation time 2231432890 ps
CPU time 2.05 seconds
Started Jul 22 04:50:44 PM PDT 24
Finished Jul 22 04:50:47 PM PDT 24
Peak memory 200884 kb
Host smart-2d995877-f9df-40d3-a4e8-1860b7cabe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396289961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.2396289961
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2524338341
Short name T393
Test name
Test status
Simulation time 2526689761 ps
CPU time 2.35 seconds
Started Jul 22 04:48:58 PM PDT 24
Finished Jul 22 04:49:01 PM PDT 24
Peak memory 200964 kb
Host smart-7fc69277-c3c0-4421-b678-c3dd145db77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524338341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.2524338341
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.668082548
Short name T626
Test name
Test status
Simulation time 2129176720 ps
CPU time 1.91 seconds
Started Jul 22 04:49:17 PM PDT 24
Finished Jul 22 04:49:19 PM PDT 24
Peak memory 200860 kb
Host smart-2e0d0ce4-1964-4c03-8120-0ca88369450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668082548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.668082548
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.281291823
Short name T751
Test name
Test status
Simulation time 7073074586 ps
CPU time 10.7 seconds
Started Jul 22 04:48:57 PM PDT 24
Finished Jul 22 04:49:08 PM PDT 24
Peak memory 200972 kb
Host smart-ea86d4b4-62c2-4304-a771-efed0c84f30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281291823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.281291823
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4001090448
Short name T200
Test name
Test status
Simulation time 4938328951 ps
CPU time 1.99 seconds
Started Jul 22 04:48:55 PM PDT 24
Finished Jul 22 04:48:58 PM PDT 24
Peak memory 200940 kb
Host smart-19d26ee1-40c6-4d0c-a8a9-8e89b33700ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001090448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.4001090448
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.4194874285
Short name T682
Test name
Test status
Simulation time 2018055695 ps
CPU time 3.92 seconds
Started Jul 22 04:49:00 PM PDT 24
Finished Jul 22 04:49:04 PM PDT 24
Peak memory 200952 kb
Host smart-f04b04de-a840-4cbd-879c-78d26bad2084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194874285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.4194874285
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1671944531
Short name T724
Test name
Test status
Simulation time 3513064526 ps
CPU time 5.09 seconds
Started Jul 22 04:48:55 PM PDT 24
Finished Jul 22 04:49:01 PM PDT 24
Peak memory 201020 kb
Host smart-8f125186-cec9-4488-b94a-600633f1ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671944531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1
671944531
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3622357446
Short name T106
Test name
Test status
Simulation time 191878516117 ps
CPU time 494.81 seconds
Started Jul 22 04:48:57 PM PDT 24
Finished Jul 22 04:57:12 PM PDT 24
Peak memory 201160 kb
Host smart-908827c8-0610-4a6a-ad23-72a54e61c80d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622357446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.3622357446
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1276838534
Short name T304
Test name
Test status
Simulation time 889656865862 ps
CPU time 594.28 seconds
Started Jul 22 04:50:10 PM PDT 24
Finished Jul 22 05:00:05 PM PDT 24
Peak memory 200916 kb
Host smart-563aac19-1890-4e4f-b852-1648c3542923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276838534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1276838534
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.548911673
Short name T11
Test name
Test status
Simulation time 3409619217 ps
CPU time 2.26 seconds
Started Jul 22 04:48:58 PM PDT 24
Finished Jul 22 04:49:01 PM PDT 24
Peak memory 200952 kb
Host smart-9c2eb7f7-2773-410f-b998-8c5f68ad46ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548911673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctr
l_edge_detect.548911673
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2999229105
Short name T568
Test name
Test status
Simulation time 2613578363 ps
CPU time 6.71 seconds
Started Jul 22 04:49:28 PM PDT 24
Finished Jul 22 04:49:35 PM PDT 24
Peak memory 200956 kb
Host smart-923eea78-bb7b-4b8b-9b21-70c9131fad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999229105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.2999229105
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.2027530705
Short name T594
Test name
Test status
Simulation time 2508178587 ps
CPU time 2.32 seconds
Started Jul 22 04:49:18 PM PDT 24
Finished Jul 22 04:49:21 PM PDT 24
Peak memory 201024 kb
Host smart-38f5c33b-86a5-43ac-8f6f-4093a5586f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027530705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.2027530705
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.24467824
Short name T468
Test name
Test status
Simulation time 2267669996 ps
CPU time 2 seconds
Started Jul 22 04:51:28 PM PDT 24
Finished Jul 22 04:51:31 PM PDT 24
Peak memory 200928 kb
Host smart-016890e3-6e20-4102-b860-25b6aec71553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24467824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.24467824
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1421001457
Short name T560
Test name
Test status
Simulation time 2537712600 ps
CPU time 1.91 seconds
Started Jul 22 04:51:28 PM PDT 24
Finished Jul 22 04:51:30 PM PDT 24
Peak memory 200932 kb
Host smart-80803a4a-994c-498e-98ff-79fc417072b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421001457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1421001457
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.3675666946
Short name T98
Test name
Test status
Simulation time 2110576038 ps
CPU time 5.53 seconds
Started Jul 22 04:48:57 PM PDT 24
Finished Jul 22 04:49:02 PM PDT 24
Peak memory 200872 kb
Host smart-dff034bc-25c8-43d5-8399-0d0fb975f0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675666946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3675666946
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.526255714
Short name T153
Test name
Test status
Simulation time 1095317560300 ps
CPU time 365.72 seconds
Started Jul 22 04:49:28 PM PDT 24
Finished Jul 22 04:55:34 PM PDT 24
Peak memory 212284 kb
Host smart-714361a9-056e-44c1-aebd-a23e2433e133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526255714 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.526255714
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.388815647
Short name T494
Test name
Test status
Simulation time 3396277868 ps
CPU time 6.64 seconds
Started Jul 22 04:48:59 PM PDT 24
Finished Jul 22 04:49:06 PM PDT 24
Peak memory 200924 kb
Host smart-8e09d2e5-56c7-4b2b-b45d-952127b8b130
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388815647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_ultra_low_pwr.388815647
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.385594351
Short name T644
Test name
Test status
Simulation time 2039719334 ps
CPU time 1.97 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:07 PM PDT 24
Peak memory 201008 kb
Host smart-7bd0335a-d6ca-4cea-b598-17e76c0a2bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385594351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_tes
t.385594351
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1163078651
Short name T480
Test name
Test status
Simulation time 3672203876 ps
CPU time 2.53 seconds
Started Jul 22 04:51:28 PM PDT 24
Finished Jul 22 04:51:31 PM PDT 24
Peak memory 200996 kb
Host smart-715e3e1f-1a44-4b61-9ebb-18a8d7f25a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163078651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
163078651
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.289973767
Short name T91
Test name
Test status
Simulation time 62314115161 ps
CPU time 20.02 seconds
Started Jul 22 04:49:03 PM PDT 24
Finished Jul 22 04:49:23 PM PDT 24
Peak memory 201168 kb
Host smart-94dc8255-495e-462d-be89-5795cce63cc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289973767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_combo_detect.289973767
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1892055476
Short name T437
Test name
Test status
Simulation time 3064356155 ps
CPU time 8.41 seconds
Started Jul 22 04:50:44 PM PDT 24
Finished Jul 22 04:50:54 PM PDT 24
Peak memory 200240 kb
Host smart-afe24441-203d-4d85-b944-c04dfa541ad4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892055476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.1892055476
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.627068725
Short name T156
Test name
Test status
Simulation time 3478508463 ps
CPU time 2.78 seconds
Started Jul 22 04:49:03 PM PDT 24
Finished Jul 22 04:49:06 PM PDT 24
Peak memory 200856 kb
Host smart-c5de4960-96d8-4a2f-ad4d-85f6083ebc62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627068725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.627068725
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1898844062
Short name T466
Test name
Test status
Simulation time 2612692908 ps
CPU time 5.98 seconds
Started Jul 22 04:49:03 PM PDT 24
Finished Jul 22 04:49:10 PM PDT 24
Peak memory 200944 kb
Host smart-3582fbd6-4d0d-40eb-b959-ffe03847d718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898844062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1898844062
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.2895101275
Short name T65
Test name
Test status
Simulation time 2468588473 ps
CPU time 3.96 seconds
Started Jul 22 04:49:06 PM PDT 24
Finished Jul 22 04:49:11 PM PDT 24
Peak memory 200956 kb
Host smart-f1e98230-2418-472c-b137-41e6c4bc1589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895101275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.2895101275
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3200511018
Short name T637
Test name
Test status
Simulation time 2102804431 ps
CPU time 4.64 seconds
Started Jul 22 04:49:05 PM PDT 24
Finished Jul 22 04:49:10 PM PDT 24
Peak memory 200844 kb
Host smart-69098db7-d9f8-4810-9105-8058a9827932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200511018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3200511018
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2232213009
Short name T529
Test name
Test status
Simulation time 2510374132 ps
CPU time 7.41 seconds
Started Jul 22 04:50:20 PM PDT 24
Finished Jul 22 04:50:28 PM PDT 24
Peak memory 200940 kb
Host smart-663d34ea-9992-43dc-9cf6-7ada5daa172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232213009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.2232213009
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.264629385
Short name T573
Test name
Test status
Simulation time 2111994605 ps
CPU time 6.01 seconds
Started Jul 22 04:49:03 PM PDT 24
Finished Jul 22 04:49:09 PM PDT 24
Peak memory 200860 kb
Host smart-c4711832-1cfe-494f-a027-20e52ec70373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264629385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.264629385
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.1554712856
Short name T55
Test name
Test status
Simulation time 14334979328 ps
CPU time 9.62 seconds
Started Jul 22 04:51:28 PM PDT 24
Finished Jul 22 04:51:39 PM PDT 24
Peak memory 200968 kb
Host smart-633fdf61-74c5-4d81-9f09-82a2c5f19487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554712856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.1554712856
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3203725020
Short name T61
Test name
Test status
Simulation time 5894426334 ps
CPU time 7.56 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:13 PM PDT 24
Peak memory 201008 kb
Host smart-d44115a3-fbcb-47a6-aa5c-7e81a8c07fc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203725020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.3203725020
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.1746169595
Short name T205
Test name
Test status
Simulation time 2010732731 ps
CPU time 5.57 seconds
Started Jul 22 04:49:12 PM PDT 24
Finished Jul 22 04:49:18 PM PDT 24
Peak memory 200952 kb
Host smart-02241dde-385c-4f31-8f97-f39dda1182fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746169595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.1746169595
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2053510717
Short name T108
Test name
Test status
Simulation time 3256845745 ps
CPU time 2.67 seconds
Started Jul 22 04:49:02 PM PDT 24
Finished Jul 22 04:49:05 PM PDT 24
Peak memory 201004 kb
Host smart-cee67a84-7e4b-4e59-911a-c397a67821d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053510717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
053510717
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2688927396
Short name T196
Test name
Test status
Simulation time 37040500035 ps
CPU time 10.53 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:50:30 PM PDT 24
Peak memory 201232 kb
Host smart-66519a5a-a0b8-450c-85e9-c080b0800f52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688927396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2688927396
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2117852691
Short name T533
Test name
Test status
Simulation time 25079253298 ps
CPU time 67.69 seconds
Started Jul 22 04:50:15 PM PDT 24
Finished Jul 22 04:51:23 PM PDT 24
Peak memory 201340 kb
Host smart-5b1b3d87-5645-4189-b96d-6d29e6461a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117852691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.2117852691
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2610765631
Short name T405
Test name
Test status
Simulation time 2754145426 ps
CPU time 1.21 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:06 PM PDT 24
Peak memory 200904 kb
Host smart-a6e5a76e-7dd8-4d77-b505-352bac231375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610765631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.2610765631
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.1813541711
Short name T780
Test name
Test status
Simulation time 635401387038 ps
CPU time 26 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:31 PM PDT 24
Peak memory 201012 kb
Host smart-7b7bbe6d-ab77-471d-bfc4-b02a20e7d841
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813541711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.1813541711
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.120004207
Short name T548
Test name
Test status
Simulation time 2637333191 ps
CPU time 2.23 seconds
Started Jul 22 04:49:05 PM PDT 24
Finished Jul 22 04:49:08 PM PDT 24
Peak memory 200988 kb
Host smart-3ab58c45-33a8-412d-b081-faf110dbb5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120004207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.120004207
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1699103394
Short name T776
Test name
Test status
Simulation time 2462432676 ps
CPU time 6.44 seconds
Started Jul 22 04:49:05 PM PDT 24
Finished Jul 22 04:49:12 PM PDT 24
Peak memory 201024 kb
Host smart-fd6fbf1e-59f1-446b-8c9d-b6461c4fe53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699103394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1699103394
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3161568832
Short name T123
Test name
Test status
Simulation time 2217505837 ps
CPU time 1.99 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:06 PM PDT 24
Peak memory 200956 kb
Host smart-e4fe869d-fefa-4d29-9178-f9e8d2d87473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161568832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3161568832
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1255769105
Short name T498
Test name
Test status
Simulation time 2529440096 ps
CPU time 2.45 seconds
Started Jul 22 04:49:46 PM PDT 24
Finished Jul 22 04:49:49 PM PDT 24
Peak memory 200912 kb
Host smart-3a5d266f-ca33-4449-8aa0-7203c9f6366b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255769105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.1255769105
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.4051542234
Short name T730
Test name
Test status
Simulation time 2112087211 ps
CPU time 5.6 seconds
Started Jul 22 04:49:05 PM PDT 24
Finished Jul 22 04:49:11 PM PDT 24
Peak memory 200876 kb
Host smart-618c1073-d912-4efa-a033-5b45e117bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051542234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.4051542234
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.4099184964
Short name T766
Test name
Test status
Simulation time 9105747583 ps
CPU time 5.37 seconds
Started Jul 22 04:49:13 PM PDT 24
Finished Jul 22 04:49:19 PM PDT 24
Peak memory 201000 kb
Host smart-fa874b7f-e12a-4dfc-b4c9-4c7001fc2e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099184964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.4099184964
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.711742704
Short name T128
Test name
Test status
Simulation time 31528735965 ps
CPU time 37.92 seconds
Started Jul 22 04:49:13 PM PDT 24
Finished Jul 22 04:49:52 PM PDT 24
Peak memory 209552 kb
Host smart-a03385a1-ff2c-41a8-9c3b-513714ca45fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711742704 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.711742704
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.644292246
Short name T208
Test name
Test status
Simulation time 4963204700 ps
CPU time 6.59 seconds
Started Jul 22 04:51:28 PM PDT 24
Finished Jul 22 04:51:35 PM PDT 24
Peak memory 200944 kb
Host smart-ff57ee3c-dd6b-4937-9786-53a4ff95e675
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644292246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ultra_low_pwr.644292246
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.3731269
Short name T711
Test name
Test status
Simulation time 2021875866 ps
CPU time 1.99 seconds
Started Jul 22 04:49:20 PM PDT 24
Finished Jul 22 04:49:22 PM PDT 24
Peak memory 200856 kb
Host smart-9cf477d7-2eed-4267-8331-5a1de94dcb3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.3731269
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1445740295
Short name T543
Test name
Test status
Simulation time 303557563213 ps
CPU time 738.92 seconds
Started Jul 22 04:49:14 PM PDT 24
Finished Jul 22 05:01:34 PM PDT 24
Peak memory 200992 kb
Host smart-1debac43-ed58-4c84-9aa2-7769aa69982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445740295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1
445740295
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1398505474
Short name T687
Test name
Test status
Simulation time 101223379043 ps
CPU time 65.43 seconds
Started Jul 22 04:49:21 PM PDT 24
Finished Jul 22 04:50:26 PM PDT 24
Peak memory 201092 kb
Host smart-ae5edb2c-2fb4-4a16-aa19-6b2d7c1cbb7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398505474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1398505474
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2706126938
Short name T446
Test name
Test status
Simulation time 3987407577 ps
CPU time 5.54 seconds
Started Jul 22 04:49:12 PM PDT 24
Finished Jul 22 04:49:18 PM PDT 24
Peak memory 200924 kb
Host smart-73f997ae-6938-4dff-b869-38a72099a36a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706126938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.2706126938
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.1836073422
Short name T147
Test name
Test status
Simulation time 3417852468 ps
CPU time 2.35 seconds
Started Jul 22 04:49:15 PM PDT 24
Finished Jul 22 04:49:18 PM PDT 24
Peak memory 200960 kb
Host smart-854c4cba-6d08-4f7b-a693-5ceaafa2e659
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836073422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.1836073422
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1437180594
Short name T650
Test name
Test status
Simulation time 2610093561 ps
CPU time 7.18 seconds
Started Jul 22 04:49:15 PM PDT 24
Finished Jul 22 04:49:23 PM PDT 24
Peak memory 200948 kb
Host smart-9f5d4370-2baf-476d-b4ef-aa3e270ddb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437180594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.1437180594
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.4189160150
Short name T764
Test name
Test status
Simulation time 2593518451 ps
CPU time 1.09 seconds
Started Jul 22 04:49:13 PM PDT 24
Finished Jul 22 04:49:15 PM PDT 24
Peak memory 201024 kb
Host smart-64ebcad3-d47b-40b2-b839-1fee93afe71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189160150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.4189160150
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2931028353
Short name T761
Test name
Test status
Simulation time 2284589795 ps
CPU time 1.29 seconds
Started Jul 22 04:49:14 PM PDT 24
Finished Jul 22 04:49:16 PM PDT 24
Peak memory 200972 kb
Host smart-225a8510-e08c-4b7b-9ce9-5c1e1d041023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931028353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.2931028353
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.1571513705
Short name T600
Test name
Test status
Simulation time 2538069857 ps
CPU time 1.65 seconds
Started Jul 22 04:49:14 PM PDT 24
Finished Jul 22 04:49:17 PM PDT 24
Peak memory 201024 kb
Host smart-8dab9c51-8727-4f50-9d62-a58ad2094e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571513705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.1571513705
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2951568540
Short name T695
Test name
Test status
Simulation time 2112619057 ps
CPU time 5.74 seconds
Started Jul 22 04:49:20 PM PDT 24
Finished Jul 22 04:49:26 PM PDT 24
Peak memory 200744 kb
Host smart-bc92d716-28f3-46e2-87ba-130c53ae6a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951568540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2951568540
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.1763873938
Short name T64
Test name
Test status
Simulation time 13145641987 ps
CPU time 34.79 seconds
Started Jul 22 04:49:13 PM PDT 24
Finished Jul 22 04:49:48 PM PDT 24
Peak memory 200980 kb
Host smart-bc213510-5a5b-4888-9ad2-e2916eb0e7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763873938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.1763873938
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1520138904
Short name T320
Test name
Test status
Simulation time 119374598666 ps
CPU time 74.34 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:50:40 PM PDT 24
Peak memory 212164 kb
Host smart-b8cdb288-19c3-41de-898a-59c1cb00e97e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520138904 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1520138904
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.4142543906
Short name T223
Test name
Test status
Simulation time 6718447199 ps
CPU time 2.37 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:39 PM PDT 24
Peak memory 200936 kb
Host smart-88bf3acf-76e4-4ada-8873-82f3eba38cc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142543906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.4142543906
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.4248692264
Short name T112
Test name
Test status
Simulation time 2023611452 ps
CPU time 3.25 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:50:50 PM PDT 24
Peak memory 200956 kb
Host smart-f1d41715-1455-475c-9f1e-f000cc290330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248692264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.4248692264
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2567908163
Short name T578
Test name
Test status
Simulation time 3030467180 ps
CPU time 4.23 seconds
Started Jul 22 04:50:14 PM PDT 24
Finished Jul 22 04:50:18 PM PDT 24
Peak memory 201048 kb
Host smart-e36d7b0b-dfad-4af5-94f5-abc1b3856e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567908163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.2
567908163
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.4094660872
Short name T347
Test name
Test status
Simulation time 120481408071 ps
CPU time 81.65 seconds
Started Jul 22 04:49:13 PM PDT 24
Finished Jul 22 04:50:35 PM PDT 24
Peak memory 201152 kb
Host smart-91e0da3c-1412-4c28-a551-9a15100a0efa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094660872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.4094660872
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1124577935
Short name T671
Test name
Test status
Simulation time 25118639679 ps
CPU time 9.49 seconds
Started Jul 22 04:49:15 PM PDT 24
Finished Jul 22 04:49:25 PM PDT 24
Peak memory 201312 kb
Host smart-cd2d706b-655a-4a33-9544-b11adb5aa54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124577935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.1124577935
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.963659369
Short name T402
Test name
Test status
Simulation time 2968788703 ps
CPU time 8.67 seconds
Started Jul 22 04:49:12 PM PDT 24
Finished Jul 22 04:49:21 PM PDT 24
Peak memory 200916 kb
Host smart-53b45c7f-1507-4139-a6d3-bf09cc5547aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963659369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ec_pwr_on_rst.963659369
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.608001664
Short name T70
Test name
Test status
Simulation time 3402710344 ps
CPU time 9.29 seconds
Started Jul 22 04:49:12 PM PDT 24
Finished Jul 22 04:49:22 PM PDT 24
Peak memory 201012 kb
Host smart-764f2812-549e-496d-9e2b-ce0c8cc5c120
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608001664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctr
l_edge_detect.608001664
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3791755249
Short name T404
Test name
Test status
Simulation time 2612086486 ps
CPU time 7.19 seconds
Started Jul 22 04:49:20 PM PDT 24
Finished Jul 22 04:49:27 PM PDT 24
Peak memory 200824 kb
Host smart-9fc09fdc-e71d-41e0-83c5-4b5822a0bcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791755249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.3791755249
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3033820504
Short name T416
Test name
Test status
Simulation time 2498243469 ps
CPU time 2.44 seconds
Started Jul 22 04:49:12 PM PDT 24
Finished Jul 22 04:49:15 PM PDT 24
Peak memory 200936 kb
Host smart-22d0a66c-12b3-4421-b152-4d308b5c7ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033820504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3033820504
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.273966178
Short name T622
Test name
Test status
Simulation time 2174781282 ps
CPU time 2.21 seconds
Started Jul 22 04:49:11 PM PDT 24
Finished Jul 22 04:49:14 PM PDT 24
Peak memory 200952 kb
Host smart-65bd83eb-15ac-465a-a599-aa02cb9794a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273966178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.273966178
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.844442811
Short name T391
Test name
Test status
Simulation time 2513797927 ps
CPU time 4.21 seconds
Started Jul 22 04:49:12 PM PDT 24
Finished Jul 22 04:49:17 PM PDT 24
Peak memory 201004 kb
Host smart-de13c2f2-7ff6-4e85-8b82-2f60c1c3a7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844442811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.844442811
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.2998036428
Short name T187
Test name
Test status
Simulation time 2135210361 ps
CPU time 1.27 seconds
Started Jul 22 04:49:13 PM PDT 24
Finished Jul 22 04:49:14 PM PDT 24
Peak memory 200840 kb
Host smart-c038b8a3-6032-4504-a7e4-20ac760d52f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998036428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.2998036428
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.2684133948
Short name T735
Test name
Test status
Simulation time 9232997467 ps
CPU time 9.84 seconds
Started Jul 22 04:49:31 PM PDT 24
Finished Jul 22 04:49:41 PM PDT 24
Peak memory 200968 kb
Host smart-042e84b5-c1b1-4339-9989-ef9383e27a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684133948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.2684133948
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2255487949
Short name T124
Test name
Test status
Simulation time 4098915432 ps
CPU time 7.3 seconds
Started Jul 22 04:49:50 PM PDT 24
Finished Jul 22 04:49:58 PM PDT 24
Peak memory 201036 kb
Host smart-df1d10d6-328a-445f-9b24-2589742863a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255487949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.2255487949
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3073766847
Short name T57
Test name
Test status
Simulation time 2022430517 ps
CPU time 3.24 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:50:48 PM PDT 24
Peak memory 200856 kb
Host smart-4a4e2025-6492-4f03-b144-c8cec4d4ba6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073766847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3073766847
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3564797591
Short name T53
Test name
Test status
Simulation time 3508528206 ps
CPU time 9.63 seconds
Started Jul 22 04:49:25 PM PDT 24
Finished Jul 22 04:49:35 PM PDT 24
Peak memory 201044 kb
Host smart-e0cbc078-975e-415b-8a2d-52b4f33d9424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564797591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.3
564797591
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2805295675
Short name T716
Test name
Test status
Simulation time 3121726232 ps
CPU time 4.57 seconds
Started Jul 22 04:49:23 PM PDT 24
Finished Jul 22 04:49:28 PM PDT 24
Peak memory 200996 kb
Host smart-841c44a5-b7f2-4e0d-98d1-d3c068015b23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805295675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.2805295675
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.1703355638
Short name T178
Test name
Test status
Simulation time 3989998838 ps
CPU time 11.55 seconds
Started Jul 22 04:50:02 PM PDT 24
Finished Jul 22 04:50:14 PM PDT 24
Peak memory 200892 kb
Host smart-049e1ce3-80fc-49fd-9ae9-2f6a33bd18bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703355638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.1703355638
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1339435540
Short name T58
Test name
Test status
Simulation time 2611807355 ps
CPU time 7.18 seconds
Started Jul 22 04:49:27 PM PDT 24
Finished Jul 22 04:49:35 PM PDT 24
Peak memory 201024 kb
Host smart-c89e69b2-614f-4c14-8a98-6d6ce6395bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339435540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1339435540
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2286418019
Short name T757
Test name
Test status
Simulation time 2481975965 ps
CPU time 4.05 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:49:29 PM PDT 24
Peak memory 200876 kb
Host smart-2d221732-9abf-4d9e-8770-70d133d21598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286418019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.2286418019
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.4248051387
Short name T399
Test name
Test status
Simulation time 2058909119 ps
CPU time 2.11 seconds
Started Jul 22 04:49:27 PM PDT 24
Finished Jul 22 04:49:29 PM PDT 24
Peak memory 200900 kb
Host smart-dfb419f7-ef4f-45c5-84ce-51eb2be7e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248051387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.4248051387
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3707923983
Short name T5
Test name
Test status
Simulation time 2650487830 ps
CPU time 1.05 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:49:25 PM PDT 24
Peak memory 201008 kb
Host smart-467b33cb-f9ab-4438-853f-70cff45e8730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707923983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3707923983
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.4105992337
Short name T519
Test name
Test status
Simulation time 2128946157 ps
CPU time 1.97 seconds
Started Jul 22 04:49:25 PM PDT 24
Finished Jul 22 04:49:28 PM PDT 24
Peak memory 200840 kb
Host smart-b431bfb1-5145-4d17-8cfb-b7351a376516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105992337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.4105992337
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.3756921918
Short name T374
Test name
Test status
Simulation time 174834438764 ps
CPU time 475.91 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:57:20 PM PDT 24
Peak memory 201164 kb
Host smart-7cf11932-50e4-4281-8db1-283de8c23c17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756921918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.3756921918
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1776735963
Short name T131
Test name
Test status
Simulation time 5924031769 ps
CPU time 1.82 seconds
Started Jul 22 04:49:25 PM PDT 24
Finished Jul 22 04:49:28 PM PDT 24
Peak memory 200916 kb
Host smart-b587f092-ba07-498c-8f97-14e5fe5b6ae8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776735963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.1776735963
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.3330959756
Short name T120
Test name
Test status
Simulation time 2027005762 ps
CPU time 2.24 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:49:42 PM PDT 24
Peak memory 200960 kb
Host smart-e5282211-5a7a-4844-87d2-46ff63f4b53b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330959756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.3330959756
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2848558764
Short name T752
Test name
Test status
Simulation time 209837731053 ps
CPU time 123.36 seconds
Started Jul 22 04:49:25 PM PDT 24
Finished Jul 22 04:51:29 PM PDT 24
Peak memory 201040 kb
Host smart-3738409b-ca77-4a96-86cf-8bccf965f3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848558764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.2
848558764
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3064132566
Short name T370
Test name
Test status
Simulation time 119789625941 ps
CPU time 212.53 seconds
Started Jul 22 04:49:25 PM PDT 24
Finished Jul 22 04:52:58 PM PDT 24
Peak memory 201116 kb
Host smart-c73a9754-40ba-48a5-8d7a-5f55563ba602
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064132566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3064132566
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.365119436
Short name T601
Test name
Test status
Simulation time 63105585113 ps
CPU time 79.36 seconds
Started Jul 22 04:49:37 PM PDT 24
Finished Jul 22 04:50:57 PM PDT 24
Peak memory 201276 kb
Host smart-cbc30938-cf67-48a7-a667-9b53115b3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365119436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wi
th_pre_cond.365119436
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.681754109
Short name T102
Test name
Test status
Simulation time 2885096431 ps
CPU time 4.36 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:49:29 PM PDT 24
Peak memory 201000 kb
Host smart-1a494f07-0f12-4fef-b180-fc0cdcdda3dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681754109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.681754109
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.4064266609
Short name T77
Test name
Test status
Simulation time 4793473063 ps
CPU time 2.93 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:49:28 PM PDT 24
Peak memory 200916 kb
Host smart-a4cbe198-246c-484c-a06a-1d862b383ba7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064266609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.4064266609
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.968166589
Short name T475
Test name
Test status
Simulation time 2629020385 ps
CPU time 2.32 seconds
Started Jul 22 04:49:40 PM PDT 24
Finished Jul 22 04:49:43 PM PDT 24
Peak memory 201000 kb
Host smart-b82e7cd8-aa72-45b6-9a40-b9f8d01c282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968166589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.968166589
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1465790067
Short name T721
Test name
Test status
Simulation time 2497287340 ps
CPU time 1.38 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:49:26 PM PDT 24
Peak memory 200916 kb
Host smart-cef82eac-23a0-48da-a027-03d309199588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465790067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1465790067
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2141284150
Short name T410
Test name
Test status
Simulation time 2016666087 ps
CPU time 5.9 seconds
Started Jul 22 04:49:25 PM PDT 24
Finished Jul 22 04:49:32 PM PDT 24
Peak memory 200824 kb
Host smart-eba97158-01b4-4a4c-b898-53c67578a5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141284150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.2141284150
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3583394977
Short name T504
Test name
Test status
Simulation time 2510488165 ps
CPU time 7.57 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:49:32 PM PDT 24
Peak memory 200948 kb
Host smart-25315807-4418-40e4-80ff-6f138f86dc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583394977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3583394977
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.1206580658
Short name T786
Test name
Test status
Simulation time 2120134982 ps
CPU time 3.22 seconds
Started Jul 22 04:49:24 PM PDT 24
Finished Jul 22 04:49:28 PM PDT 24
Peak memory 200824 kb
Host smart-43f4cc2b-3183-4dd3-800e-df244758bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206580658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.1206580658
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.256905115
Short name T266
Test name
Test status
Simulation time 105506937954 ps
CPU time 260.29 seconds
Started Jul 22 04:49:38 PM PDT 24
Finished Jul 22 04:53:59 PM PDT 24
Peak memory 201188 kb
Host smart-364de96f-a0ea-4960-9e71-b45669390fa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256905115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_st
ress_all.256905115
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2229129540
Short name T118
Test name
Test status
Simulation time 3139546380369 ps
CPU time 523.93 seconds
Started Jul 22 04:49:25 PM PDT 24
Finished Jul 22 04:58:10 PM PDT 24
Peak memory 200928 kb
Host smart-33b0c5eb-d115-4158-b61d-84b27da2f82b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229129540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.2229129540
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1241517649
Short name T435
Test name
Test status
Simulation time 2012462612 ps
CPU time 5.69 seconds
Started Jul 22 04:48:23 PM PDT 24
Finished Jul 22 04:48:30 PM PDT 24
Peak memory 200952 kb
Host smart-4159beed-562c-4937-b969-2e079e3e096b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241517649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1241517649
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2329064266
Short name T614
Test name
Test status
Simulation time 4023205793 ps
CPU time 11.87 seconds
Started Jul 22 04:47:59 PM PDT 24
Finished Jul 22 04:48:12 PM PDT 24
Peak memory 201016 kb
Host smart-70daf788-d62e-44c3-866a-b705d73b444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329064266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.2329064266
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.646169238
Short name T84
Test name
Test status
Simulation time 112514658157 ps
CPU time 167.19 seconds
Started Jul 22 04:48:03 PM PDT 24
Finished Jul 22 04:50:50 PM PDT 24
Peak memory 201200 kb
Host smart-f69465aa-e87a-4edf-82de-1422506c0550
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646169238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_combo_detect.646169238
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3729108981
Short name T321
Test name
Test status
Simulation time 2416181997 ps
CPU time 6.88 seconds
Started Jul 22 04:47:59 PM PDT 24
Finished Jul 22 04:48:06 PM PDT 24
Peak memory 200920 kb
Host smart-69acf4c8-cf97-419d-8861-5ec06ffcec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729108981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3729108981
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1476357277
Short name T621
Test name
Test status
Simulation time 2333298260 ps
CPU time 1.19 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:02 PM PDT 24
Peak memory 200948 kb
Host smart-0ef4eb28-fe24-4603-8487-fa147e3004bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476357277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1476357277
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2466154723
Short name T109
Test name
Test status
Simulation time 54807299055 ps
CPU time 136.51 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:50:17 PM PDT 24
Peak memory 201184 kb
Host smart-904d642a-2f6b-4ab1-a867-0840a8fdf847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466154723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.2466154723
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2196484981
Short name T195
Test name
Test status
Simulation time 4208309281 ps
CPU time 5.98 seconds
Started Jul 22 04:48:01 PM PDT 24
Finished Jul 22 04:48:08 PM PDT 24
Peak memory 200924 kb
Host smart-4dcca3ee-4b67-4d2d-91e6-8027376a6f6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196484981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.2196484981
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1825540535
Short name T152
Test name
Test status
Simulation time 3881025510 ps
CPU time 4.3 seconds
Started Jul 22 04:47:59 PM PDT 24
Finished Jul 22 04:48:04 PM PDT 24
Peak memory 200872 kb
Host smart-f5fd1dd2-b137-410f-b0b3-dd4e2ed44b51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825540535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.1825540535
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1870975475
Short name T477
Test name
Test status
Simulation time 2629884781 ps
CPU time 2.39 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:03 PM PDT 24
Peak memory 200964 kb
Host smart-488bd8de-f42e-4da9-b472-2fed6410dafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870975475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1870975475
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.110808434
Short name T523
Test name
Test status
Simulation time 2479854315 ps
CPU time 2.36 seconds
Started Jul 22 04:48:01 PM PDT 24
Finished Jul 22 04:48:04 PM PDT 24
Peak memory 200964 kb
Host smart-ceee03cb-e44e-4dce-a641-2f7b0c1dd54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110808434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.110808434
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.835938663
Short name T459
Test name
Test status
Simulation time 2257493025 ps
CPU time 2.06 seconds
Started Jul 22 04:48:01 PM PDT 24
Finished Jul 22 04:48:04 PM PDT 24
Peak memory 200972 kb
Host smart-bef84373-f6d3-4ba7-a3b2-b2087928d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835938663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.835938663
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1263507272
Short name T667
Test name
Test status
Simulation time 2540682992 ps
CPU time 2.23 seconds
Started Jul 22 04:47:58 PM PDT 24
Finished Jul 22 04:48:01 PM PDT 24
Peak memory 200908 kb
Host smart-d38b57e2-2df1-49ea-8207-308b82d77c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263507272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1263507272
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2717196388
Short name T281
Test name
Test status
Simulation time 22013373549 ps
CPU time 54.64 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:56 PM PDT 24
Peak memory 220720 kb
Host smart-feade6f6-7fcf-4a45-bda2-8e067979c11c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717196388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2717196388
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1967269759
Short name T214
Test name
Test status
Simulation time 2116896361 ps
CPU time 2.3 seconds
Started Jul 22 04:47:59 PM PDT 24
Finished Jul 22 04:48:02 PM PDT 24
Peak memory 200948 kb
Host smart-80ff8d0a-f334-45d9-9fb8-6ea4a2080597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967269759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1967269759
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.128835268
Short name T524
Test name
Test status
Simulation time 12419632364 ps
CPU time 27.27 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:28 PM PDT 24
Peak memory 200972 kb
Host smart-8a551970-dd65-450d-9512-01a1f7746c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128835268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_str
ess_all.128835268
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1505676185
Short name T302
Test name
Test status
Simulation time 23171046841 ps
CPU time 64.18 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:49:06 PM PDT 24
Peak memory 201376 kb
Host smart-698aeb0a-cc81-49ca-ad70-c0cbc651f4a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505676185 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1505676185
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2713656976
Short name T275
Test name
Test status
Simulation time 1295621730210 ps
CPU time 14.75 seconds
Started Jul 22 04:48:01 PM PDT 24
Finished Jul 22 04:48:17 PM PDT 24
Peak memory 201036 kb
Host smart-cf185ba5-88fb-4379-b874-5b5d277bbd6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713656976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.2713656976
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3823705331
Short name T629
Test name
Test status
Simulation time 2026232083 ps
CPU time 1.84 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:49:42 PM PDT 24
Peak memory 200956 kb
Host smart-9cfbcfee-cde1-424a-ae62-895eaec20fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823705331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3823705331
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3837215293
Short name T512
Test name
Test status
Simulation time 2976303432 ps
CPU time 2.61 seconds
Started Jul 22 04:50:13 PM PDT 24
Finished Jul 22 04:50:16 PM PDT 24
Peak memory 201020 kb
Host smart-390a1f6f-3340-4bb8-8eb5-128e1db13786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837215293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3
837215293
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1097583890
Short name T95
Test name
Test status
Simulation time 2740770327 ps
CPU time 7.03 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:43 PM PDT 24
Peak memory 200912 kb
Host smart-1ff19202-3b13-4835-96b2-550804eb5fc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097583890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.1097583890
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3500227359
Short name T457
Test name
Test status
Simulation time 2642264124 ps
CPU time 2.24 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:38 PM PDT 24
Peak memory 200916 kb
Host smart-93cb8876-ea67-491f-b0d9-9d3b808431e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500227359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.3500227359
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3314334428
Short name T679
Test name
Test status
Simulation time 2472489423 ps
CPU time 6.62 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:49:47 PM PDT 24
Peak memory 200824 kb
Host smart-664dbaf8-d63b-48b2-8960-b7e44d9c87e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314334428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3314334428
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3592038140
Short name T6
Test name
Test status
Simulation time 2107060192 ps
CPU time 2.27 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:50:48 PM PDT 24
Peak memory 200876 kb
Host smart-57988cfe-f7ab-4d88-b9cb-24a11af71a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592038140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3592038140
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.1788406643
Short name T589
Test name
Test status
Simulation time 2529960944 ps
CPU time 2.18 seconds
Started Jul 22 04:49:35 PM PDT 24
Finished Jul 22 04:49:37 PM PDT 24
Peak memory 200932 kb
Host smart-87da16ee-9865-4013-8f08-cdc9b99fd5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788406643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.1788406643
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1551314536
Short name T453
Test name
Test status
Simulation time 2117601679 ps
CPU time 3.33 seconds
Started Jul 22 04:49:37 PM PDT 24
Finished Jul 22 04:49:41 PM PDT 24
Peak memory 200900 kb
Host smart-d087007b-19e7-497a-b6ab-a2620ec1e034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551314536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1551314536
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.89382755
Short name T216
Test name
Test status
Simulation time 14603539693 ps
CPU time 9.45 seconds
Started Jul 22 04:49:35 PM PDT 24
Finished Jul 22 04:49:45 PM PDT 24
Peak memory 201024 kb
Host smart-dc7f1698-ca81-42f3-a2d5-a239f09710c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89382755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_str
ess_all.89382755
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3332357755
Short name T316
Test name
Test status
Simulation time 18833080566 ps
CPU time 48.37 seconds
Started Jul 22 04:49:38 PM PDT 24
Finished Jul 22 04:50:27 PM PDT 24
Peak memory 201368 kb
Host smart-914abeac-6484-4a6d-a8a7-0dd1ad2dd717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332357755 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3332357755
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1497440325
Short name T12
Test name
Test status
Simulation time 4179306326 ps
CPU time 1.63 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:38 PM PDT 24
Peak memory 200928 kb
Host smart-2eda7d6b-a141-4c45-b723-bafda5159dcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497440325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.1497440325
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.4196537064
Short name T542
Test name
Test status
Simulation time 2014495313 ps
CPU time 5.85 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:43 PM PDT 24
Peak memory 200952 kb
Host smart-1df3a4d5-491a-4059-92c3-6df0e64c52ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196537064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.4196537064
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.499948340
Short name T712
Test name
Test status
Simulation time 3243006479 ps
CPU time 8.42 seconds
Started Jul 22 04:49:37 PM PDT 24
Finished Jul 22 04:49:46 PM PDT 24
Peak memory 200996 kb
Host smart-e3f1f776-fbb6-4cd8-b181-03ff43da2ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499948340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.499948340
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.1835100565
Short name T101
Test name
Test status
Simulation time 115658149037 ps
CPU time 314.95 seconds
Started Jul 22 04:49:38 PM PDT 24
Finished Jul 22 04:54:54 PM PDT 24
Peak memory 201148 kb
Host smart-3c4deb1c-23eb-4f8c-b9c9-b4769c2b3783
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835100565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.1835100565
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.2323423433
Short name T353
Test name
Test status
Simulation time 86199101745 ps
CPU time 23.03 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:50:00 PM PDT 24
Peak memory 201224 kb
Host smart-ad7f90ed-135f-414d-828e-3b0c495cf1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323423433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.2323423433
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1859897692
Short name T496
Test name
Test status
Simulation time 4951949263 ps
CPU time 13.33 seconds
Started Jul 22 04:49:37 PM PDT 24
Finished Jul 22 04:49:51 PM PDT 24
Peak memory 200908 kb
Host smart-182c417c-7b2f-4371-ad28-ae3a9c63e5bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859897692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.1859897692
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.2693043640
Short name T624
Test name
Test status
Simulation time 3461615252 ps
CPU time 2.22 seconds
Started Jul 22 04:49:38 PM PDT 24
Finished Jul 22 04:49:41 PM PDT 24
Peak memory 201004 kb
Host smart-fda65a96-af14-44b4-a2d3-3689a0776092
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693043640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.2693043640
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3258171684
Short name T415
Test name
Test status
Simulation time 2609763774 ps
CPU time 6.96 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:44 PM PDT 24
Peak memory 201008 kb
Host smart-93df11b8-baca-44a3-91b5-df5e2877b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258171684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3258171684
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.1973066170
Short name T508
Test name
Test status
Simulation time 2445929500 ps
CPU time 7.17 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:44 PM PDT 24
Peak memory 200936 kb
Host smart-f414bc90-697c-409f-9252-b59493ae67bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973066170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.1973066170
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3451576305
Short name T788
Test name
Test status
Simulation time 2088100341 ps
CPU time 5.77 seconds
Started Jul 22 04:49:35 PM PDT 24
Finished Jul 22 04:49:42 PM PDT 24
Peak memory 200860 kb
Host smart-0f92344f-e758-4c69-a433-e1c78ba43c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451576305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3451576305
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.797765605
Short name T552
Test name
Test status
Simulation time 2525444756 ps
CPU time 3.34 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:40 PM PDT 24
Peak memory 200988 kb
Host smart-7c39232c-9eaf-4bc4-88e8-b18bebc25682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797765605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.797765605
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1545643954
Short name T413
Test name
Test status
Simulation time 2136546273 ps
CPU time 2.2 seconds
Started Jul 22 04:49:35 PM PDT 24
Finished Jul 22 04:49:37 PM PDT 24
Peak memory 200872 kb
Host smart-f7979d20-a917-459a-9d1d-1c156dfa1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545643954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1545643954
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.2110100689
Short name T790
Test name
Test status
Simulation time 14574485610 ps
CPU time 7.84 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:45 PM PDT 24
Peak memory 200908 kb
Host smart-eb75fed3-ef03-4dfd-b8fa-6b4aab1b4a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110100689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.2110100689
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2422806441
Short name T145
Test name
Test status
Simulation time 19412252557 ps
CPU time 50.57 seconds
Started Jul 22 04:49:37 PM PDT 24
Finished Jul 22 04:50:28 PM PDT 24
Peak memory 210900 kb
Host smart-9995e409-7738-4df7-b579-647e5be3a0cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422806441 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2422806441
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3154469855
Short name T574
Test name
Test status
Simulation time 11943751194 ps
CPU time 2.72 seconds
Started Jul 22 04:49:34 PM PDT 24
Finished Jul 22 04:49:37 PM PDT 24
Peak memory 201004 kb
Host smart-f2a26442-c126-4235-bd72-768953c0902f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154469855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.3154469855
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.3895935144
Short name T532
Test name
Test status
Simulation time 2011821509 ps
CPU time 5.5 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:49:50 PM PDT 24
Peak memory 200936 kb
Host smart-7539bab4-3b0f-4679-a8ac-7fb965f15442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895935144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.3895935144
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.225626082
Short name T174
Test name
Test status
Simulation time 3114981731 ps
CPU time 4.78 seconds
Started Jul 22 04:49:37 PM PDT 24
Finished Jul 22 04:49:43 PM PDT 24
Peak memory 200904 kb
Host smart-ab0b1b1e-bf8d-47d4-b526-44527d3e01f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225626082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.225626082
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3086262326
Short name T273
Test name
Test status
Simulation time 186753094583 ps
CPU time 456.15 seconds
Started Jul 22 04:49:38 PM PDT 24
Finished Jul 22 04:57:15 PM PDT 24
Peak memory 201152 kb
Host smart-3e04884f-4a91-4b44-96b1-adf34b0ab8c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086262326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.3086262326
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.513135100
Short name T610
Test name
Test status
Simulation time 25328980206 ps
CPU time 50.09 seconds
Started Jul 22 04:49:46 PM PDT 24
Finished Jul 22 04:50:37 PM PDT 24
Peak memory 201384 kb
Host smart-dae82763-daa9-4060-a269-93910472f8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513135100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_wi
th_pre_cond.513135100
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.4107030640
Short name T420
Test name
Test status
Simulation time 5118732943 ps
CPU time 14.46 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:49:54 PM PDT 24
Peak memory 200996 kb
Host smart-2087b734-1a72-4607-ae3c-cd0fb6dc891c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107030640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.4107030640
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.4027604444
Short name T514
Test name
Test status
Simulation time 2968464357 ps
CPU time 1.81 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:39 PM PDT 24
Peak memory 200920 kb
Host smart-2e4992f4-7a74-4ee2-98df-90c33ce50ec0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027604444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.4027604444
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.802006107
Short name T438
Test name
Test status
Simulation time 2614294185 ps
CPU time 7.37 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:49:48 PM PDT 24
Peak memory 200952 kb
Host smart-d16e73a5-5922-4b77-82c3-4b419a835cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802006107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.802006107
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.151719778
Short name T409
Test name
Test status
Simulation time 2463922164 ps
CPU time 3.63 seconds
Started Jul 22 04:49:37 PM PDT 24
Finished Jul 22 04:49:41 PM PDT 24
Peak memory 200916 kb
Host smart-f105d62f-9d1c-40d9-87d4-2f270c375b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151719778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.151719778
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3508047012
Short name T620
Test name
Test status
Simulation time 2176320789 ps
CPU time 1.06 seconds
Started Jul 22 04:49:37 PM PDT 24
Finished Jul 22 04:49:39 PM PDT 24
Peak memory 200944 kb
Host smart-f5ad12cc-d56a-49df-a029-56e1204102a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508047012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3508047012
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2048364924
Short name T582
Test name
Test status
Simulation time 2534220684 ps
CPU time 2.21 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:49:42 PM PDT 24
Peak memory 200940 kb
Host smart-c09d6300-6004-46d0-9487-07365adcad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048364924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2048364924
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.1353613902
Short name T692
Test name
Test status
Simulation time 2111473856 ps
CPU time 6.1 seconds
Started Jul 22 04:49:36 PM PDT 24
Finished Jul 22 04:49:43 PM PDT 24
Peak memory 200864 kb
Host smart-7ef4bd0b-da42-4b2f-bb8e-f732de093cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353613902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1353613902
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.1580824549
Short name T90
Test name
Test status
Simulation time 67965762235 ps
CPU time 86.19 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:51:11 PM PDT 24
Peak memory 209712 kb
Host smart-237ad772-8932-42f0-939f-23e9a8eefc8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580824549 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.1580824549
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3849301350
Short name T125
Test name
Test status
Simulation time 6620836529 ps
CPU time 1.22 seconds
Started Jul 22 04:49:39 PM PDT 24
Finished Jul 22 04:49:41 PM PDT 24
Peak memory 200928 kb
Host smart-356b127b-b45e-4dd8-a329-91c122ad42c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849301350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3849301350
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.4072734459
Short name T691
Test name
Test status
Simulation time 2011603203 ps
CPU time 5.93 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:49:51 PM PDT 24
Peak memory 200928 kb
Host smart-f59c875c-f819-4521-ac28-8793d838f7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072734459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.4072734459
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.1242698090
Short name T558
Test name
Test status
Simulation time 3381228690 ps
CPU time 4.95 seconds
Started Jul 22 04:49:47 PM PDT 24
Finished Jul 22 04:49:53 PM PDT 24
Peak memory 201076 kb
Host smart-28dc64af-2382-46fb-b597-0df67a5890d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242698090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.1
242698090
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.2752261223
Short name T268
Test name
Test status
Simulation time 148744130249 ps
CPU time 89.73 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:51:15 PM PDT 24
Peak memory 201124 kb
Host smart-cbfec809-c13b-4e93-afe2-5f9604e8bc27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752261223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.2752261223
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1075707891
Short name T572
Test name
Test status
Simulation time 51643931525 ps
CPU time 58.61 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:50:44 PM PDT 24
Peak memory 201280 kb
Host smart-f41b9aae-128f-4dc2-9f4a-6745738e147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075707891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.1075707891
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1207161625
Short name T403
Test name
Test status
Simulation time 3060064745 ps
CPU time 8.74 seconds
Started Jul 22 04:49:48 PM PDT 24
Finished Jul 22 04:49:57 PM PDT 24
Peak memory 200932 kb
Host smart-96bffaca-912b-4102-850b-db9db7061825
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207161625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.1207161625
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.4066217806
Short name T225
Test name
Test status
Simulation time 2856994577 ps
CPU time 2.3 seconds
Started Jul 22 04:49:47 PM PDT 24
Finished Jul 22 04:49:49 PM PDT 24
Peak memory 201012 kb
Host smart-8659e1a5-4685-4660-b50d-f0b5fa64b55b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066217806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.4066217806
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.426871355
Short name T483
Test name
Test status
Simulation time 2613563193 ps
CPU time 4.15 seconds
Started Jul 22 04:49:43 PM PDT 24
Finished Jul 22 04:49:48 PM PDT 24
Peak memory 200928 kb
Host smart-1d331dd5-57de-41a4-8a14-d2a824fd776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426871355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.426871355
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.4275526248
Short name T215
Test name
Test status
Simulation time 2470133065 ps
CPU time 6.94 seconds
Started Jul 22 04:53:07 PM PDT 24
Finished Jul 22 04:53:14 PM PDT 24
Peak memory 200956 kb
Host smart-3db47151-f80c-442b-8288-7e8ff66566c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275526248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.4275526248
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.879489487
Short name T531
Test name
Test status
Simulation time 2113227032 ps
CPU time 1.39 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:49:46 PM PDT 24
Peak memory 200900 kb
Host smart-eadbd70d-57b0-43f2-ae4a-49da6e38a9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879489487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.879489487
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2104727469
Short name T506
Test name
Test status
Simulation time 2526749403 ps
CPU time 2.2 seconds
Started Jul 22 04:49:47 PM PDT 24
Finished Jul 22 04:49:50 PM PDT 24
Peak memory 200936 kb
Host smart-bf650ce4-ab6b-48ca-9693-2a828f5fd25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104727469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2104727469
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.166189962
Short name T308
Test name
Test status
Simulation time 2124057317 ps
CPU time 2.18 seconds
Started Jul 22 04:49:47 PM PDT 24
Finished Jul 22 04:49:50 PM PDT 24
Peak memory 200856 kb
Host smart-c89b3ac2-3e26-4d68-889c-560f871c4a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166189962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.166189962
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2024561634
Short name T33
Test name
Test status
Simulation time 62699806708 ps
CPU time 39.58 seconds
Started Jul 22 04:53:07 PM PDT 24
Finished Jul 22 04:53:47 PM PDT 24
Peak memory 209616 kb
Host smart-3424529b-b5b2-4d0d-b7e6-ce4cf653b41b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024561634 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.2024561634
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3352042057
Short name T129
Test name
Test status
Simulation time 6078810914 ps
CPU time 7.3 seconds
Started Jul 22 04:49:45 PM PDT 24
Finished Jul 22 04:49:53 PM PDT 24
Peak memory 200964 kb
Host smart-062aa07e-96e2-482f-a8fa-74e6022c0a82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352042057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.3352042057
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.1090215423
Short name T646
Test name
Test status
Simulation time 2027090797 ps
CPU time 1.91 seconds
Started Jul 22 04:50:26 PM PDT 24
Finished Jul 22 04:50:28 PM PDT 24
Peak memory 200932 kb
Host smart-57c1cccc-8204-4e16-bef6-ad51cc94cb0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090215423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.1090215423
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.4129519436
Short name T74
Test name
Test status
Simulation time 2923758984 ps
CPU time 4.14 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:49:49 PM PDT 24
Peak memory 201088 kb
Host smart-3c699e27-fe99-4412-a21c-b717b1031d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129519436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.4
129519436
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.3547770602
Short name T342
Test name
Test status
Simulation time 138118032620 ps
CPU time 180.25 seconds
Started Jul 22 04:49:43 PM PDT 24
Finished Jul 22 04:52:44 PM PDT 24
Peak memory 201128 kb
Host smart-a2b24af8-d937-416b-8040-b76ef7744713
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547770602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.3547770602
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.686273858
Short name T76
Test name
Test status
Simulation time 136446409501 ps
CPU time 91.6 seconds
Started Jul 22 04:49:48 PM PDT 24
Finished Jul 22 04:51:20 PM PDT 24
Peak memory 201228 kb
Host smart-5ec0c2e9-a9e1-4c9e-817c-5e432155b910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686273858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_wi
th_pre_cond.686273858
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2753110886
Short name T487
Test name
Test status
Simulation time 2866810732 ps
CPU time 1.69 seconds
Started Jul 22 04:49:48 PM PDT 24
Finished Jul 22 04:49:50 PM PDT 24
Peak memory 201000 kb
Host smart-74c3a720-e3d4-4394-ba98-4f9eb8bc1fb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753110886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.2753110886
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1691814335
Short name T590
Test name
Test status
Simulation time 1039225788501 ps
CPU time 4.06 seconds
Started Jul 22 04:50:18 PM PDT 24
Finished Jul 22 04:50:22 PM PDT 24
Peak memory 201052 kb
Host smart-c6a8884a-a054-4edf-881c-5bc7b35b7e3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691814335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.1691814335
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.55663037
Short name T97
Test name
Test status
Simulation time 2616028501 ps
CPU time 4.08 seconds
Started Jul 22 04:49:44 PM PDT 24
Finished Jul 22 04:49:49 PM PDT 24
Peak memory 201020 kb
Host smart-bc12219f-a00a-469c-8fad-e445bb2f5b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55663037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.55663037
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3384336868
Short name T431
Test name
Test status
Simulation time 2471268896 ps
CPU time 7.22 seconds
Started Jul 22 04:49:46 PM PDT 24
Finished Jul 22 04:49:54 PM PDT 24
Peak memory 200956 kb
Host smart-00fa8871-a3bd-444e-ada7-dbbc406eb990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384336868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3384336868
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.22887463
Short name T731
Test name
Test status
Simulation time 2243642774 ps
CPU time 1.92 seconds
Started Jul 22 04:49:45 PM PDT 24
Finished Jul 22 04:49:47 PM PDT 24
Peak memory 200960 kb
Host smart-cd674a6a-9509-4413-b64d-4d63bc5ee33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22887463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.22887463
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2756736157
Short name T464
Test name
Test status
Simulation time 2535562350 ps
CPU time 2.36 seconds
Started Jul 22 04:49:46 PM PDT 24
Finished Jul 22 04:49:49 PM PDT 24
Peak memory 200940 kb
Host smart-09ecc1a7-980f-4f9f-9f1b-7eb66b4a0854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756736157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2756736157
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.2277707928
Short name T414
Test name
Test status
Simulation time 2171564814 ps
CPU time 1.09 seconds
Started Jul 22 04:49:43 PM PDT 24
Finished Jul 22 04:49:46 PM PDT 24
Peak memory 201280 kb
Host smart-06df3eb9-bd2c-4971-91f8-72655191b45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277707928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2277707928
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.2512877676
Short name T429
Test name
Test status
Simulation time 7083722393 ps
CPU time 9.55 seconds
Started Jul 22 04:49:52 PM PDT 24
Finished Jul 22 04:50:03 PM PDT 24
Peak memory 200924 kb
Host smart-3c847e34-d03c-49bf-84f3-e37bd7bbd1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512877676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.2512877676
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1340918877
Short name T603
Test name
Test status
Simulation time 2580632725 ps
CPU time 2.42 seconds
Started Jul 22 04:53:07 PM PDT 24
Finished Jul 22 04:53:10 PM PDT 24
Peak memory 200940 kb
Host smart-ca292323-54f0-472f-890b-3cbc21ea38d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340918877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1340918877
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.2607446130
Short name T778
Test name
Test status
Simulation time 2033471836 ps
CPU time 2.09 seconds
Started Jul 22 04:49:54 PM PDT 24
Finished Jul 22 04:49:57 PM PDT 24
Peak memory 200932 kb
Host smart-066b940e-b7aa-47c7-bdbe-b17551cced71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607446130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.2607446130
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.329263383
Short name T21
Test name
Test status
Simulation time 3829761889 ps
CPU time 3.25 seconds
Started Jul 22 04:49:53 PM PDT 24
Finished Jul 22 04:49:57 PM PDT 24
Peak memory 200996 kb
Host smart-23c16880-52b9-40bc-805d-d8119e4e5fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329263383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.329263383
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2718116284
Short name T760
Test name
Test status
Simulation time 43209755613 ps
CPU time 104.15 seconds
Started Jul 22 04:49:52 PM PDT 24
Finished Jul 22 04:51:37 PM PDT 24
Peak memory 201116 kb
Host smart-f7c1cfab-d7c7-4c5e-bcfc-327203c416f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718116284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.2718116284
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3159047466
Short name T242
Test name
Test status
Simulation time 33884343624 ps
CPU time 49.4 seconds
Started Jul 22 04:49:52 PM PDT 24
Finished Jul 22 04:50:42 PM PDT 24
Peak memory 201336 kb
Host smart-79c6cd16-b96e-4036-8e9c-2cd26135911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159047466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.3159047466
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3331847624
Short name T551
Test name
Test status
Simulation time 2747090596 ps
CPU time 3.88 seconds
Started Jul 22 04:49:54 PM PDT 24
Finished Jul 22 04:49:59 PM PDT 24
Peak memory 200928 kb
Host smart-c899959a-7afa-4bda-9105-df6d79674898
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331847624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.3331847624
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2553458890
Short name T9
Test name
Test status
Simulation time 4761702533 ps
CPU time 3.44 seconds
Started Jul 22 04:50:20 PM PDT 24
Finished Jul 22 04:50:25 PM PDT 24
Peak memory 200984 kb
Host smart-086a67f3-864b-4034-9cc0-52943b903058
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553458890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.2553458890
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1768398942
Short name T207
Test name
Test status
Simulation time 2610994294 ps
CPU time 7.31 seconds
Started Jul 22 04:49:52 PM PDT 24
Finished Jul 22 04:50:00 PM PDT 24
Peak memory 200940 kb
Host smart-dcce55b2-5b75-46d4-87e3-f1e137264d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768398942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1768398942
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1258858836
Short name T231
Test name
Test status
Simulation time 2466762620 ps
CPU time 2.17 seconds
Started Jul 22 04:49:53 PM PDT 24
Finished Jul 22 04:49:56 PM PDT 24
Peak memory 200956 kb
Host smart-a3e0cde8-3936-47fa-9202-1105750961ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258858836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1258858836
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.1758474689
Short name T490
Test name
Test status
Simulation time 2050560025 ps
CPU time 5.87 seconds
Started Jul 22 04:49:54 PM PDT 24
Finished Jul 22 04:50:00 PM PDT 24
Peak memory 200876 kb
Host smart-3314f663-7f93-4ae7-ad02-73e5caae6625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758474689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.1758474689
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3064033654
Short name T276
Test name
Test status
Simulation time 2518449635 ps
CPU time 3.76 seconds
Started Jul 22 04:49:51 PM PDT 24
Finished Jul 22 04:49:56 PM PDT 24
Peak memory 200988 kb
Host smart-5570d141-84e0-4467-ba41-fa2855eb927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064033654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3064033654
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2446439118
Short name T499
Test name
Test status
Simulation time 2251026496 ps
CPU time 0.9 seconds
Started Jul 22 04:49:53 PM PDT 24
Finished Jul 22 04:49:55 PM PDT 24
Peak memory 200944 kb
Host smart-a4cfef85-4af6-47af-ade5-2b001e7d7537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446439118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2446439118
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3739125244
Short name T150
Test name
Test status
Simulation time 13413694615 ps
CPU time 30.03 seconds
Started Jul 22 04:49:53 PM PDT 24
Finished Jul 22 04:50:24 PM PDT 24
Peak memory 201024 kb
Host smart-d9b4707f-70ea-4ba9-8ec8-3014c2c90276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739125244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3739125244
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.889791519
Short name T135
Test name
Test status
Simulation time 181719033902 ps
CPU time 8.74 seconds
Started Jul 22 04:49:52 PM PDT 24
Finished Jul 22 04:50:02 PM PDT 24
Peak memory 200916 kb
Host smart-648409b4-c6f7-4b72-a489-173ddd02ba0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889791519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ultra_low_pwr.889791519
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.2646592114
Short name T567
Test name
Test status
Simulation time 2016643660 ps
CPU time 3.08 seconds
Started Jul 22 04:50:02 PM PDT 24
Finished Jul 22 04:50:05 PM PDT 24
Peak memory 201016 kb
Host smart-7170396e-50f2-45b7-91ab-0e9e8a549813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646592114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.2646592114
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3595016812
Short name T697
Test name
Test status
Simulation time 3502357348 ps
CPU time 9.13 seconds
Started Jul 22 04:50:00 PM PDT 24
Finished Jul 22 04:50:09 PM PDT 24
Peak memory 201032 kb
Host smart-767c6402-6cc0-4e58-8c4b-e3be49d8c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595016812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.3
595016812
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2377832962
Short name T110
Test name
Test status
Simulation time 50045473276 ps
CPU time 26.41 seconds
Started Jul 22 04:50:01 PM PDT 24
Finished Jul 22 04:50:28 PM PDT 24
Peak memory 201276 kb
Host smart-e1cc8a79-0886-49b9-a11e-3159b66af6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377832962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.2377832962
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1879955366
Short name T265
Test name
Test status
Simulation time 4096199723 ps
CPU time 10.41 seconds
Started Jul 22 04:50:24 PM PDT 24
Finished Jul 22 04:50:35 PM PDT 24
Peak memory 200952 kb
Host smart-7e311cd9-86dd-47fd-84ab-c97f63aa218c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879955366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.1879955366
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2419219714
Short name T42
Test name
Test status
Simulation time 3067147174 ps
CPU time 1.28 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:50:48 PM PDT 24
Peak memory 200952 kb
Host smart-f73e0d5f-da4c-480c-b92c-77e897d7d8a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419219714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2419219714
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1729710369
Short name T518
Test name
Test status
Simulation time 2611570678 ps
CPU time 6.8 seconds
Started Jul 22 04:49:54 PM PDT 24
Finished Jul 22 04:50:01 PM PDT 24
Peak memory 201024 kb
Host smart-8d986608-42f6-434f-9ff9-14e1fce31a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729710369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1729710369
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1348011383
Short name T313
Test name
Test status
Simulation time 2465933268 ps
CPU time 7.33 seconds
Started Jul 22 04:49:52 PM PDT 24
Finished Jul 22 04:50:00 PM PDT 24
Peak memory 200944 kb
Host smart-30be3c32-1efc-449b-bbcc-7dd198a03b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348011383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1348011383
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3485790738
Short name T201
Test name
Test status
Simulation time 2137803933 ps
CPU time 1.59 seconds
Started Jul 22 04:50:02 PM PDT 24
Finished Jul 22 04:50:04 PM PDT 24
Peak memory 200872 kb
Host smart-ee3f9e3b-1c46-48dd-90d9-11c908ce5271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485790738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3485790738
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3375566194
Short name T224
Test name
Test status
Simulation time 2512260682 ps
CPU time 7.21 seconds
Started Jul 22 04:49:52 PM PDT 24
Finished Jul 22 04:50:00 PM PDT 24
Peak memory 200920 kb
Host smart-42204680-ad5c-4929-9d57-6de47bd62adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375566194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3375566194
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.4233771853
Short name T173
Test name
Test status
Simulation time 2112837201 ps
CPU time 6.04 seconds
Started Jul 22 04:53:07 PM PDT 24
Finished Jul 22 04:53:14 PM PDT 24
Peak memory 200884 kb
Host smart-ceffde4d-2ee7-4c23-a576-4b059708ba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233771853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.4233771853
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2923029089
Short name T520
Test name
Test status
Simulation time 60167806777 ps
CPU time 151.93 seconds
Started Jul 22 04:50:00 PM PDT 24
Finished Jul 22 04:52:32 PM PDT 24
Peak memory 201064 kb
Host smart-6d558816-029e-4669-95db-2a2e8f700b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923029089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2923029089
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.90547811
Short name T126
Test name
Test status
Simulation time 67479689706 ps
CPU time 155.06 seconds
Started Jul 22 04:50:37 PM PDT 24
Finished Jul 22 04:53:12 PM PDT 24
Peak memory 209584 kb
Host smart-a3abecff-b9ff-4130-8efa-e94a2ae82e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90547811 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.90547811
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.617615415
Short name T725
Test name
Test status
Simulation time 7964251353 ps
CPU time 2.79 seconds
Started Jul 22 04:50:00 PM PDT 24
Finished Jul 22 04:50:03 PM PDT 24
Peak memory 201036 kb
Host smart-f4776d78-7d19-4c1f-a163-11cd49782ce9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617615415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.617615415
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.3360553761
Short name T444
Test name
Test status
Simulation time 2065505769 ps
CPU time 1.13 seconds
Started Jul 22 04:50:12 PM PDT 24
Finished Jul 22 04:50:13 PM PDT 24
Peak memory 201012 kb
Host smart-e8b9fa74-3c66-425d-b597-f76ffce98767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360553761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.3360553761
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3090013883
Short name T87
Test name
Test status
Simulation time 3407303859 ps
CPU time 2.79 seconds
Started Jul 22 04:50:01 PM PDT 24
Finished Jul 22 04:50:04 PM PDT 24
Peak memory 201028 kb
Host smart-93e11761-7b76-49ff-8857-8260c7c31fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090013883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3
090013883
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3623190567
Short name T89
Test name
Test status
Simulation time 30105566760 ps
CPU time 22.23 seconds
Started Jul 22 04:50:00 PM PDT 24
Finished Jul 22 04:50:22 PM PDT 24
Peak memory 201268 kb
Host smart-f51fa7f0-254a-4e6c-8ac1-fcbb3f089634
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623190567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.3623190567
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2068139601
Short name T247
Test name
Test status
Simulation time 27832288299 ps
CPU time 67.92 seconds
Started Jul 22 04:50:33 PM PDT 24
Finished Jul 22 04:51:41 PM PDT 24
Peak memory 200832 kb
Host smart-ed9cadc0-2fa2-4a7d-9be5-f08f59356245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068139601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.2068139601
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.46585056
Short name T495
Test name
Test status
Simulation time 5409848183 ps
CPU time 3.71 seconds
Started Jul 22 04:53:07 PM PDT 24
Finished Jul 22 04:53:11 PM PDT 24
Peak memory 200952 kb
Host smart-17d62070-9858-4923-817b-da6ae58e4838
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46585056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_ec_pwr_on_rst.46585056
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1125353191
Short name T59
Test name
Test status
Simulation time 2613374062 ps
CPU time 6.97 seconds
Started Jul 22 04:49:59 PM PDT 24
Finished Jul 22 04:50:06 PM PDT 24
Peak memory 201024 kb
Host smart-2ada5b9a-68b6-4ac0-ba71-473fbd80a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125353191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.1125353191
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2187343637
Short name T445
Test name
Test status
Simulation time 2471492035 ps
CPU time 2.4 seconds
Started Jul 22 04:50:01 PM PDT 24
Finished Jul 22 04:50:04 PM PDT 24
Peak memory 200952 kb
Host smart-e21578a6-712d-4ee3-a8a5-b2250221addc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187343637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2187343637
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1293538993
Short name T430
Test name
Test status
Simulation time 2072436850 ps
CPU time 3.38 seconds
Started Jul 22 04:50:01 PM PDT 24
Finished Jul 22 04:50:05 PM PDT 24
Peak memory 200876 kb
Host smart-f61c13b7-258c-4bc3-9f84-e0a36dcf23ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293538993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1293538993
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.595264740
Short name T666
Test name
Test status
Simulation time 2529514200 ps
CPU time 2.31 seconds
Started Jul 22 04:50:37 PM PDT 24
Finished Jul 22 04:50:40 PM PDT 24
Peak memory 200608 kb
Host smart-687276e7-e1d7-41af-ab15-96788f31f224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595264740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.595264740
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.1819249630
Short name T655
Test name
Test status
Simulation time 2153041726 ps
CPU time 1.51 seconds
Started Jul 22 04:50:02 PM PDT 24
Finished Jul 22 04:50:04 PM PDT 24
Peak memory 201012 kb
Host smart-8ebbe60d-5b8b-4bd2-a205-0de7140167a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819249630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.1819249630
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.991941630
Short name T769
Test name
Test status
Simulation time 114206392519 ps
CPU time 64.02 seconds
Started Jul 22 04:50:43 PM PDT 24
Finished Jul 22 04:51:48 PM PDT 24
Peak memory 201288 kb
Host smart-6c4b2ddb-6260-44d5-8eec-a61583dbd1e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991941630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_st
ress_all.991941630
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3044414043
Short name T703
Test name
Test status
Simulation time 2469060845901 ps
CPU time 215.1 seconds
Started Jul 22 04:50:00 PM PDT 24
Finished Jul 22 04:53:36 PM PDT 24
Peak memory 200900 kb
Host smart-c3ef6e14-1601-4d2a-8c8c-b3a68a8bb3e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044414043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.3044414043
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.2210732905
Short name T791
Test name
Test status
Simulation time 2022602905 ps
CPU time 3.33 seconds
Started Jul 22 04:50:11 PM PDT 24
Finished Jul 22 04:50:14 PM PDT 24
Peak memory 200928 kb
Host smart-1f680ee4-8b01-4802-a76b-da43d60901be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210732905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.2210732905
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.1162409916
Short name T300
Test name
Test status
Simulation time 3743584704 ps
CPU time 9.11 seconds
Started Jul 22 04:50:11 PM PDT 24
Finished Jul 22 04:50:21 PM PDT 24
Peak memory 201016 kb
Host smart-01e2e564-3e9e-492e-afad-3a39c9258452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162409916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.1
162409916
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.4027334953
Short name T656
Test name
Test status
Simulation time 89627267435 ps
CPU time 60.01 seconds
Started Jul 22 04:50:10 PM PDT 24
Finished Jul 22 04:51:11 PM PDT 24
Peak memory 201116 kb
Host smart-a7e12018-9179-45bb-9807-ce376b2534b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027334953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.4027334953
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.4240344063
Short name T235
Test name
Test status
Simulation time 3768195031 ps
CPU time 2.83 seconds
Started Jul 22 04:50:16 PM PDT 24
Finished Jul 22 04:50:20 PM PDT 24
Peak memory 200960 kb
Host smart-827c27e4-09f0-4a66-bc29-89735dea1708
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240344063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.4240344063
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1125246740
Short name T8
Test name
Test status
Simulation time 3658144203 ps
CPU time 7.62 seconds
Started Jul 22 04:50:11 PM PDT 24
Finished Jul 22 04:50:19 PM PDT 24
Peak memory 200952 kb
Host smart-1453473e-1e8d-40f4-9658-696162ecfc08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125246740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.1125246740
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1641399536
Short name T180
Test name
Test status
Simulation time 2644301978 ps
CPU time 1.78 seconds
Started Jul 22 04:50:10 PM PDT 24
Finished Jul 22 04:50:12 PM PDT 24
Peak memory 200920 kb
Host smart-77864cfe-85cd-4e32-812c-deba1f67bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641399536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.1641399536
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1866126431
Short name T443
Test name
Test status
Simulation time 2462369479 ps
CPU time 7.85 seconds
Started Jul 22 04:50:11 PM PDT 24
Finished Jul 22 04:50:19 PM PDT 24
Peak memory 200952 kb
Host smart-1e475357-747b-439f-a5dc-1bc88bf63cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866126431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.1866126431
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.215945452
Short name T602
Test name
Test status
Simulation time 2251257330 ps
CPU time 0.91 seconds
Started Jul 22 04:50:09 PM PDT 24
Finished Jul 22 04:50:10 PM PDT 24
Peak memory 201020 kb
Host smart-c8f689ab-e71c-41c5-9097-f62ad7d3bdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215945452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.215945452
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1405904621
Short name T556
Test name
Test status
Simulation time 2518697558 ps
CPU time 3.85 seconds
Started Jul 22 04:50:09 PM PDT 24
Finished Jul 22 04:50:14 PM PDT 24
Peak memory 200912 kb
Host smart-2bebc6c3-a95f-43bf-83ad-50d604e8afa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405904621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1405904621
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.3604181629
Short name T452
Test name
Test status
Simulation time 2112304684 ps
CPU time 6.23 seconds
Started Jul 22 04:50:43 PM PDT 24
Finished Jul 22 04:50:50 PM PDT 24
Peak memory 200944 kb
Host smart-ef7522a7-b4c1-417a-9e57-8d5c2506f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604181629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3604181629
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.2037776940
Short name T141
Test name
Test status
Simulation time 9965301658 ps
CPU time 19.74 seconds
Started Jul 22 04:50:12 PM PDT 24
Finished Jul 22 04:50:32 PM PDT 24
Peak memory 200960 kb
Host smart-00c362f5-a40c-4601-84c8-a60417735f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037776940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.2037776940
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.4223575066
Short name T534
Test name
Test status
Simulation time 7526553818 ps
CPU time 4.02 seconds
Started Jul 22 04:50:12 PM PDT 24
Finished Jul 22 04:50:17 PM PDT 24
Peak memory 200960 kb
Host smart-05e64b3d-f398-4d44-8448-ea101996c1da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223575066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.4223575066
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.714540065
Short name T412
Test name
Test status
Simulation time 2015941319 ps
CPU time 5.15 seconds
Started Jul 22 04:50:23 PM PDT 24
Finished Jul 22 04:50:28 PM PDT 24
Peak memory 201008 kb
Host smart-95b2f9eb-b27c-4dbb-9833-75cebc122012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714540065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_tes
t.714540065
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1196577365
Short name T565
Test name
Test status
Simulation time 3776457329 ps
CPU time 3.76 seconds
Started Jul 22 04:50:20 PM PDT 24
Finished Jul 22 04:50:25 PM PDT 24
Peak memory 201068 kb
Host smart-889fa981-0a4b-41c8-9ade-92310383685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196577365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
196577365
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3233724071
Short name T258
Test name
Test status
Simulation time 75842987914 ps
CPU time 46.75 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:51:07 PM PDT 24
Peak memory 201140 kb
Host smart-612228c2-ac9b-4664-8b17-e4780e4b253e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233724071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.3233724071
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2630110241
Short name T271
Test name
Test status
Simulation time 148460351125 ps
CPU time 357.19 seconds
Started Jul 22 04:50:21 PM PDT 24
Finished Jul 22 04:56:18 PM PDT 24
Peak memory 201308 kb
Host smart-3c0918c3-a077-44c3-a99a-2c4027f6ba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630110241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2630110241
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2362937761
Short name T121
Test name
Test status
Simulation time 3257390758 ps
CPU time 9.42 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:50:30 PM PDT 24
Peak memory 201000 kb
Host smart-93d53e30-41bb-42e8-af80-590e05214165
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362937761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.2362937761
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.3599942982
Short name T206
Test name
Test status
Simulation time 4892157485 ps
CPU time 2.55 seconds
Started Jul 22 04:50:20 PM PDT 24
Finished Jul 22 04:50:23 PM PDT 24
Peak memory 200928 kb
Host smart-3abd732b-785c-4dec-a4b1-a8d30adbc801
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599942982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.3599942982
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.225967546
Short name T100
Test name
Test status
Simulation time 2616508017 ps
CPU time 3.83 seconds
Started Jul 22 04:50:23 PM PDT 24
Finished Jul 22 04:50:27 PM PDT 24
Peak memory 201004 kb
Host smart-9e7eaf2e-31c8-44bb-9f8d-6a95b1aad73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225967546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.225967546
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2087313483
Short name T310
Test name
Test status
Simulation time 2523476881 ps
CPU time 1.35 seconds
Started Jul 22 04:50:10 PM PDT 24
Finished Jul 22 04:50:12 PM PDT 24
Peak memory 200908 kb
Host smart-d08aad8b-2071-4c0e-8504-93d7a78d09c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087313483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2087313483
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1107863254
Short name T638
Test name
Test status
Simulation time 2239293831 ps
CPU time 1.99 seconds
Started Jul 22 04:51:53 PM PDT 24
Finished Jul 22 04:51:55 PM PDT 24
Peak memory 200888 kb
Host smart-e4519e16-fa7a-4053-8ed5-f03e5fc2f05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107863254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1107863254
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.2999703075
Short name T571
Test name
Test status
Simulation time 2521860433 ps
CPU time 2.18 seconds
Started Jul 22 04:50:09 PM PDT 24
Finished Jul 22 04:50:12 PM PDT 24
Peak memory 200900 kb
Host smart-08a5f2f6-0072-4c53-ad23-60d3d6d09c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999703075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.2999703075
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.2420662474
Short name T500
Test name
Test status
Simulation time 2143775949 ps
CPU time 1.55 seconds
Started Jul 22 04:50:11 PM PDT 24
Finished Jul 22 04:50:13 PM PDT 24
Peak memory 200848 kb
Host smart-4ddc5ee3-f376-47d0-ac0b-60536fee1ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420662474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.2420662474
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3901571145
Short name T62
Test name
Test status
Simulation time 8407170927 ps
CPU time 11.54 seconds
Started Jul 22 04:50:20 PM PDT 24
Finished Jul 22 04:50:32 PM PDT 24
Peak memory 200924 kb
Host smart-b31901ad-7d6c-4687-b921-06a66d1a1ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901571145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3901571145
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.412196844
Short name T167
Test name
Test status
Simulation time 51066885395 ps
CPU time 123.67 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:52:23 PM PDT 24
Peak memory 209668 kb
Host smart-40233070-8bd4-4b56-ace0-8210271478df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412196844 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.412196844
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.551634724
Short name T541
Test name
Test status
Simulation time 7468712571 ps
CPU time 1.93 seconds
Started Jul 22 04:50:25 PM PDT 24
Finished Jul 22 04:50:28 PM PDT 24
Peak memory 200968 kb
Host smart-ad36a15d-4126-42f6-b1c9-1cfa0968acce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551634724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_ultra_low_pwr.551634724
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.2607650501
Short name T696
Test name
Test status
Simulation time 2095536734 ps
CPU time 0.95 seconds
Started Jul 22 04:48:11 PM PDT 24
Finished Jul 22 04:48:12 PM PDT 24
Peak memory 200952 kb
Host smart-df76d701-7738-493a-bb2c-dce598e9301f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607650501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.2607650501
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1823094152
Short name T511
Test name
Test status
Simulation time 161212109031 ps
CPU time 107.26 seconds
Started Jul 22 04:48:10 PM PDT 24
Finished Jul 22 04:49:58 PM PDT 24
Peak memory 201048 kb
Host smart-660dc99f-7895-4bf6-8534-01fff2a34fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823094152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1823094152
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.3177566953
Short name T34
Test name
Test status
Simulation time 158912688350 ps
CPU time 388.37 seconds
Started Jul 22 04:48:09 PM PDT 24
Finished Jul 22 04:54:38 PM PDT 24
Peak memory 201232 kb
Host smart-d85a64bd-db74-4e77-91db-eb235d77f155
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177566953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.3177566953
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.30352359
Short name T676
Test name
Test status
Simulation time 2401456324 ps
CPU time 7.16 seconds
Started Jul 22 04:48:12 PM PDT 24
Finished Jul 22 04:48:19 PM PDT 24
Peak memory 200948 kb
Host smart-11576e42-e165-4615-b5de-f83e7ff71bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30352359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.30352359
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3916416355
Short name T47
Test name
Test status
Simulation time 2533548100 ps
CPU time 7.44 seconds
Started Jul 22 04:48:12 PM PDT 24
Finished Jul 22 04:48:20 PM PDT 24
Peak memory 200952 kb
Host smart-c4380be3-ea31-4484-9c7c-fa9487a93681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916416355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3916416355
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.38032370
Short name T535
Test name
Test status
Simulation time 2488155878 ps
CPU time 2.21 seconds
Started Jul 22 04:48:12 PM PDT 24
Finished Jul 22 04:48:14 PM PDT 24
Peak memory 200916 kb
Host smart-860bde0a-8801-418c-962e-0bf3e21bb011
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38032370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_ec_pwr_on_rst.38032370
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.492195955
Short name T654
Test name
Test status
Simulation time 2748751236 ps
CPU time 2.18 seconds
Started Jul 22 04:48:11 PM PDT 24
Finished Jul 22 04:48:14 PM PDT 24
Peak memory 200884 kb
Host smart-37f09d3b-b944-4708-a3c4-93709e29d205
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492195955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_edge_detect.492195955
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1857788804
Short name T397
Test name
Test status
Simulation time 2619184157 ps
CPU time 3.15 seconds
Started Jul 22 04:48:11 PM PDT 24
Finished Jul 22 04:48:15 PM PDT 24
Peak memory 200964 kb
Host smart-c1fbe3ff-e429-4007-aabb-c6895b43f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857788804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.1857788804
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.554373045
Short name T618
Test name
Test status
Simulation time 2522446273 ps
CPU time 1.67 seconds
Started Jul 22 04:48:13 PM PDT 24
Finished Jul 22 04:48:15 PM PDT 24
Peak memory 200936 kb
Host smart-c407bc4f-cd85-4ede-be13-0eeab017e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554373045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.554373045
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3383057887
Short name T395
Test name
Test status
Simulation time 2279936611 ps
CPU time 1.69 seconds
Started Jul 22 04:48:11 PM PDT 24
Finished Jul 22 04:48:13 PM PDT 24
Peak memory 200932 kb
Host smart-20d8c046-ada5-4b92-9402-c822ee138d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383057887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3383057887
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2397044288
Short name T392
Test name
Test status
Simulation time 2511384586 ps
CPU time 7.26 seconds
Started Jul 22 04:48:39 PM PDT 24
Finished Jul 22 04:48:47 PM PDT 24
Peak memory 200940 kb
Host smart-8ca4a4b1-9e2f-4936-9157-cc4dccc516d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397044288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2397044288
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3774363433
Short name T297
Test name
Test status
Simulation time 22111481624 ps
CPU time 9.72 seconds
Started Jul 22 04:48:24 PM PDT 24
Finished Jul 22 04:48:35 PM PDT 24
Peak memory 220840 kb
Host smart-bdd7ebb2-4cee-4809-b339-fc52b489aa25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774363433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3774363433
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.4088147871
Short name T720
Test name
Test status
Simulation time 2113271944 ps
CPU time 4.84 seconds
Started Jul 22 04:48:37 PM PDT 24
Finished Jul 22 04:48:43 PM PDT 24
Peak memory 200828 kb
Host smart-427bf237-6887-4609-b9e0-a6bb019a6eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088147871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.4088147871
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2642765556
Short name T149
Test name
Test status
Simulation time 41502032293 ps
CPU time 27.2 seconds
Started Jul 22 04:48:12 PM PDT 24
Finished Jul 22 04:48:39 PM PDT 24
Peak memory 217604 kb
Host smart-af0b8c03-61a3-42bb-81ca-66c70adbda52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642765556 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2642765556
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2200802873
Short name T478
Test name
Test status
Simulation time 3248359137 ps
CPU time 6.28 seconds
Started Jul 22 04:48:10 PM PDT 24
Finished Jul 22 04:48:16 PM PDT 24
Peak memory 200928 kb
Host smart-302ee846-0677-470a-8d4d-47fece3435c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200802873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2200802873
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.2506107809
Short name T743
Test name
Test status
Simulation time 2014275298 ps
CPU time 3.42 seconds
Started Jul 22 04:50:23 PM PDT 24
Finished Jul 22 04:50:27 PM PDT 24
Peak memory 201008 kb
Host smart-f7264150-3907-4435-9cab-9e7b6476ae81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506107809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.2506107809
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.566584906
Short name T486
Test name
Test status
Simulation time 3425550216 ps
CPU time 8.56 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:50:29 PM PDT 24
Peak memory 201008 kb
Host smart-972620a4-ad78-4298-b549-5c3489b20a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566584906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.566584906
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.3477985776
Short name T350
Test name
Test status
Simulation time 96979593870 ps
CPU time 62.52 seconds
Started Jul 22 04:50:20 PM PDT 24
Finished Jul 22 04:51:23 PM PDT 24
Peak memory 201128 kb
Host smart-2fe5a792-b3ab-4375-8536-9f6bbd134e38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477985776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.3477985776
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3131191274
Short name T210
Test name
Test status
Simulation time 645765538897 ps
CPU time 856.99 seconds
Started Jul 22 04:50:18 PM PDT 24
Finished Jul 22 05:04:35 PM PDT 24
Peak memory 200912 kb
Host smart-44569b69-a037-4447-ad8b-a3ac61168b95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131191274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.3131191274
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1207527477
Short name T148
Test name
Test status
Simulation time 5394358443 ps
CPU time 9.82 seconds
Started Jul 22 04:50:20 PM PDT 24
Finished Jul 22 04:50:30 PM PDT 24
Peak memory 200960 kb
Host smart-78f27fed-c6aa-461e-af69-564cc3bb3224
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207527477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.1207527477
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.586141276
Short name T171
Test name
Test status
Simulation time 2614278262 ps
CPU time 3.93 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:50:24 PM PDT 24
Peak memory 200968 kb
Host smart-5dd3d506-7c41-4187-8edf-825a569d836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586141276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.586141276
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2469693322
Short name T407
Test name
Test status
Simulation time 2474231826 ps
CPU time 6.49 seconds
Started Jul 22 04:50:44 PM PDT 24
Finished Jul 22 04:50:51 PM PDT 24
Peak memory 201020 kb
Host smart-50c2788f-bedc-4ddf-8404-3d65279e0420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469693322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.2469693322
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.1472572060
Short name T158
Test name
Test status
Simulation time 2163540900 ps
CPU time 5.62 seconds
Started Jul 22 04:50:23 PM PDT 24
Finished Jul 22 04:50:29 PM PDT 24
Peak memory 200992 kb
Host smart-7eadf69c-12ae-4b06-a6dc-5678b6dd0863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472572060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.1472572060
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.4263917119
Short name T239
Test name
Test status
Simulation time 2526052282 ps
CPU time 2.22 seconds
Started Jul 22 04:50:18 PM PDT 24
Finished Jul 22 04:50:21 PM PDT 24
Peak memory 200932 kb
Host smart-7fa62c31-b019-49b7-9492-634a8c1c6f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263917119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.4263917119
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.392170394
Short name T674
Test name
Test status
Simulation time 2132745671 ps
CPU time 1.91 seconds
Started Jul 22 04:50:37 PM PDT 24
Finished Jul 22 04:50:40 PM PDT 24
Peak memory 200536 kb
Host smart-7a877dd6-f39c-4b4d-9cfb-dd05ecbe26a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392170394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.392170394
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2647128315
Short name T52
Test name
Test status
Simulation time 168984040621 ps
CPU time 202.42 seconds
Started Jul 22 04:50:18 PM PDT 24
Finished Jul 22 04:53:41 PM PDT 24
Peak memory 201220 kb
Host smart-d1ee2044-f0c4-4581-8464-c55bf14ce0f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647128315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2647128315
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.517930430
Short name T476
Test name
Test status
Simulation time 2054722952 ps
CPU time 1.53 seconds
Started Jul 22 04:50:48 PM PDT 24
Finished Jul 22 04:50:50 PM PDT 24
Peak memory 200924 kb
Host smart-7e1230fe-824c-4959-b278-9986e3db7032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517930430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_tes
t.517930430
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3140302189
Short name T544
Test name
Test status
Simulation time 3101733727 ps
CPU time 8.78 seconds
Started Jul 22 04:50:27 PM PDT 24
Finished Jul 22 04:50:37 PM PDT 24
Peak memory 201344 kb
Host smart-70447e7b-8f6b-416b-a1a8-77664c83df58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140302189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
140302189
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1675742601
Short name T367
Test name
Test status
Simulation time 88437672099 ps
CPU time 223.73 seconds
Started Jul 22 04:50:51 PM PDT 24
Finished Jul 22 04:54:35 PM PDT 24
Peak memory 201272 kb
Host smart-48b3c454-20e4-4086-bbea-6a35203e529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675742601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.1675742601
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3124122625
Short name T599
Test name
Test status
Simulation time 3396770230 ps
CPU time 2.95 seconds
Started Jul 22 04:50:31 PM PDT 24
Finished Jul 22 04:50:34 PM PDT 24
Peak memory 200932 kb
Host smart-d3e188aa-8e25-42d8-abdf-d1d0b5181941
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124122625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.3124122625
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2941954514
Short name T763
Test name
Test status
Simulation time 2636381635 ps
CPU time 1.87 seconds
Started Jul 22 04:50:30 PM PDT 24
Finished Jul 22 04:50:32 PM PDT 24
Peak memory 201004 kb
Host smart-68a07a66-636b-4559-aeb4-94ca7c3ff9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941954514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2941954514
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2855927048
Short name T749
Test name
Test status
Simulation time 2465814911 ps
CPU time 7.08 seconds
Started Jul 22 04:50:21 PM PDT 24
Finished Jul 22 04:50:28 PM PDT 24
Peak memory 200916 kb
Host smart-4a4b2e5f-06bd-497f-817f-f7f6924ea533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855927048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2855927048
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2176844622
Short name T488
Test name
Test status
Simulation time 2196968059 ps
CPU time 3.32 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:50:23 PM PDT 24
Peak memory 200916 kb
Host smart-39c0ead6-1aaa-4343-b007-68143b1f6704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176844622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2176844622
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.4129305816
Short name T236
Test name
Test status
Simulation time 2526257534 ps
CPU time 3.4 seconds
Started Jul 22 04:50:20 PM PDT 24
Finished Jul 22 04:50:24 PM PDT 24
Peak memory 200840 kb
Host smart-750e1f5b-d334-422b-9e61-3e50c4e6313f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129305816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.4129305816
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.2275453828
Short name T467
Test name
Test status
Simulation time 2111740783 ps
CPU time 5.97 seconds
Started Jul 22 04:50:19 PM PDT 24
Finished Jul 22 04:50:26 PM PDT 24
Peak memory 200804 kb
Host smart-fd2b44a3-a255-48aa-acc5-214934c45f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275453828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.2275453828
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.4054188642
Short name T625
Test name
Test status
Simulation time 9742681837 ps
CPU time 26.34 seconds
Started Jul 22 04:50:28 PM PDT 24
Finished Jul 22 04:50:55 PM PDT 24
Peak memory 200988 kb
Host smart-b223bcf4-9d01-4707-a5f2-d673da87175c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054188642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.4054188642
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1853540130
Short name T301
Test name
Test status
Simulation time 52827216508 ps
CPU time 122.96 seconds
Started Jul 22 04:50:30 PM PDT 24
Finished Jul 22 04:52:33 PM PDT 24
Peak memory 209612 kb
Host smart-c1451a89-1d90-4879-8f24-bc977ca2f323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853540130 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1853540130
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3824921092
Short name T709
Test name
Test status
Simulation time 2785834359 ps
CPU time 2.01 seconds
Started Jul 22 04:50:29 PM PDT 24
Finished Jul 22 04:50:31 PM PDT 24
Peak memory 200964 kb
Host smart-edcdcc1d-ac72-4375-bcef-f8a8ba29f188
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824921092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.3824921092
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.69322288
Short name T615
Test name
Test status
Simulation time 2054152047 ps
CPU time 1.76 seconds
Started Jul 22 04:51:53 PM PDT 24
Finished Jul 22 04:51:55 PM PDT 24
Peak memory 200912 kb
Host smart-f477d9b5-f00b-4fd8-88a2-1253cd85ee15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69322288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test
.69322288
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3560828710
Short name T693
Test name
Test status
Simulation time 3072023949 ps
CPU time 2.64 seconds
Started Jul 22 04:50:28 PM PDT 24
Finished Jul 22 04:50:31 PM PDT 24
Peak memory 201020 kb
Host smart-a0a20d31-7ae7-471e-a961-eae74c7e246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560828710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3
560828710
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.163201681
Short name T717
Test name
Test status
Simulation time 114539658128 ps
CPU time 64.02 seconds
Started Jul 22 04:50:29 PM PDT 24
Finished Jul 22 04:51:33 PM PDT 24
Peak memory 201152 kb
Host smart-6a6baf6e-9663-4e7a-a2de-c1c5ed0e3c35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163201681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_combo_detect.163201681
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3322355462
Short name T639
Test name
Test status
Simulation time 30605960605 ps
CPU time 20.14 seconds
Started Jul 22 04:50:33 PM PDT 24
Finished Jul 22 04:50:53 PM PDT 24
Peak memory 201368 kb
Host smart-dd5bb545-b7d5-49bd-ab3e-487be7464648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322355462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.3322355462
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.4075049850
Short name T727
Test name
Test status
Simulation time 3975923063 ps
CPU time 4.1 seconds
Started Jul 22 04:50:33 PM PDT 24
Finished Jul 22 04:50:38 PM PDT 24
Peak memory 200996 kb
Host smart-a47c22bf-f039-424c-940b-d1e32076d1b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075049850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.4075049850
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1182792099
Short name T203
Test name
Test status
Simulation time 3268838145 ps
CPU time 4.35 seconds
Started Jul 22 04:50:38 PM PDT 24
Finished Jul 22 04:50:43 PM PDT 24
Peak memory 200888 kb
Host smart-ba302d5f-f745-43d1-927e-964acc8829fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182792099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.1182792099
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.4230645371
Short name T418
Test name
Test status
Simulation time 2612086065 ps
CPU time 7.07 seconds
Started Jul 22 04:50:43 PM PDT 24
Finished Jul 22 04:50:50 PM PDT 24
Peak memory 200964 kb
Host smart-b4862a19-127d-42e7-bd07-b232f498c85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230645371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.4230645371
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1548645230
Short name T422
Test name
Test status
Simulation time 2486590276 ps
CPU time 3.92 seconds
Started Jul 22 04:52:36 PM PDT 24
Finished Jul 22 04:52:41 PM PDT 24
Peak memory 200932 kb
Host smart-6828ba8f-fa90-4db2-89be-f0f034856a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548645230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1548645230
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1144144743
Short name T493
Test name
Test status
Simulation time 2087662940 ps
CPU time 5.16 seconds
Started Jul 22 04:50:30 PM PDT 24
Finished Jul 22 04:50:35 PM PDT 24
Peak memory 200952 kb
Host smart-53478b82-0e19-4a77-95df-d22f85597dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144144743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1144144743
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3309933940
Short name T447
Test name
Test status
Simulation time 2513688598 ps
CPU time 7.12 seconds
Started Jul 22 04:50:28 PM PDT 24
Finished Jul 22 04:50:36 PM PDT 24
Peak memory 200940 kb
Host smart-ac7f05be-7172-46e5-b5da-6f4c5df2f201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309933940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.3309933940
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.2368652375
Short name T670
Test name
Test status
Simulation time 2123835412 ps
CPU time 2.08 seconds
Started Jul 22 04:50:27 PM PDT 24
Finished Jul 22 04:50:30 PM PDT 24
Peak memory 200852 kb
Host smart-86e128b5-76c8-4369-8201-43c4daf4baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368652375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2368652375
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.3187643981
Short name T306
Test name
Test status
Simulation time 14803994853 ps
CPU time 4.13 seconds
Started Jul 22 04:50:30 PM PDT 24
Finished Jul 22 04:50:35 PM PDT 24
Peak memory 200980 kb
Host smart-5e1a1e47-51a3-417a-a5c1-7bc7726d326d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187643981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.3187643981
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1112308473
Short name T530
Test name
Test status
Simulation time 24973730639 ps
CPU time 63.61 seconds
Started Jul 22 04:50:29 PM PDT 24
Finished Jul 22 04:51:33 PM PDT 24
Peak memory 201376 kb
Host smart-6f12bf26-df6f-433b-be29-373ffb550d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112308473 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1112308473
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.522767665
Short name T105
Test name
Test status
Simulation time 11705610084 ps
CPU time 9.84 seconds
Started Jul 22 04:50:31 PM PDT 24
Finished Jul 22 04:50:41 PM PDT 24
Peak memory 201000 kb
Host smart-59e1d301-1232-4ab1-9c76-ceef3902ae74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522767665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_ultra_low_pwr.522767665
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.111039295
Short name T485
Test name
Test status
Simulation time 2030188801 ps
CPU time 2.16 seconds
Started Jul 22 04:50:37 PM PDT 24
Finished Jul 22 04:50:40 PM PDT 24
Peak memory 200928 kb
Host smart-9c7503d8-4618-4ecf-ba8c-67a69e735c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111039295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_tes
t.111039295
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.4225282792
Short name T723
Test name
Test status
Simulation time 3535417976 ps
CPU time 5.09 seconds
Started Jul 22 04:50:28 PM PDT 24
Finished Jul 22 04:50:34 PM PDT 24
Peak memory 201016 kb
Host smart-25476b9d-ee0f-4e83-b866-62e8202445bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225282792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.4
225282792
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.242466823
Short name T345
Test name
Test status
Simulation time 164921493517 ps
CPU time 429.45 seconds
Started Jul 22 04:52:07 PM PDT 24
Finished Jul 22 04:59:17 PM PDT 24
Peak memory 201168 kb
Host smart-d34d68fc-5afb-41ff-8e19-fbe3ec4b8eb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242466823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_combo_detect.242466823
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2218363197
Short name T442
Test name
Test status
Simulation time 2823879959 ps
CPU time 2.06 seconds
Started Jul 22 04:50:28 PM PDT 24
Finished Jul 22 04:50:31 PM PDT 24
Peak memory 200880 kb
Host smart-dc96965e-54a2-40eb-b411-a5d74d02acb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218363197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.2218363197
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.385268353
Short name T557
Test name
Test status
Simulation time 2627870773 ps
CPU time 1.09 seconds
Started Jul 22 04:50:38 PM PDT 24
Finished Jul 22 04:50:40 PM PDT 24
Peak memory 201036 kb
Host smart-6b465c3f-5eb0-4865-b7d7-dedb22cb46b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385268353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctr
l_edge_detect.385268353
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3782389897
Short name T627
Test name
Test status
Simulation time 2637820368 ps
CPU time 1.76 seconds
Started Jul 22 04:52:36 PM PDT 24
Finished Jul 22 04:52:39 PM PDT 24
Peak memory 200712 kb
Host smart-e644d877-588d-48f3-bbaa-bccbfbb2a64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782389897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3782389897
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3343274654
Short name T781
Test name
Test status
Simulation time 2466358354 ps
CPU time 4.07 seconds
Started Jul 22 04:50:29 PM PDT 24
Finished Jul 22 04:50:34 PM PDT 24
Peak memory 201020 kb
Host smart-1219b761-5ff7-42b9-b213-99c7cdea033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343274654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.3343274654
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.495676449
Short name T325
Test name
Test status
Simulation time 2017804128 ps
CPU time 5.59 seconds
Started Jul 22 04:50:29 PM PDT 24
Finished Jul 22 04:50:35 PM PDT 24
Peak memory 200864 kb
Host smart-ff3f7ebe-4fbe-4123-b43e-d3a7a2ead857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495676449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.495676449
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3262802621
Short name T792
Test name
Test status
Simulation time 2521498664 ps
CPU time 4.02 seconds
Started Jul 22 04:50:30 PM PDT 24
Finished Jul 22 04:50:35 PM PDT 24
Peak memory 200880 kb
Host smart-50b9a037-7679-4e0e-811c-66841e797f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262802621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3262802621
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.958321403
Short name T426
Test name
Test status
Simulation time 2129769594 ps
CPU time 2.08 seconds
Started Jul 22 04:50:30 PM PDT 24
Finished Jul 22 04:50:33 PM PDT 24
Peak memory 200804 kb
Host smart-047461d4-7bc1-45a9-b5ae-9864b9417cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958321403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.958321403
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.567630417
Short name T240
Test name
Test status
Simulation time 9917772939 ps
CPU time 7.04 seconds
Started Jul 22 04:50:37 PM PDT 24
Finished Jul 22 04:50:44 PM PDT 24
Peak memory 200928 kb
Host smart-657ccdc2-7196-4ec9-b299-cb8adc9406ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567630417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_st
ress_all.567630417
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.802247138
Short name T387
Test name
Test status
Simulation time 38866223067 ps
CPU time 23.51 seconds
Started Jul 22 04:50:39 PM PDT 24
Finished Jul 22 04:51:03 PM PDT 24
Peak memory 209612 kb
Host smart-0fa41607-603b-49da-bf02-82786f2bea43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802247138 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.802247138
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3900859213
Short name T63
Test name
Test status
Simulation time 5395464235 ps
CPU time 2.06 seconds
Started Jul 22 04:50:28 PM PDT 24
Finished Jul 22 04:50:31 PM PDT 24
Peak memory 200912 kb
Host smart-863a8257-a058-4496-a74c-cc77b20ebeb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900859213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.3900859213
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.2805839272
Short name T111
Test name
Test status
Simulation time 2035725142 ps
CPU time 1.86 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:50:49 PM PDT 24
Peak memory 200952 kb
Host smart-39f4d4aa-d641-4c8b-9fe2-5f8f13f5c8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805839272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.2805839272
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1964359893
Short name T678
Test name
Test status
Simulation time 108075897152 ps
CPU time 68.67 seconds
Started Jul 22 04:52:36 PM PDT 24
Finished Jul 22 04:53:47 PM PDT 24
Peak memory 200884 kb
Host smart-9151cbc1-9fc1-466c-8ed2-3765b2bfc0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964359893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.1
964359893
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.463759302
Short name T260
Test name
Test status
Simulation time 103464850741 ps
CPU time 135.29 seconds
Started Jul 22 04:50:36 PM PDT 24
Finished Jul 22 04:52:52 PM PDT 24
Peak memory 201172 kb
Host smart-ac740391-a40a-468b-aff1-b300b3b0b94a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463759302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_combo_detect.463759302
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3321230444
Short name T26
Test name
Test status
Simulation time 47857990029 ps
CPU time 53.18 seconds
Started Jul 22 04:50:38 PM PDT 24
Finished Jul 22 04:51:31 PM PDT 24
Peak memory 201264 kb
Host smart-8ce29161-53fa-4331-a660-d5dc3d46b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321230444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.3321230444
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2850289627
Short name T579
Test name
Test status
Simulation time 2916568673 ps
CPU time 2.45 seconds
Started Jul 22 04:50:38 PM PDT 24
Finished Jul 22 04:50:41 PM PDT 24
Peak memory 200912 kb
Host smart-64a97846-f4b0-464e-a90e-8841498937df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850289627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.2850289627
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1432269632
Short name T45
Test name
Test status
Simulation time 3855633873 ps
CPU time 5.1 seconds
Started Jul 22 04:50:38 PM PDT 24
Finished Jul 22 04:50:44 PM PDT 24
Peak memory 200952 kb
Host smart-bbd80fa3-08cb-4ff1-8e46-28661795c7ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432269632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1432269632
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.330838316
Short name T729
Test name
Test status
Simulation time 2620056497 ps
CPU time 3.92 seconds
Started Jul 22 04:50:37 PM PDT 24
Finished Jul 22 04:50:41 PM PDT 24
Peak memory 200948 kb
Host smart-958a2753-4ad1-4b44-8cbe-d41628eb43dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330838316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.330838316
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.956645751
Short name T522
Test name
Test status
Simulation time 2479608063 ps
CPU time 6.93 seconds
Started Jul 22 04:50:58 PM PDT 24
Finished Jul 22 04:51:05 PM PDT 24
Peak memory 200968 kb
Host smart-ce06a89b-591d-4efa-b2e3-5a84c93e42a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956645751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.956645751
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.3823878395
Short name T688
Test name
Test status
Simulation time 2104285055 ps
CPU time 3.07 seconds
Started Jul 22 04:50:38 PM PDT 24
Finished Jul 22 04:50:42 PM PDT 24
Peak memory 200868 kb
Host smart-ff7b840c-86cb-4bb4-9f93-40f865e72dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823878395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.3823878395
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1572950480
Short name T219
Test name
Test status
Simulation time 2511600117 ps
CPU time 7.28 seconds
Started Jul 22 04:50:58 PM PDT 24
Finished Jul 22 04:51:06 PM PDT 24
Peak memory 200964 kb
Host smart-f184f938-eb7e-4bec-ac8b-c3d3ca4425ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572950480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.1572950480
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.3676969447
Short name T773
Test name
Test status
Simulation time 2127737205 ps
CPU time 2.39 seconds
Started Jul 22 04:50:38 PM PDT 24
Finished Jul 22 04:50:41 PM PDT 24
Peak memory 200920 kb
Host smart-7d96c8c4-8114-4ce5-8f98-1651b2798019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676969447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3676969447
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.1976492152
Short name T80
Test name
Test status
Simulation time 10945105358 ps
CPU time 30.3 seconds
Started Jul 22 04:50:37 PM PDT 24
Finished Jul 22 04:51:08 PM PDT 24
Peak memory 200924 kb
Host smart-2bdaf6c4-cdc5-4f25-8152-54691715f9bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976492152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.1976492152
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1255592719
Short name T732
Test name
Test status
Simulation time 31926039199 ps
CPU time 40.06 seconds
Started Jul 22 04:50:39 PM PDT 24
Finished Jul 22 04:51:19 PM PDT 24
Peak memory 201428 kb
Host smart-7e6d001e-13c3-42ce-8c1c-139cd695097e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255592719 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.1255592719
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2698257984
Short name T647
Test name
Test status
Simulation time 10257198114 ps
CPU time 8.46 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:51:13 PM PDT 24
Peak memory 201000 kb
Host smart-611e33e5-90b5-4213-8aa4-ce8f9556d02a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698257984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2698257984
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3103404503
Short name T663
Test name
Test status
Simulation time 2030849946 ps
CPU time 1.81 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:50:48 PM PDT 24
Peak memory 200932 kb
Host smart-36c42ac1-4b40-41d1-863c-082baba81854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103404503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3103404503
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3724149470
Short name T549
Test name
Test status
Simulation time 4054466004 ps
CPU time 11.32 seconds
Started Jul 22 04:50:48 PM PDT 24
Finished Jul 22 04:51:00 PM PDT 24
Peak memory 201052 kb
Host smart-83deb639-1ebd-4db5-8c6a-0814535cd72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724149470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.3
724149470
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3177146502
Short name T103
Test name
Test status
Simulation time 3984746391 ps
CPU time 3.31 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:50:49 PM PDT 24
Peak memory 200904 kb
Host smart-8b994627-2d49-4da2-a120-0a5edd724727
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177146502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.3177146502
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.388570331
Short name T539
Test name
Test status
Simulation time 2588306073 ps
CPU time 3.47 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:50:49 PM PDT 24
Peak memory 200924 kb
Host smart-62e4eb9d-2610-4e0b-9d1c-fdaa910b3774
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388570331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctr
l_edge_detect.388570331
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2691394805
Short name T489
Test name
Test status
Simulation time 2637166972 ps
CPU time 2.23 seconds
Started Jul 22 04:50:47 PM PDT 24
Finished Jul 22 04:50:50 PM PDT 24
Peak memory 200956 kb
Host smart-3ef11dc6-b4e5-4655-ae7a-778604fc5879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691394805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2691394805
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.3700583369
Short name T699
Test name
Test status
Simulation time 2481530336 ps
CPU time 2.17 seconds
Started Jul 22 04:52:50 PM PDT 24
Finished Jul 22 04:52:53 PM PDT 24
Peak memory 201012 kb
Host smart-e4783093-f498-4bd2-9673-eb8c315e1880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700583369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.3700583369
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.503836621
Short name T164
Test name
Test status
Simulation time 2259658185 ps
CPU time 1.98 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:50:49 PM PDT 24
Peak memory 200968 kb
Host smart-37cf10d0-4c10-4a05-b05c-88657cce6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503836621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.503836621
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2764009660
Short name T15
Test name
Test status
Simulation time 2517489323 ps
CPU time 3.96 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:50:50 PM PDT 24
Peak memory 200952 kb
Host smart-f839c624-32d1-4ae4-a8ca-ec20cf64b0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764009660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2764009660
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.2244638474
Short name T577
Test name
Test status
Simulation time 2112341447 ps
CPU time 5.51 seconds
Started Jul 22 04:52:50 PM PDT 24
Finished Jul 22 04:52:56 PM PDT 24
Peak memory 200940 kb
Host smart-fca08374-3475-4159-8900-c267eadaec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244638474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2244638474
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.2736735468
Short name T312
Test name
Test status
Simulation time 12180464261 ps
CPU time 30.26 seconds
Started Jul 22 04:52:50 PM PDT 24
Finished Jul 22 04:53:22 PM PDT 24
Peak memory 201208 kb
Host smart-ea3a12f7-b6a2-4f19-8aa3-1b103f6fb28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736735468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.2736735468
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2182018208
Short name T36
Test name
Test status
Simulation time 63537656955 ps
CPU time 39.66 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:51:26 PM PDT 24
Peak memory 209608 kb
Host smart-3c0713fb-6b41-4e31-a4fc-5f04f95732e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182018208 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.2182018208
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.1899237113
Short name T139
Test name
Test status
Simulation time 5261030719 ps
CPU time 1.64 seconds
Started Jul 22 04:51:48 PM PDT 24
Finished Jul 22 04:51:50 PM PDT 24
Peak memory 201008 kb
Host smart-4b5a73d5-d353-42da-a949-c7fbe0fa9d74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899237113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.1899237113
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.2394975945
Short name T396
Test name
Test status
Simulation time 2012056449 ps
CPU time 5.89 seconds
Started Jul 22 04:50:55 PM PDT 24
Finished Jul 22 04:51:01 PM PDT 24
Peak memory 200888 kb
Host smart-47011a39-f903-4240-b35a-d97dcef540b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394975945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.2394975945
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.4016411725
Short name T460
Test name
Test status
Simulation time 3842644405 ps
CPU time 5.34 seconds
Started Jul 22 04:52:30 PM PDT 24
Finished Jul 22 04:52:36 PM PDT 24
Peak memory 201032 kb
Host smart-d905cb09-8f1e-48a7-97f7-ec33bc8d992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016411725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.4
016411725
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.3189659123
Short name T7
Test name
Test status
Simulation time 32197412441 ps
CPU time 23.86 seconds
Started Jul 22 04:50:57 PM PDT 24
Finished Jul 22 04:51:21 PM PDT 24
Peak memory 201136 kb
Host smart-7d896a1d-a2b5-403e-b48f-e53969f63353
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189659123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.3189659123
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2412789463
Short name T368
Test name
Test status
Simulation time 123259651314 ps
CPU time 37.71 seconds
Started Jul 22 04:50:55 PM PDT 24
Finished Jul 22 04:51:34 PM PDT 24
Peak memory 201236 kb
Host smart-59b60fa4-6f95-48a0-8804-f5916d936c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412789463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.2412789463
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2072682197
Short name T736
Test name
Test status
Simulation time 2835048345 ps
CPU time 2.1 seconds
Started Jul 22 04:51:11 PM PDT 24
Finished Jul 22 04:51:13 PM PDT 24
Peak memory 200908 kb
Host smart-b03caaa7-e8e7-407c-91c7-35753e4e2c76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072682197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.2072682197
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3515476572
Short name T144
Test name
Test status
Simulation time 3284069731 ps
CPU time 2.37 seconds
Started Jul 22 04:52:28 PM PDT 24
Finished Jul 22 04:52:30 PM PDT 24
Peak memory 200980 kb
Host smart-cfc93bd5-c067-4e17-b414-5369bc653cec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515476572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.3515476572
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3457920544
Short name T94
Test name
Test status
Simulation time 2608447909 ps
CPU time 7.26 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:50:54 PM PDT 24
Peak memory 200940 kb
Host smart-373770a8-359c-46f0-9090-265b684f7ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457920544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.3457920544
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2278993078
Short name T683
Test name
Test status
Simulation time 2456941599 ps
CPU time 2.47 seconds
Started Jul 22 04:50:49 PM PDT 24
Finished Jul 22 04:50:51 PM PDT 24
Peak memory 200956 kb
Host smart-87f4b14d-2735-4fe0-80f3-4a65b33dac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278993078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2278993078
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2498147702
Short name T322
Test name
Test status
Simulation time 2236724117 ps
CPU time 1.95 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:50:49 PM PDT 24
Peak memory 200912 kb
Host smart-810248db-5b79-4f6e-967c-9d51981ba60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498147702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2498147702
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.608965166
Short name T104
Test name
Test status
Simulation time 2520226577 ps
CPU time 2.22 seconds
Started Jul 22 04:50:45 PM PDT 24
Finished Jul 22 04:50:48 PM PDT 24
Peak memory 201024 kb
Host smart-61ec3289-4f56-48f4-884e-105ea6d4aa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608965166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.608965166
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.3456808380
Short name T554
Test name
Test status
Simulation time 2111462051 ps
CPU time 5.46 seconds
Started Jul 22 04:50:46 PM PDT 24
Finished Jul 22 04:50:52 PM PDT 24
Peak memory 200864 kb
Host smart-2afe402a-42b8-4296-96e7-0ed2a94ac20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456808380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.3456808380
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.1474742916
Short name T373
Test name
Test status
Simulation time 221525188277 ps
CPU time 291.98 seconds
Started Jul 22 04:50:54 PM PDT 24
Finished Jul 22 04:55:47 PM PDT 24
Peak memory 201280 kb
Host smart-6751ec94-cb6d-4894-804f-3e8a7121115f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474742916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.1474742916
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1098149017
Short name T597
Test name
Test status
Simulation time 3631329462 ps
CPU time 1.99 seconds
Started Jul 22 04:51:16 PM PDT 24
Finished Jul 22 04:51:18 PM PDT 24
Peak memory 200912 kb
Host smart-f2b5ac87-0b2e-4578-bc19-8c8e0096cab1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098149017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.1098149017
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.2234703769
Short name T161
Test name
Test status
Simulation time 2030908394 ps
CPU time 1.94 seconds
Started Jul 22 04:51:04 PM PDT 24
Finished Jul 22 04:51:07 PM PDT 24
Peak memory 200940 kb
Host smart-126c3c1f-a910-4c8e-bff0-71f1b8943ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234703769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.2234703769
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.4199335262
Short name T176
Test name
Test status
Simulation time 3228139964 ps
CPU time 5.16 seconds
Started Jul 22 04:50:57 PM PDT 24
Finished Jul 22 04:51:02 PM PDT 24
Peak memory 201004 kb
Host smart-90732438-1a28-4b97-ac25-e6769431369e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199335262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.4
199335262
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2348670159
Short name T754
Test name
Test status
Simulation time 136447399408 ps
CPU time 89.32 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:52:33 PM PDT 24
Peak memory 201228 kb
Host smart-7e435cb9-adbe-40b1-b023-d7dbb6518401
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348670159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.2348670159
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3943530709
Short name T270
Test name
Test status
Simulation time 76289796267 ps
CPU time 49.91 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:51:54 PM PDT 24
Peak memory 201232 kb
Host smart-292231fd-26c2-4084-b9cd-03a6dc3b6604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943530709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.3943530709
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2953111852
Short name T661
Test name
Test status
Simulation time 4107069812 ps
CPU time 6.03 seconds
Started Jul 22 04:50:54 PM PDT 24
Finished Jul 22 04:51:00 PM PDT 24
Peak memory 200924 kb
Host smart-ff90738b-1b0d-4b6a-bb4a-d2c8f7cf362d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953111852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2953111852
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1702583246
Short name T609
Test name
Test status
Simulation time 2611063468 ps
CPU time 7.37 seconds
Started Jul 22 04:52:28 PM PDT 24
Finished Jul 22 04:52:35 PM PDT 24
Peak memory 200952 kb
Host smart-dcb53aac-31ce-4455-9bde-6b6df8f53daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702583246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.1702583246
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.699081640
Short name T521
Test name
Test status
Simulation time 2477442819 ps
CPU time 1.92 seconds
Started Jul 22 04:50:58 PM PDT 24
Finished Jul 22 04:51:01 PM PDT 24
Peak memory 200920 kb
Host smart-c5bf9cbe-d81e-4e00-a161-0a41749640ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699081640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.699081640
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2323148843
Short name T507
Test name
Test status
Simulation time 2103432985 ps
CPU time 3.63 seconds
Started Jul 22 04:50:58 PM PDT 24
Finished Jul 22 04:51:02 PM PDT 24
Peak memory 200852 kb
Host smart-02e939d7-e024-4dc2-b074-1ebb4a67ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323148843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.2323148843
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.1643277587
Short name T584
Test name
Test status
Simulation time 2526897662 ps
CPU time 2.62 seconds
Started Jul 22 04:50:56 PM PDT 24
Finished Jul 22 04:50:59 PM PDT 24
Peak memory 201024 kb
Host smart-154ac12a-c4c0-4f70-a45a-dc3d984c742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643277587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.1643277587
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1537509943
Short name T424
Test name
Test status
Simulation time 2107857150 ps
CPU time 5.9 seconds
Started Jul 22 04:50:56 PM PDT 24
Finished Jul 22 04:51:02 PM PDT 24
Peak memory 200952 kb
Host smart-aeeb6a1d-5fa2-4b35-bce2-d986ca959a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537509943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1537509943
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.3587870376
Short name T619
Test name
Test status
Simulation time 7840516565 ps
CPU time 21.8 seconds
Started Jul 22 04:52:58 PM PDT 24
Finished Jul 22 04:53:21 PM PDT 24
Peak memory 200896 kb
Host smart-cc8c5991-e767-4bf9-8f94-5a2ba168383c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587870376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.3587870376
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3474922082
Short name T388
Test name
Test status
Simulation time 39986386087 ps
CPU time 104.67 seconds
Started Jul 22 04:51:23 PM PDT 24
Finished Jul 22 04:53:08 PM PDT 24
Peak memory 217588 kb
Host smart-14c2e310-d7df-4ed8-80d8-abd2baad7ae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474922082 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3474922082
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3090368040
Short name T138
Test name
Test status
Simulation time 265810825170 ps
CPU time 11.89 seconds
Started Jul 22 04:50:56 PM PDT 24
Finished Jul 22 04:51:08 PM PDT 24
Peak memory 201040 kb
Host smart-27698745-76ca-49b6-a9dd-22d8d43ada66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090368040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.3090368040
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.1795048317
Short name T592
Test name
Test status
Simulation time 2034290579 ps
CPU time 1.77 seconds
Started Jul 22 04:53:21 PM PDT 24
Finished Jul 22 04:53:23 PM PDT 24
Peak memory 200952 kb
Host smart-12b01c24-ebb0-4c59-b6c3-c701148b71ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795048317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.1795048317
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2786646211
Short name T649
Test name
Test status
Simulation time 3509470620 ps
CPU time 5.02 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:51:08 PM PDT 24
Peak memory 200940 kb
Host smart-de3f036a-7225-4afd-b26f-b3f1b3f3022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786646211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2
786646211
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.3281841042
Short name T226
Test name
Test status
Simulation time 85432641263 ps
CPU time 76.2 seconds
Started Jul 22 04:51:04 PM PDT 24
Finished Jul 22 04:52:21 PM PDT 24
Peak memory 201184 kb
Host smart-15b5eac2-e900-4ed3-9739-406e79f45b34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281841042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.3281841042
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.271953652
Short name T249
Test name
Test status
Simulation time 26328750018 ps
CPU time 65.4 seconds
Started Jul 22 04:52:35 PM PDT 24
Finished Jul 22 04:53:41 PM PDT 24
Peak memory 201324 kb
Host smart-8af14987-cbc5-48e3-aec9-8060a6d52b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271953652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_wi
th_pre_cond.271953652
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3852228555
Short name T484
Test name
Test status
Simulation time 3966254197 ps
CPU time 3.05 seconds
Started Jul 22 04:52:31 PM PDT 24
Finished Jul 22 04:52:35 PM PDT 24
Peak memory 200920 kb
Host smart-c3946842-a6f2-4d13-9685-e7973577637b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852228555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.3852228555
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.474751916
Short name T192
Test name
Test status
Simulation time 3506334606 ps
CPU time 2.35 seconds
Started Jul 22 04:51:06 PM PDT 24
Finished Jul 22 04:51:09 PM PDT 24
Peak memory 201016 kb
Host smart-ab624333-d8dc-4708-933f-93789a22aa25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474751916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctr
l_edge_detect.474751916
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3919861801
Short name T449
Test name
Test status
Simulation time 2627238753 ps
CPU time 2.02 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:51:05 PM PDT 24
Peak memory 201024 kb
Host smart-43aba7e4-dd5c-4ad2-808e-ba229395d6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919861801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3919861801
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1744542521
Short name T550
Test name
Test status
Simulation time 2452518659 ps
CPU time 7.88 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:51:11 PM PDT 24
Peak memory 200932 kb
Host smart-28a930ac-5c64-43a6-8ce3-f813e372fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744542521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1744542521
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3338314928
Short name T461
Test name
Test status
Simulation time 2260021800 ps
CPU time 3.81 seconds
Started Jul 22 04:51:07 PM PDT 24
Finished Jul 22 04:51:11 PM PDT 24
Peak memory 201004 kb
Host smart-7465773c-7500-4730-b9ac-214757204fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338314928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3338314928
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2877022561
Short name T596
Test name
Test status
Simulation time 2555380785 ps
CPU time 1.54 seconds
Started Jul 22 04:51:35 PM PDT 24
Finished Jul 22 04:51:37 PM PDT 24
Peak memory 200956 kb
Host smart-fe428a67-f1b9-4dd0-8ca4-619fe21e7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877022561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.2877022561
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.1549143757
Short name T213
Test name
Test status
Simulation time 2128978766 ps
CPU time 1.97 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:51:05 PM PDT 24
Peak memory 200948 kb
Host smart-43a8a57e-3618-471d-ac70-91de5dfcd0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549143757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1549143757
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.956712551
Short name T473
Test name
Test status
Simulation time 189734592430 ps
CPU time 461.85 seconds
Started Jul 22 04:51:07 PM PDT 24
Finished Jul 22 04:58:49 PM PDT 24
Peak memory 201064 kb
Host smart-d08e873b-f5da-4c75-9bc1-80189229474c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956712551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.956712551
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3481539531
Short name T40
Test name
Test status
Simulation time 39766859289 ps
CPU time 24.12 seconds
Started Jul 22 04:52:01 PM PDT 24
Finished Jul 22 04:52:26 PM PDT 24
Peak memory 209640 kb
Host smart-61189ee3-e20d-4fa8-90be-cfa1ff27cb8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481539531 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3481539531
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2218591318
Short name T119
Test name
Test status
Simulation time 5187684011 ps
CPU time 3.8 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:51:08 PM PDT 24
Peak memory 200940 kb
Host smart-64ea2513-e9a1-4b74-a524-de8d69c59f1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218591318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.2218591318
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.370958727
Short name T591
Test name
Test status
Simulation time 2015796046 ps
CPU time 5.68 seconds
Started Jul 22 04:53:11 PM PDT 24
Finished Jul 22 04:53:18 PM PDT 24
Peak memory 201024 kb
Host smart-d9d91eb8-7c6f-4ac2-a75b-9357cd4f8f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370958727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_tes
t.370958727
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1247311336
Short name T479
Test name
Test status
Simulation time 3379211491 ps
CPU time 1.1 seconds
Started Jul 22 04:51:13 PM PDT 24
Finished Jul 22 04:51:14 PM PDT 24
Peak memory 201088 kb
Host smart-6520ca66-10ef-4507-9fe1-e14ac14c2ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247311336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1
247311336
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3808047617
Short name T82
Test name
Test status
Simulation time 67727104558 ps
CPU time 50.67 seconds
Started Jul 22 04:51:14 PM PDT 24
Finished Jul 22 04:52:05 PM PDT 24
Peak memory 201168 kb
Host smart-9484e7a3-ace2-4c06-8c93-f8a0aa7d440d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808047617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.3808047617
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1964629810
Short name T245
Test name
Test status
Simulation time 23328702848 ps
CPU time 60.73 seconds
Started Jul 22 04:51:14 PM PDT 24
Finished Jul 22 04:52:16 PM PDT 24
Peak memory 201224 kb
Host smart-681fe629-4845-44df-96d8-82918e72ba94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964629810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1964629810
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2822767752
Short name T440
Test name
Test status
Simulation time 3566841456 ps
CPU time 5.08 seconds
Started Jul 22 04:51:13 PM PDT 24
Finished Jul 22 04:51:18 PM PDT 24
Peak memory 200944 kb
Host smart-ab6402a4-cc1c-4680-8643-9c0c4b9f3732
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822767752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.2822767752
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.662114090
Short name T3
Test name
Test status
Simulation time 4159635682 ps
CPU time 10.23 seconds
Started Jul 22 04:51:14 PM PDT 24
Finished Jul 22 04:51:25 PM PDT 24
Peak memory 201008 kb
Host smart-f588d30f-d127-42b8-bf7e-6c3dcba1191b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662114090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.662114090
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2766728979
Short name T406
Test name
Test status
Simulation time 2629028911 ps
CPU time 2.62 seconds
Started Jul 22 04:51:14 PM PDT 24
Finished Jul 22 04:51:17 PM PDT 24
Peak memory 200952 kb
Host smart-bff891a6-c0e9-43d7-852e-c039038fdee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766728979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.2766728979
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.325107729
Short name T628
Test name
Test status
Simulation time 2488783075 ps
CPU time 1.95 seconds
Started Jul 22 04:51:04 PM PDT 24
Finished Jul 22 04:51:06 PM PDT 24
Peak memory 200952 kb
Host smart-e564f0f7-07ca-4820-8dab-154ce0adb7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325107729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.325107729
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.530205747
Short name T451
Test name
Test status
Simulation time 2251352840 ps
CPU time 6.55 seconds
Started Jul 22 04:52:44 PM PDT 24
Finished Jul 22 04:52:52 PM PDT 24
Peak memory 200940 kb
Host smart-dbafc1d2-8722-45c4-9a1e-1ef30972c82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530205747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.530205747
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.352293906
Short name T527
Test name
Test status
Simulation time 2512352370 ps
CPU time 7.01 seconds
Started Jul 22 04:51:13 PM PDT 24
Finished Jul 22 04:51:20 PM PDT 24
Peak memory 200956 kb
Host smart-0d8b0e04-08a0-43d8-bb51-96686d7c41e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352293906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.352293906
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.2192649116
Short name T99
Test name
Test status
Simulation time 2114622857 ps
CPU time 5.73 seconds
Started Jul 22 04:51:03 PM PDT 24
Finished Jul 22 04:51:09 PM PDT 24
Peak memory 200764 kb
Host smart-4f3c63a2-b3bf-4b45-9f99-10cbfd00255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192649116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.2192649116
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.2280175936
Short name T587
Test name
Test status
Simulation time 9432351782 ps
CPU time 3.03 seconds
Started Jul 22 04:51:16 PM PDT 24
Finished Jul 22 04:51:19 PM PDT 24
Peak memory 200924 kb
Host smart-0d4a0b9b-af1c-4f50-aed3-dae12107ff2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280175936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.2280175936
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2801778530
Short name T93
Test name
Test status
Simulation time 68590553589 ps
CPU time 83.61 seconds
Started Jul 22 04:51:13 PM PDT 24
Finished Jul 22 04:52:38 PM PDT 24
Peak memory 209496 kb
Host smart-906568f0-33ab-4d1f-a08a-0b77623f19a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801778530 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2801778530
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2318692676
Short name T770
Test name
Test status
Simulation time 3778301944 ps
CPU time 1.23 seconds
Started Jul 22 04:51:27 PM PDT 24
Finished Jul 22 04:51:29 PM PDT 24
Peak memory 200920 kb
Host smart-c4220273-2b1b-4c36-901e-1512df8aeffa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318692676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.2318692676
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.1111967320
Short name T664
Test name
Test status
Simulation time 2081996725 ps
CPU time 1.17 seconds
Started Jul 22 04:48:23 PM PDT 24
Finished Jul 22 04:48:25 PM PDT 24
Peak memory 200928 kb
Host smart-05b2a392-28fa-4572-a8e1-596c2c391aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111967320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.1111967320
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.705673002
Short name T559
Test name
Test status
Simulation time 3423438642 ps
CPU time 9.78 seconds
Started Jul 22 04:48:32 PM PDT 24
Finished Jul 22 04:48:42 PM PDT 24
Peak memory 200968 kb
Host smart-c290b8aa-db6b-48e1-88f5-a5888e9f288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705673002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.705673002
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.2135572461
Short name T768
Test name
Test status
Simulation time 124075590089 ps
CPU time 73.5 seconds
Started Jul 22 04:48:18 PM PDT 24
Finished Jul 22 04:49:32 PM PDT 24
Peak memory 201080 kb
Host smart-c7476ad7-ae36-4cfe-a41e-47739402ee7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135572461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.2135572461
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1961381768
Short name T470
Test name
Test status
Simulation time 2138403972 ps
CPU time 5.83 seconds
Started Jul 22 04:48:18 PM PDT 24
Finished Jul 22 04:48:24 PM PDT 24
Peak memory 200960 kb
Host smart-33b94be4-afd1-4a7d-8041-ed05ef734a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961381768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.1961381768
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2886986457
Short name T71
Test name
Test status
Simulation time 2502518035 ps
CPU time 7.53 seconds
Started Jul 22 04:48:19 PM PDT 24
Finished Jul 22 04:48:27 PM PDT 24
Peak memory 200928 kb
Host smart-8afa7000-2106-447c-8b0d-601a3f54f2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886986457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2886986457
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2078083770
Short name T681
Test name
Test status
Simulation time 53295511752 ps
CPU time 23.37 seconds
Started Jul 22 04:48:20 PM PDT 24
Finished Jul 22 04:48:44 PM PDT 24
Peak memory 201304 kb
Host smart-db8534dc-d27d-49c4-878e-f3bab28a4058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078083770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.2078083770
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3649380012
Short name T16
Test name
Test status
Simulation time 4817692612 ps
CPU time 6.44 seconds
Started Jul 22 04:48:19 PM PDT 24
Finished Jul 22 04:48:25 PM PDT 24
Peak memory 200880 kb
Host smart-b6014103-3445-4456-8c9f-6a3ca4924bd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649380012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.3649380012
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2528152198
Short name T165
Test name
Test status
Simulation time 3065967361 ps
CPU time 7.51 seconds
Started Jul 22 04:48:39 PM PDT 24
Finished Jul 22 04:48:48 PM PDT 24
Peak memory 200952 kb
Host smart-ae657a62-7f04-4bb7-8d3b-1c5780b8c587
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528152198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.2528152198
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3499997519
Short name T68
Test name
Test status
Simulation time 2629390888 ps
CPU time 2.27 seconds
Started Jul 22 04:48:19 PM PDT 24
Finished Jul 22 04:48:22 PM PDT 24
Peak memory 200940 kb
Host smart-5f0701a5-028e-451d-a1cb-401d82b2742f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499997519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3499997519
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2586526403
Short name T66
Test name
Test status
Simulation time 2460357805 ps
CPU time 3.96 seconds
Started Jul 22 04:48:17 PM PDT 24
Finished Jul 22 04:48:22 PM PDT 24
Peak memory 200936 kb
Host smart-b079a580-ff40-452c-94df-5ede74462522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586526403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.2586526403
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1861202413
Short name T774
Test name
Test status
Simulation time 2126700430 ps
CPU time 6.09 seconds
Started Jul 22 04:48:18 PM PDT 24
Finished Jul 22 04:48:25 PM PDT 24
Peak memory 200864 kb
Host smart-b55bf4c9-a0a3-4732-bab9-971a86f75039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861202413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1861202413
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2676354252
Short name T745
Test name
Test status
Simulation time 2512560170 ps
CPU time 7.38 seconds
Started Jul 22 04:48:22 PM PDT 24
Finished Jul 22 04:48:30 PM PDT 24
Peak memory 200904 kb
Host smart-a00c343d-1e9d-42fb-96fa-6bd54246c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676354252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.2676354252
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2048514027
Short name T296
Test name
Test status
Simulation time 22065976468 ps
CPU time 45.71 seconds
Started Jul 22 04:48:19 PM PDT 24
Finished Jul 22 04:49:06 PM PDT 24
Peak memory 220620 kb
Host smart-520a6ee3-bd36-4321-8718-abcf83e91e95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048514027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.2048514027
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.3620761399
Short name T212
Test name
Test status
Simulation time 2131325031 ps
CPU time 2.04 seconds
Started Jul 22 04:48:20 PM PDT 24
Finished Jul 22 04:48:23 PM PDT 24
Peak memory 200876 kb
Host smart-85cc5f25-523e-450c-bc5d-fe7529c5ca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620761399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3620761399
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.156564361
Short name T130
Test name
Test status
Simulation time 14325154309 ps
CPU time 28.99 seconds
Started Jul 22 04:48:21 PM PDT 24
Finished Jul 22 04:48:51 PM PDT 24
Peak memory 200992 kb
Host smart-274d6ef0-ff74-45b0-a20b-347fe9d17336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156564361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_str
ess_all.156564361
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.214071723
Short name T463
Test name
Test status
Simulation time 4033516408 ps
CPU time 5.27 seconds
Started Jul 22 04:48:18 PM PDT 24
Finished Jul 22 04:48:23 PM PDT 24
Peak memory 201028 kb
Host smart-d2a46b21-685c-48f0-b306-40f5ae2a7d15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214071723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ultra_low_pwr.214071723
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.159518307
Short name T665
Test name
Test status
Simulation time 2012450490 ps
CPU time 5.62 seconds
Started Jul 22 04:53:01 PM PDT 24
Finished Jul 22 04:53:07 PM PDT 24
Peak memory 200936 kb
Host smart-2e3ea005-de01-4a06-af4b-b01436f33e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159518307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.159518307
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2695268494
Short name T738
Test name
Test status
Simulation time 3352509876 ps
CPU time 2.81 seconds
Started Jul 22 04:52:59 PM PDT 24
Finished Jul 22 04:53:02 PM PDT 24
Peak memory 201004 kb
Host smart-8d53a934-963b-4700-82cd-d6b2513b749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695268494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.2
695268494
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.568257633
Short name T56
Test name
Test status
Simulation time 3145427827 ps
CPU time 2.4 seconds
Started Jul 22 04:54:06 PM PDT 24
Finished Jul 22 04:54:08 PM PDT 24
Peak memory 200892 kb
Host smart-68d8c798-d7b9-413f-a71b-10a441abe5ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568257633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ec_pwr_on_rst.568257633
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.1513980856
Short name T190
Test name
Test status
Simulation time 2870596425 ps
CPU time 6.91 seconds
Started Jul 22 04:51:17 PM PDT 24
Finished Jul 22 04:51:24 PM PDT 24
Peak memory 200908 kb
Host smart-b807a9e5-e1a6-4cf7-9aa9-694491b4022c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513980856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.1513980856
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2533489615
Short name T545
Test name
Test status
Simulation time 2609401840 ps
CPU time 7.25 seconds
Started Jul 22 04:51:15 PM PDT 24
Finished Jul 22 04:51:23 PM PDT 24
Peak memory 200920 kb
Host smart-35c0b3bb-baa9-4a18-b3bb-62f256431536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533489615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.2533489615
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3112387840
Short name T67
Test name
Test status
Simulation time 2464471312 ps
CPU time 3.94 seconds
Started Jul 22 04:51:15 PM PDT 24
Finished Jul 22 04:51:20 PM PDT 24
Peak memory 200940 kb
Host smart-d8d8ad4f-5686-4bb3-a464-611dd21458a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112387840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3112387840
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3219437344
Short name T482
Test name
Test status
Simulation time 2227516719 ps
CPU time 1.73 seconds
Started Jul 22 04:51:13 PM PDT 24
Finished Jul 22 04:51:16 PM PDT 24
Peak memory 201304 kb
Host smart-fd8f6ef2-7332-4d6a-b607-13c5e8bcc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219437344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.3219437344
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2502955265
Short name T204
Test name
Test status
Simulation time 2557726143 ps
CPU time 1.43 seconds
Started Jul 22 04:51:16 PM PDT 24
Finished Jul 22 04:51:18 PM PDT 24
Peak memory 201024 kb
Host smart-c78ffc80-503a-40b2-abfb-cd90d9a2ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502955265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2502955265
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.4122597171
Short name T160
Test name
Test status
Simulation time 2114460044 ps
CPU time 5 seconds
Started Jul 22 04:51:24 PM PDT 24
Finished Jul 22 04:51:29 PM PDT 24
Peak memory 200904 kb
Host smart-fccce899-79e3-4c4c-97df-9da1e4c6c01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122597171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.4122597171
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.1049062857
Short name T648
Test name
Test status
Simulation time 15718771818 ps
CPU time 7.72 seconds
Started Jul 22 04:51:16 PM PDT 24
Finished Jul 22 04:51:25 PM PDT 24
Peak memory 200908 kb
Host smart-dfc78536-f7c2-44ef-b2fb-69d326d69b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049062857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.1049062857
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1976493348
Short name T471
Test name
Test status
Simulation time 7069745976 ps
CPU time 1.44 seconds
Started Jul 22 04:51:16 PM PDT 24
Finished Jul 22 04:51:18 PM PDT 24
Peak memory 201032 kb
Host smart-a3bdae0b-9b86-4197-93d8-b1f0305d659c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976493348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.1976493348
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.279591769
Short name T538
Test name
Test status
Simulation time 2089055697 ps
CPU time 1.05 seconds
Started Jul 22 04:53:08 PM PDT 24
Finished Jul 22 04:53:09 PM PDT 24
Peak memory 201000 kb
Host smart-a00ef48b-4cd8-4a62-bb99-781ce5c4b5d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279591769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_tes
t.279591769
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.4246801390
Short name T632
Test name
Test status
Simulation time 3085007068 ps
CPU time 2.58 seconds
Started Jul 22 04:51:14 PM PDT 24
Finished Jul 22 04:51:17 PM PDT 24
Peak memory 201084 kb
Host smart-c78bc646-784b-499d-865f-4308b181e873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246801390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.4
246801390
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.2737467402
Short name T714
Test name
Test status
Simulation time 44353433731 ps
CPU time 31.4 seconds
Started Jul 22 04:52:38 PM PDT 24
Finished Jul 22 04:53:10 PM PDT 24
Peak memory 201208 kb
Host smart-2a92d335-7108-4e1a-8831-c507aada89de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737467402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.2737467402
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1760104914
Short name T585
Test name
Test status
Simulation time 22602954753 ps
CPU time 16 seconds
Started Jul 22 04:51:17 PM PDT 24
Finished Jul 22 04:51:34 PM PDT 24
Peak memory 201376 kb
Host smart-87b53985-1de6-46fd-b2d8-8325ceb75f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760104914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1760104914
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1138666484
Short name T439
Test name
Test status
Simulation time 3094679960 ps
CPU time 1.18 seconds
Started Jul 22 04:51:14 PM PDT 24
Finished Jul 22 04:51:16 PM PDT 24
Peak memory 201004 kb
Host smart-4ab094f8-84dd-4b78-8fa7-2ef6d44a45ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138666484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.1138666484
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3102960314
Short name T677
Test name
Test status
Simulation time 3018268445 ps
CPU time 2.3 seconds
Started Jul 22 04:53:18 PM PDT 24
Finished Jul 22 04:53:21 PM PDT 24
Peak memory 200984 kb
Host smart-8909b46a-8b01-44c2-af62-c7300bb29e38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102960314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.3102960314
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.4074325216
Short name T562
Test name
Test status
Simulation time 2614261184 ps
CPU time 7.7 seconds
Started Jul 22 04:51:20 PM PDT 24
Finished Jul 22 04:51:28 PM PDT 24
Peak memory 201024 kb
Host smart-45de57d5-b5ab-4a47-bf4c-7390f19b01e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074325216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.4074325216
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.485752698
Short name T680
Test name
Test status
Simulation time 2506038112 ps
CPU time 1.63 seconds
Started Jul 22 04:51:17 PM PDT 24
Finished Jul 22 04:51:19 PM PDT 24
Peak memory 200880 kb
Host smart-274deade-9c9f-4502-9df3-2e16070ed7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485752698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.485752698
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1098139169
Short name T642
Test name
Test status
Simulation time 2204682330 ps
CPU time 3.49 seconds
Started Jul 22 04:52:27 PM PDT 24
Finished Jul 22 04:52:31 PM PDT 24
Peak memory 200904 kb
Host smart-fd5566d9-4787-46a8-91cc-82f9f7f609e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098139169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1098139169
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2597607194
Short name T588
Test name
Test status
Simulation time 2513056717 ps
CPU time 3.96 seconds
Started Jul 22 04:51:16 PM PDT 24
Finished Jul 22 04:51:21 PM PDT 24
Peak memory 200876 kb
Host smart-b37b300f-517e-46cd-ab1c-171dc63c076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597607194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2597607194
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.3399296913
Short name T513
Test name
Test status
Simulation time 2109597376 ps
CPU time 5.48 seconds
Started Jul 22 04:51:15 PM PDT 24
Finished Jul 22 04:51:21 PM PDT 24
Peak memory 200880 kb
Host smart-5ed44a4e-f83e-4127-aeb3-1cd004f2aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399296913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3399296913
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.684966181
Short name T633
Test name
Test status
Simulation time 94064093402 ps
CPU time 123.43 seconds
Started Jul 22 04:51:25 PM PDT 24
Finished Jul 22 04:53:29 PM PDT 24
Peak memory 201208 kb
Host smart-f83e5212-af5f-431f-a44a-feb082bad885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684966181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.684966181
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2637027445
Short name T303
Test name
Test status
Simulation time 121206364033 ps
CPU time 39.65 seconds
Started Jul 22 04:51:22 PM PDT 24
Finished Jul 22 04:52:02 PM PDT 24
Peak memory 217392 kb
Host smart-8e648243-c75e-4ad7-950f-a255f240e307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637027445 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2637027445
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3442177898
Short name T586
Test name
Test status
Simulation time 4134876357 ps
CPU time 2.21 seconds
Started Jul 22 04:53:18 PM PDT 24
Finished Jul 22 04:53:21 PM PDT 24
Peak memory 200972 kb
Host smart-0ef594d4-8832-4b59-bff6-3de606ea845d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442177898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.3442177898
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.1065116403
Short name T733
Test name
Test status
Simulation time 2038649902 ps
CPU time 1.87 seconds
Started Jul 22 04:51:23 PM PDT 24
Finished Jul 22 04:51:25 PM PDT 24
Peak memory 200952 kb
Host smart-f07801f8-dc62-41f5-b12c-20f30a272ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065116403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.1065116403
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3963231634
Short name T434
Test name
Test status
Simulation time 3062470961 ps
CPU time 8.12 seconds
Started Jul 22 04:52:32 PM PDT 24
Finished Jul 22 04:52:40 PM PDT 24
Peak memory 201044 kb
Host smart-3815e0d3-8c7a-4732-9bf2-5495cd9d7b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963231634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3
963231634
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.3800450608
Short name T272
Test name
Test status
Simulation time 61096065892 ps
CPU time 19.45 seconds
Started Jul 22 04:51:22 PM PDT 24
Finished Jul 22 04:51:42 PM PDT 24
Peak memory 201148 kb
Host smart-c7aad7ea-3404-462b-9d74-a64cc247d178
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800450608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.3800450608
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3856119123
Short name T669
Test name
Test status
Simulation time 46834284261 ps
CPU time 122.12 seconds
Started Jul 22 04:51:26 PM PDT 24
Finished Jul 22 04:53:29 PM PDT 24
Peak memory 201384 kb
Host smart-b298223f-1e42-4faf-bcbf-db0f6e4a477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856119123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.3856119123
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1581612450
Short name T492
Test name
Test status
Simulation time 4720748864 ps
CPU time 6.22 seconds
Started Jul 22 04:54:59 PM PDT 24
Finished Jul 22 04:55:06 PM PDT 24
Peak memory 199828 kb
Host smart-c7cfe6bb-0a8f-4793-ae5a-7f2b53fa97ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581612450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.1581612450
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.2572545334
Short name T41
Test name
Test status
Simulation time 4091391837 ps
CPU time 5.29 seconds
Started Jul 22 04:51:22 PM PDT 24
Finished Jul 22 04:51:27 PM PDT 24
Peak memory 201036 kb
Host smart-fee2c980-d6dd-4b97-b44f-6c07c769ff40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572545334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.2572545334
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2565155587
Short name T69
Test name
Test status
Simulation time 2609925850 ps
CPU time 7.1 seconds
Started Jul 22 04:51:22 PM PDT 24
Finished Jul 22 04:51:30 PM PDT 24
Peak memory 200964 kb
Host smart-d0e4e8fb-58fd-47ee-bab0-6f9be48c60e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565155587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.2565155587
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3771513955
Short name T441
Test name
Test status
Simulation time 2472705527 ps
CPU time 3.72 seconds
Started Jul 22 04:51:35 PM PDT 24
Finished Jul 22 04:51:39 PM PDT 24
Peak memory 200944 kb
Host smart-e7f20e31-9c4e-4e82-a8e6-2cc72a09a707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771513955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.3771513955
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.578942360
Short name T719
Test name
Test status
Simulation time 2208140315 ps
CPU time 3.6 seconds
Started Jul 22 04:51:27 PM PDT 24
Finished Jul 22 04:51:31 PM PDT 24
Peak memory 200996 kb
Host smart-34b8cd3a-cfa5-4f71-8a1e-ec9bff001f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578942360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.578942360
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1267797640
Short name T528
Test name
Test status
Simulation time 2510791023 ps
CPU time 5.47 seconds
Started Jul 22 04:51:21 PM PDT 24
Finished Jul 22 04:51:27 PM PDT 24
Peak memory 200948 kb
Host smart-a9d1d953-f6a2-4f02-8bb8-576099fb1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267797640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.1267797640
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.2883704209
Short name T668
Test name
Test status
Simulation time 2134023764 ps
CPU time 1.98 seconds
Started Jul 22 04:51:22 PM PDT 24
Finished Jul 22 04:51:24 PM PDT 24
Peak memory 200888 kb
Host smart-2b92fc90-40e5-4785-99f2-c5125dad418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883704209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2883704209
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.46339770
Short name T142
Test name
Test status
Simulation time 14203888284 ps
CPU time 32.8 seconds
Started Jul 22 04:51:59 PM PDT 24
Finished Jul 22 04:52:33 PM PDT 24
Peak memory 200968 kb
Host smart-736874fc-6dcc-4dbd-bb66-2a80c13c93c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46339770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_str
ess_all.46339770
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2698565658
Short name T38
Test name
Test status
Simulation time 49993361016 ps
CPU time 116.73 seconds
Started Jul 22 04:51:20 PM PDT 24
Finished Jul 22 04:53:17 PM PDT 24
Peak memory 217708 kb
Host smart-cfa98d6d-de0c-4480-ada9-2ae0f25a20ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698565658 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2698565658
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.4266223261
Short name T564
Test name
Test status
Simulation time 5168588048 ps
CPU time 7.34 seconds
Started Jul 22 04:52:39 PM PDT 24
Finished Jul 22 04:52:47 PM PDT 24
Peak memory 200988 kb
Host smart-dc1eb1a8-efd5-4495-9617-08de6a177f7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266223261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.4266223261
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.352417977
Short name T175
Test name
Test status
Simulation time 2022954941 ps
CPU time 3.33 seconds
Started Jul 22 04:51:34 PM PDT 24
Finished Jul 22 04:51:38 PM PDT 24
Peak memory 200940 kb
Host smart-151d8de2-3196-4f90-bcf9-456eca09f60c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352417977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_tes
t.352417977
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.822907137
Short name T184
Test name
Test status
Simulation time 3286681146 ps
CPU time 2.76 seconds
Started Jul 22 04:51:25 PM PDT 24
Finished Jul 22 04:51:28 PM PDT 24
Peak memory 201088 kb
Host smart-89d0a129-f2b0-4d0f-a93f-a910296cc3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822907137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.822907137
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.67159951
Short name T259
Test name
Test status
Simulation time 124246496602 ps
CPU time 307.23 seconds
Started Jul 22 04:51:27 PM PDT 24
Finished Jul 22 04:56:34 PM PDT 24
Peak memory 201232 kb
Host smart-6d0a3b51-fe17-4bf9-b74e-9352802055d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67159951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctr
l_combo_detect.67159951
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3479068430
Short name T233
Test name
Test status
Simulation time 5063753901 ps
CPU time 3.37 seconds
Started Jul 22 04:51:23 PM PDT 24
Finished Jul 22 04:51:27 PM PDT 24
Peak memory 200968 kb
Host smart-09d8fc27-1871-4f9a-ba0d-f39cad349425
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479068430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.3479068430
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.1350105760
Short name T191
Test name
Test status
Simulation time 4956944569 ps
CPU time 11.3 seconds
Started Jul 22 04:51:34 PM PDT 24
Finished Jul 22 04:51:46 PM PDT 24
Peak memory 200932 kb
Host smart-3a1cba19-9a1a-44a6-8340-39046088f6cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350105760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.1350105760
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4248259423
Short name T450
Test name
Test status
Simulation time 2629481632 ps
CPU time 2.24 seconds
Started Jul 22 04:51:22 PM PDT 24
Finished Jul 22 04:51:25 PM PDT 24
Peak memory 200952 kb
Host smart-65893308-1cbd-4b8f-a7b6-7a8df980e2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248259423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.4248259423
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1514962529
Short name T454
Test name
Test status
Simulation time 2457618228 ps
CPU time 7.67 seconds
Started Jul 22 04:51:24 PM PDT 24
Finished Jul 22 04:51:32 PM PDT 24
Peak memory 200980 kb
Host smart-24e87d7d-ca9e-4735-b4db-c205b4f27fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514962529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.1514962529
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.4219533684
Short name T252
Test name
Test status
Simulation time 2247961470 ps
CPU time 2.01 seconds
Started Jul 22 04:52:30 PM PDT 24
Finished Jul 22 04:52:33 PM PDT 24
Peak memory 200904 kb
Host smart-9c2d287e-5e9b-44c7-93dc-266884fcb36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219533684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.4219533684
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1075577052
Short name T547
Test name
Test status
Simulation time 2512418920 ps
CPU time 7.2 seconds
Started Jul 22 04:51:21 PM PDT 24
Finished Jul 22 04:51:29 PM PDT 24
Peak memory 200968 kb
Host smart-e8c8f471-67cc-4078-a930-54e926555d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075577052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1075577052
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.656265470
Short name T198
Test name
Test status
Simulation time 2112005462 ps
CPU time 5.77 seconds
Started Jul 22 04:51:25 PM PDT 24
Finished Jul 22 04:51:31 PM PDT 24
Peak memory 200948 kb
Host smart-dd62d94a-0442-4356-9116-66233a53d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656265470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.656265470
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.1181044540
Short name T662
Test name
Test status
Simulation time 15554834236 ps
CPU time 29.71 seconds
Started Jul 22 04:51:36 PM PDT 24
Finished Jul 22 04:52:06 PM PDT 24
Peak memory 200888 kb
Host smart-9639d5c6-3c98-4166-abc7-93bf22913e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181044540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.1181044540
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4114861099
Short name T318
Test name
Test status
Simulation time 85289865746 ps
CPU time 51.48 seconds
Started Jul 22 04:51:45 PM PDT 24
Finished Jul 22 04:52:37 PM PDT 24
Peak memory 215184 kb
Host smart-ceb02a58-f7a0-4f2e-aa02-b832e47e0148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114861099 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.4114861099
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.28281515
Short name T117
Test name
Test status
Simulation time 7083822020 ps
CPU time 2.19 seconds
Started Jul 22 04:51:23 PM PDT 24
Finished Jul 22 04:51:26 PM PDT 24
Peak memory 200952 kb
Host smart-af5c83d1-6aec-47c4-bd68-f9c70bfe6673
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28281515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_ultra_low_pwr.28281515
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2679428868
Short name T400
Test name
Test status
Simulation time 2033966402 ps
CPU time 1.95 seconds
Started Jul 22 04:51:33 PM PDT 24
Finished Jul 22 04:51:36 PM PDT 24
Peak memory 200920 kb
Host smart-ab31dba0-6ccd-437a-94ec-03c12ab41eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679428868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2679428868
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1605416238
Short name T92
Test name
Test status
Simulation time 3292063636 ps
CPU time 2.76 seconds
Started Jul 22 04:51:43 PM PDT 24
Finished Jul 22 04:51:47 PM PDT 24
Peak memory 201028 kb
Host smart-b08d60f5-dead-4209-bc4b-d15c355709bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605416238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.1
605416238
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.3565762790
Short name T222
Test name
Test status
Simulation time 179108653770 ps
CPU time 102.93 seconds
Started Jul 22 04:54:59 PM PDT 24
Finished Jul 22 04:56:45 PM PDT 24
Peak memory 200164 kb
Host smart-d06214d7-62af-4abf-8fd4-c80acfdc8040
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565762790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.3565762790
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1827679915
Short name T264
Test name
Test status
Simulation time 24584462137 ps
CPU time 28.95 seconds
Started Jul 22 04:54:58 PM PDT 24
Finished Jul 22 04:55:28 PM PDT 24
Peak memory 201236 kb
Host smart-1ce9c5af-451c-4716-8a94-f22f73398983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827679915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.1827679915
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2756923620
Short name T408
Test name
Test status
Simulation time 2760137279 ps
CPU time 4.05 seconds
Started Jul 22 04:53:21 PM PDT 24
Finished Jul 22 04:53:26 PM PDT 24
Peak memory 200996 kb
Host smart-7aa4d051-f0c8-4f6b-b753-9feeba531e16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756923620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.2756923620
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.835098430
Short name T608
Test name
Test status
Simulation time 4972138616 ps
CPU time 7.85 seconds
Started Jul 22 04:51:42 PM PDT 24
Finished Jul 22 04:51:50 PM PDT 24
Peak memory 200920 kb
Host smart-e8a893e3-7a0b-4e32-b065-36c51976e079
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835098430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctr
l_edge_detect.835098430
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2137914920
Short name T19
Test name
Test status
Simulation time 2640853635 ps
CPU time 1.61 seconds
Started Jul 22 04:51:33 PM PDT 24
Finished Jul 22 04:51:35 PM PDT 24
Peak memory 200940 kb
Host smart-f09b735c-569f-4255-90b2-89043c6de845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137914920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2137914920
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.790677564
Short name T750
Test name
Test status
Simulation time 2443561294 ps
CPU time 4.01 seconds
Started Jul 22 04:51:34 PM PDT 24
Finished Jul 22 04:51:39 PM PDT 24
Peak memory 200948 kb
Host smart-1afcc300-a2cb-4972-a505-4b2c8a0c6c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790677564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.790677564
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1984612279
Short name T623
Test name
Test status
Simulation time 2205658525 ps
CPU time 6.05 seconds
Started Jul 22 04:51:35 PM PDT 24
Finished Jul 22 04:51:42 PM PDT 24
Peak memory 200932 kb
Host smart-f69c3bc4-dcf7-429b-be38-82e74f318629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984612279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.1984612279
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3070743381
Short name T218
Test name
Test status
Simulation time 2519691938 ps
CPU time 3.9 seconds
Started Jul 22 04:51:35 PM PDT 24
Finished Jul 22 04:51:40 PM PDT 24
Peak memory 200940 kb
Host smart-94301caf-e9a2-4e80-8de5-1153a952919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070743381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3070743381
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.1723699295
Short name T309
Test name
Test status
Simulation time 2114792234 ps
CPU time 5.82 seconds
Started Jul 22 04:51:34 PM PDT 24
Finished Jul 22 04:51:41 PM PDT 24
Peak memory 200912 kb
Host smart-f32b0e00-1e42-4e61-9447-a142dfc7142d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723699295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.1723699295
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2789508012
Short name T348
Test name
Test status
Simulation time 157060344080 ps
CPU time 419.42 seconds
Started Jul 22 04:51:34 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 201260 kb
Host smart-e58d9763-eaf4-43d8-8331-f2d38081c1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789508012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2789508012
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2996725930
Short name T546
Test name
Test status
Simulation time 2779530229 ps
CPU time 5.84 seconds
Started Jul 22 04:51:34 PM PDT 24
Finished Jul 22 04:51:41 PM PDT 24
Peak memory 200912 kb
Host smart-c239408d-a543-4c60-bebb-3d4c63693380
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996725930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.2996725930
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.397690624
Short name T536
Test name
Test status
Simulation time 2009608675 ps
CPU time 5.66 seconds
Started Jul 22 04:51:47 PM PDT 24
Finished Jul 22 04:51:53 PM PDT 24
Peak memory 200936 kb
Host smart-6555c87e-64d0-4db1-bd55-1c6a491e47c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397690624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_tes
t.397690624
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.190757867
Short name T756
Test name
Test status
Simulation time 3472600811 ps
CPU time 1.12 seconds
Started Jul 22 04:51:36 PM PDT 24
Finished Jul 22 04:51:38 PM PDT 24
Peak memory 200968 kb
Host smart-311bbdae-2692-4a6b-8a30-1b36b1db6895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190757867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.190757867
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.1055493798
Short name T382
Test name
Test status
Simulation time 153243561916 ps
CPU time 383.62 seconds
Started Jul 22 04:51:45 PM PDT 24
Finished Jul 22 04:58:09 PM PDT 24
Peak memory 201200 kb
Host smart-5c57ab25-3acf-403b-8df0-46de1ec48a87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055493798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.1055493798
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3586653405
Short name T263
Test name
Test status
Simulation time 26334567783 ps
CPU time 68.24 seconds
Started Jul 22 04:52:50 PM PDT 24
Finished Jul 22 04:53:59 PM PDT 24
Peak memory 201292 kb
Host smart-400ca1bb-15cc-4b27-97b6-c1d7107fe77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586653405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.3586653405
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2840381894
Short name T401
Test name
Test status
Simulation time 4665614993 ps
CPU time 5.58 seconds
Started Jul 22 04:51:35 PM PDT 24
Finished Jul 22 04:51:41 PM PDT 24
Peak memory 200936 kb
Host smart-ee2750e9-cb63-48b0-a558-e71f45c9d933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840381894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.2840381894
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.381309569
Short name T179
Test name
Test status
Simulation time 3787543246 ps
CPU time 8.39 seconds
Started Jul 22 04:51:45 PM PDT 24
Finished Jul 22 04:51:54 PM PDT 24
Peak memory 200960 kb
Host smart-79a7ee1f-5ef2-4700-89f2-a98089a6c8b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381309569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctr
l_edge_detect.381309569
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.176285838
Short name T116
Test name
Test status
Simulation time 2609878384 ps
CPU time 7.47 seconds
Started Jul 22 04:51:33 PM PDT 24
Finished Jul 22 04:51:41 PM PDT 24
Peak memory 200948 kb
Host smart-4da6d942-4a7c-4962-9cd5-b50975e576a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176285838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.176285838
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1820902055
Short name T472
Test name
Test status
Simulation time 2483108786 ps
CPU time 1.66 seconds
Started Jul 22 04:51:33 PM PDT 24
Finished Jul 22 04:51:36 PM PDT 24
Peak memory 200924 kb
Host smart-f8c88526-4516-44c3-9679-42d88345def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820902055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1820902055
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.4276868749
Short name T762
Test name
Test status
Simulation time 2248591351 ps
CPU time 1.87 seconds
Started Jul 22 04:51:36 PM PDT 24
Finished Jul 22 04:51:39 PM PDT 24
Peak memory 201020 kb
Host smart-89d5565f-9172-4438-a7c3-2a92b6e2731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276868749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.4276868749
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2324572810
Short name T561
Test name
Test status
Simulation time 2531400415 ps
CPU time 2.38 seconds
Started Jul 22 04:51:34 PM PDT 24
Finished Jul 22 04:51:37 PM PDT 24
Peak memory 200956 kb
Host smart-74d64e77-1536-4653-bc66-d7a106c5db11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324572810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2324572810
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.912070157
Short name T114
Test name
Test status
Simulation time 2118455722 ps
CPU time 3.1 seconds
Started Jul 22 04:51:37 PM PDT 24
Finished Jul 22 04:51:41 PM PDT 24
Peak memory 200948 kb
Host smart-207c9168-9af6-4c74-bbdc-31694de5c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912070157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.912070157
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.2422723269
Short name T43
Test name
Test status
Simulation time 8499139010 ps
CPU time 6 seconds
Started Jul 22 04:51:44 PM PDT 24
Finished Jul 22 04:51:51 PM PDT 24
Peak memory 200880 kb
Host smart-3004c155-72ca-4330-aff8-4317edb08755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422723269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.2422723269
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.647240748
Short name T85
Test name
Test status
Simulation time 31183622711 ps
CPU time 13.53 seconds
Started Jul 22 04:51:44 PM PDT 24
Finished Jul 22 04:51:58 PM PDT 24
Peak memory 217660 kb
Host smart-601ef9b2-efdc-4092-ae80-cf5ee2cb644d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647240748 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.647240748
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3271329529
Short name T136
Test name
Test status
Simulation time 4340044395 ps
CPU time 1.17 seconds
Started Jul 22 04:52:43 PM PDT 24
Finished Jul 22 04:52:46 PM PDT 24
Peak memory 200908 kb
Host smart-f91bdab4-f2aa-4ffe-a6cd-65f88ca28812
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271329529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.3271329529
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.1445789641
Short name T502
Test name
Test status
Simulation time 2015356754 ps
CPU time 5.09 seconds
Started Jul 22 04:51:44 PM PDT 24
Finished Jul 22 04:51:50 PM PDT 24
Peak memory 201020 kb
Host smart-ce604df2-2b86-421e-b01a-e7353b3903cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445789641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.1445789641
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2163124040
Short name T765
Test name
Test status
Simulation time 79725125797 ps
CPU time 194.74 seconds
Started Jul 22 04:51:46 PM PDT 24
Finished Jul 22 04:55:02 PM PDT 24
Peak memory 201020 kb
Host smart-5f4e1442-e4e6-40c2-b500-7336df17c453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163124040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.2
163124040
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1641807924
Short name T159
Test name
Test status
Simulation time 87244282797 ps
CPU time 54.58 seconds
Started Jul 22 04:51:43 PM PDT 24
Finished Jul 22 04:52:38 PM PDT 24
Peak memory 201196 kb
Host smart-dbd863cd-a932-488c-abf2-c85af1631b50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641807924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.1641807924
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1790258067
Short name T782
Test name
Test status
Simulation time 84083711967 ps
CPU time 200.96 seconds
Started Jul 22 04:51:43 PM PDT 24
Finished Jul 22 04:55:05 PM PDT 24
Peak memory 201388 kb
Host smart-4d811818-2da4-4d7e-8627-b83c49754e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790258067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.1790258067
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2547006337
Short name T4
Test name
Test status
Simulation time 2467045605 ps
CPU time 1.33 seconds
Started Jul 22 04:53:07 PM PDT 24
Finished Jul 22 04:53:09 PM PDT 24
Peak memory 200916 kb
Host smart-613a5250-39a2-4287-a88d-101c757aa5fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547006337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.2547006337
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3209745481
Short name T707
Test name
Test status
Simulation time 2618757857 ps
CPU time 3.81 seconds
Started Jul 22 04:51:44 PM PDT 24
Finished Jul 22 04:51:48 PM PDT 24
Peak memory 201016 kb
Host smart-8fc30604-21de-4e40-a051-b88651a68dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209745481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.3209745481
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.373728704
Short name T163
Test name
Test status
Simulation time 2499624263 ps
CPU time 1.37 seconds
Started Jul 22 04:51:45 PM PDT 24
Finished Jul 22 04:51:47 PM PDT 24
Peak memory 200880 kb
Host smart-9ce93bd3-7ffd-4821-a29a-555788cfad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373728704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.373728704
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1793628401
Short name T462
Test name
Test status
Simulation time 2176128939 ps
CPU time 6.47 seconds
Started Jul 22 04:51:43 PM PDT 24
Finished Jul 22 04:51:50 PM PDT 24
Peak memory 200968 kb
Host smart-84b2ab4e-f1fe-467e-a4c2-7a9bc0d38e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793628401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1793628401
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2556706247
Short name T481
Test name
Test status
Simulation time 2508764313 ps
CPU time 7.56 seconds
Started Jul 22 04:51:44 PM PDT 24
Finished Jul 22 04:51:52 PM PDT 24
Peak memory 200948 kb
Host smart-378bf8a2-ed15-49d2-8e2e-1102a8834a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556706247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2556706247
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.3742301749
Short name T575
Test name
Test status
Simulation time 2114894512 ps
CPU time 5.82 seconds
Started Jul 22 04:51:44 PM PDT 24
Finished Jul 22 04:51:51 PM PDT 24
Peak memory 200812 kb
Host smart-fa5765f5-ffe8-4859-add0-410871c2bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742301749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.3742301749
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.2741982555
Short name T31
Test name
Test status
Simulation time 11926944495 ps
CPU time 30.98 seconds
Started Jul 22 04:51:46 PM PDT 24
Finished Jul 22 04:52:18 PM PDT 24
Peak memory 200992 kb
Host smart-6ad19d12-d2b8-4b3a-88eb-c8885880d4ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741982555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.2741982555
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2147186979
Short name T134
Test name
Test status
Simulation time 3350455293 ps
CPU time 2.19 seconds
Started Jul 22 04:52:49 PM PDT 24
Finished Jul 22 04:52:52 PM PDT 24
Peak memory 200972 kb
Host smart-c167b7bb-5ffe-4079-986d-a449f4569976
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147186979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.2147186979
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.4293618886
Short name T220
Test name
Test status
Simulation time 2013315529 ps
CPU time 5.48 seconds
Started Jul 22 04:51:52 PM PDT 24
Finished Jul 22 04:51:58 PM PDT 24
Peak memory 201008 kb
Host smart-3424bcd1-2228-445a-9f20-d90d75260050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293618886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.4293618886
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1677083478
Short name T419
Test name
Test status
Simulation time 3152807904 ps
CPU time 9.11 seconds
Started Jul 22 04:51:53 PM PDT 24
Finished Jul 22 04:52:03 PM PDT 24
Peak memory 200964 kb
Host smart-6f49a0b1-7aa0-46c6-9700-f49b6da4876f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677083478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1
677083478
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3626660891
Short name T88
Test name
Test status
Simulation time 57886729165 ps
CPU time 36.05 seconds
Started Jul 22 04:51:54 PM PDT 24
Finished Jul 22 04:52:31 PM PDT 24
Peak memory 201288 kb
Host smart-1e168f11-ff0e-4748-8bd3-34b8bf43417d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626660891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.3626660891
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2040698020
Short name T354
Test name
Test status
Simulation time 30754846779 ps
CPU time 78.11 seconds
Started Jul 22 04:51:53 PM PDT 24
Finished Jul 22 04:53:12 PM PDT 24
Peak memory 201160 kb
Host smart-86bdc11e-c0f4-4c19-8b2b-93fed2ae718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040698020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2040698020
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1841976035
Short name T713
Test name
Test status
Simulation time 3251739805 ps
CPU time 1.64 seconds
Started Jul 22 04:51:54 PM PDT 24
Finished Jul 22 04:51:56 PM PDT 24
Peak memory 201004 kb
Host smart-f682f64c-765e-4805-b5d9-11a729074489
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841976035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.1841976035
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.202720417
Short name T232
Test name
Test status
Simulation time 2893248129 ps
CPU time 1.88 seconds
Started Jul 22 04:51:55 PM PDT 24
Finished Jul 22 04:51:57 PM PDT 24
Peak memory 200904 kb
Host smart-b548cc91-16ea-4ea8-a61b-0b010a8b5bb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202720417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctr
l_edge_detect.202720417
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.992160403
Short name T509
Test name
Test status
Simulation time 2775167388 ps
CPU time 1.05 seconds
Started Jul 22 04:51:54 PM PDT 24
Finished Jul 22 04:51:55 PM PDT 24
Peak memory 201024 kb
Host smart-9294c35a-d581-4438-bc85-df38e5873db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992160403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.992160403
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.402910574
Short name T227
Test name
Test status
Simulation time 2468287079 ps
CPU time 2.26 seconds
Started Jul 22 04:51:50 PM PDT 24
Finished Jul 22 04:51:53 PM PDT 24
Peak memory 200908 kb
Host smart-1c562a58-a4a1-484b-a40a-3febf9339c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402910574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.402910574
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3551743727
Short name T469
Test name
Test status
Simulation time 2041612245 ps
CPU time 2.91 seconds
Started Jul 22 04:51:56 PM PDT 24
Finished Jul 22 04:51:59 PM PDT 24
Peak memory 200852 kb
Host smart-f5c5ecea-e980-4c9f-94c1-8dea07ed3934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551743727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3551743727
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2208073916
Short name T635
Test name
Test status
Simulation time 2531958356 ps
CPU time 2.35 seconds
Started Jul 22 04:51:55 PM PDT 24
Finished Jul 22 04:51:58 PM PDT 24
Peak memory 200940 kb
Host smart-4b4133d8-e9c1-420f-91f4-4aa9cfab431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208073916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.2208073916
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.3385208960
Short name T748
Test name
Test status
Simulation time 2113973968 ps
CPU time 5.71 seconds
Started Jul 22 04:51:54 PM PDT 24
Finished Jul 22 04:52:01 PM PDT 24
Peak memory 200952 kb
Host smart-f68ffe91-eaad-4a34-b16d-0972d716dec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385208960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3385208960
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3915321950
Short name T157
Test name
Test status
Simulation time 8895535746 ps
CPU time 6.52 seconds
Started Jul 22 04:55:00 PM PDT 24
Finished Jul 22 04:55:07 PM PDT 24
Peak memory 200924 kb
Host smart-83bb4d65-9c91-4f84-af93-8d7a946ac8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915321950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3915321950
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1297637027
Short name T616
Test name
Test status
Simulation time 4031195187 ps
CPU time 2.34 seconds
Started Jul 22 04:51:54 PM PDT 24
Finished Jul 22 04:51:57 PM PDT 24
Peak memory 201004 kb
Host smart-717b174b-1b11-4a1d-b114-71a64519f28c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297637027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.1297637027
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3048104669
Short name T517
Test name
Test status
Simulation time 2039694570 ps
CPU time 1.95 seconds
Started Jul 22 04:52:02 PM PDT 24
Finished Jul 22 04:52:05 PM PDT 24
Peak memory 200940 kb
Host smart-3f20d582-0a92-4f9b-9ce0-847b094bb698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048104669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3048104669
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.961157344
Short name T346
Test name
Test status
Simulation time 79756412962 ps
CPU time 169.59 seconds
Started Jul 22 04:51:57 PM PDT 24
Finished Jul 22 04:54:47 PM PDT 24
Peak memory 201176 kb
Host smart-4ec18174-8336-4d64-aa4e-62e746ba28bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961157344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_combo_detect.961157344
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2130377316
Short name T243
Test name
Test status
Simulation time 132412484275 ps
CPU time 323.41 seconds
Started Jul 22 04:51:57 PM PDT 24
Finished Jul 22 04:57:20 PM PDT 24
Peak memory 201296 kb
Host smart-b7980525-2831-44b8-81c1-c9c458d6e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130377316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.2130377316
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2055213976
Short name T427
Test name
Test status
Simulation time 3903444287 ps
CPU time 3.13 seconds
Started Jul 22 04:51:55 PM PDT 24
Finished Jul 22 04:51:59 PM PDT 24
Peak memory 200936 kb
Host smart-974a745e-f613-4b0f-aa99-71a677b56f2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055213976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.2055213976
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1766040981
Short name T726
Test name
Test status
Simulation time 3235809710 ps
CPU time 7 seconds
Started Jul 22 04:51:52 PM PDT 24
Finished Jul 22 04:51:59 PM PDT 24
Peak memory 201000 kb
Host smart-6b66466e-0575-47ed-bc7b-702a7a96f410
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766040981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1766040981
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3724660432
Short name T636
Test name
Test status
Simulation time 2616610374 ps
CPU time 4.18 seconds
Started Jul 22 04:51:52 PM PDT 24
Finished Jul 22 04:51:57 PM PDT 24
Peak memory 200952 kb
Host smart-ef61cadf-470c-4b82-b371-7636130fcd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724660432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3724660432
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1454080661
Short name T755
Test name
Test status
Simulation time 2449042801 ps
CPU time 7.28 seconds
Started Jul 22 04:51:56 PM PDT 24
Finished Jul 22 04:52:04 PM PDT 24
Peak memory 200920 kb
Host smart-03ef4301-12b9-4371-9e21-e493e681693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454080661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1454080661
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2324154738
Short name T698
Test name
Test status
Simulation time 2047420308 ps
CPU time 1.85 seconds
Started Jul 22 04:51:53 PM PDT 24
Finished Jul 22 04:51:56 PM PDT 24
Peak memory 200952 kb
Host smart-42e56bdd-5ce2-45c5-b538-592ae3d3893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324154738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.2324154738
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.380234130
Short name T428
Test name
Test status
Simulation time 2508097453 ps
CPU time 6.69 seconds
Started Jul 22 04:51:59 PM PDT 24
Finished Jul 22 04:52:07 PM PDT 24
Peak memory 201000 kb
Host smart-c9d20c3e-415d-4648-a854-2f175d88b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380234130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.380234130
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3643790185
Short name T14
Test name
Test status
Simulation time 2108507406 ps
CPU time 6.14 seconds
Started Jul 22 04:51:53 PM PDT 24
Finished Jul 22 04:52:00 PM PDT 24
Peak memory 200948 kb
Host smart-c805fe48-e887-4afc-87eb-dfa8a9d9ecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643790185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3643790185
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.2096213362
Short name T390
Test name
Test status
Simulation time 6955506462 ps
CPU time 5.72 seconds
Started Jul 22 04:51:59 PM PDT 24
Finished Jul 22 04:52:06 PM PDT 24
Peak memory 200992 kb
Host smart-1d3af22c-7bcd-4630-9c99-d187e219a980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096213362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.2096213362
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1764527306
Short name T779
Test name
Test status
Simulation time 16567686041 ps
CPU time 42.15 seconds
Started Jul 22 04:51:53 PM PDT 24
Finished Jul 22 04:52:36 PM PDT 24
Peak memory 209532 kb
Host smart-8ca88b76-ec42-438b-8ba7-7015de0eafff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764527306 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.1764527306
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1404956547
Short name T315
Test name
Test status
Simulation time 9591073809 ps
CPU time 2.7 seconds
Started Jul 22 04:51:51 PM PDT 24
Finished Jul 22 04:51:54 PM PDT 24
Peak memory 200964 kb
Host smart-3bf613e4-447f-4636-8994-c533db40c0e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404956547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1404956547
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.1024724924
Short name T199
Test name
Test status
Simulation time 2055104637 ps
CPU time 1.29 seconds
Started Jul 22 04:52:02 PM PDT 24
Finished Jul 22 04:52:05 PM PDT 24
Peak memory 200948 kb
Host smart-0a24a8f7-b942-4ea7-920b-f21a200d55c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024724924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.1024724924
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2649938005
Short name T537
Test name
Test status
Simulation time 3228699086 ps
CPU time 1.34 seconds
Started Jul 22 04:52:02 PM PDT 24
Finished Jul 22 04:52:03 PM PDT 24
Peak memory 201016 kb
Host smart-687cfef1-4fc4-4ab5-a0bb-0376b9489052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649938005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.2
649938005
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1742819991
Short name T753
Test name
Test status
Simulation time 54045646663 ps
CPU time 35.12 seconds
Started Jul 22 04:52:01 PM PDT 24
Finished Jul 22 04:52:37 PM PDT 24
Peak memory 201232 kb
Host smart-307dbab3-ccc2-4504-b28c-e24134109862
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742819991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.1742819991
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1180511536
Short name T423
Test name
Test status
Simulation time 3413432844 ps
CPU time 2.3 seconds
Started Jul 22 04:52:01 PM PDT 24
Finished Jul 22 04:52:04 PM PDT 24
Peak memory 201284 kb
Host smart-712d0c6a-6f07-40d4-b699-b31ab53237b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180511536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1180511536
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2641941280
Short name T177
Test name
Test status
Simulation time 3141005426 ps
CPU time 5.97 seconds
Started Jul 22 04:52:05 PM PDT 24
Finished Jul 22 04:52:11 PM PDT 24
Peak memory 200932 kb
Host smart-72091a07-d87a-4212-9c8a-22acc6da74e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641941280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2641941280
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4122735573
Short name T651
Test name
Test status
Simulation time 2609565779 ps
CPU time 7.15 seconds
Started Jul 22 04:52:00 PM PDT 24
Finished Jul 22 04:52:08 PM PDT 24
Peak memory 200956 kb
Host smart-72930a47-593a-4e68-975d-c3e1da56719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122735573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.4122735573
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.331420163
Short name T433
Test name
Test status
Simulation time 2472648570 ps
CPU time 1.85 seconds
Started Jul 22 04:52:01 PM PDT 24
Finished Jul 22 04:52:03 PM PDT 24
Peak memory 201004 kb
Host smart-13f00288-7df2-40d4-b8c1-7912d109b908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331420163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.331420163
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3869975556
Short name T432
Test name
Test status
Simulation time 2241468364 ps
CPU time 6.22 seconds
Started Jul 22 04:52:06 PM PDT 24
Finished Jul 22 04:52:12 PM PDT 24
Peak memory 200884 kb
Host smart-18555327-7fcf-44ea-897a-c29800587a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869975556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3869975556
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2107875497
Short name T566
Test name
Test status
Simulation time 2535647331 ps
CPU time 2.46 seconds
Started Jul 22 04:52:06 PM PDT 24
Finished Jul 22 04:52:09 PM PDT 24
Peak memory 200888 kb
Host smart-28161a56-4160-4226-971b-7c937c346629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107875497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2107875497
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.1575021068
Short name T122
Test name
Test status
Simulation time 2129504813 ps
CPU time 1.98 seconds
Started Jul 22 04:52:03 PM PDT 24
Finished Jul 22 04:52:06 PM PDT 24
Peak memory 200884 kb
Host smart-9340619b-e211-41a8-8990-1839409e9ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575021068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1575021068
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2506757733
Short name T183
Test name
Test status
Simulation time 140004152213 ps
CPU time 351.04 seconds
Started Jul 22 04:52:02 PM PDT 24
Finished Jul 22 04:57:55 PM PDT 24
Peak memory 201220 kb
Host smart-c5a05905-fbef-449f-be79-b21f9a3eadde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506757733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.2506757733
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.382942682
Short name T188
Test name
Test status
Simulation time 38354950437 ps
CPU time 23.92 seconds
Started Jul 22 04:52:01 PM PDT 24
Finished Jul 22 04:52:25 PM PDT 24
Peak memory 209648 kb
Host smart-57bbabd8-bb6f-4207-9b9d-f9428deca52d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382942682 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.382942682
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2805116005
Short name T708
Test name
Test status
Simulation time 6977216406 ps
CPU time 1.94 seconds
Started Jul 22 04:52:02 PM PDT 24
Finished Jul 22 04:52:06 PM PDT 24
Peak memory 200912 kb
Host smart-4ef0bf2d-6214-4caa-a7bf-670797290353
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805116005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.2805116005
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.3567147581
Short name T417
Test name
Test status
Simulation time 2015279426 ps
CPU time 5.73 seconds
Started Jul 22 04:48:30 PM PDT 24
Finished Jul 22 04:48:36 PM PDT 24
Peak memory 200940 kb
Host smart-1a3c9eef-98b6-493c-b27b-c645575ffede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567147581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.3567147581
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2100489805
Short name T185
Test name
Test status
Simulation time 3414617176 ps
CPU time 7.82 seconds
Started Jul 22 04:48:29 PM PDT 24
Finished Jul 22 04:48:37 PM PDT 24
Peak memory 200972 kb
Host smart-b5d3ba03-082b-4c2f-8b2c-d89a38258912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100489805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2100489805
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2253911772
Short name T371
Test name
Test status
Simulation time 53540343313 ps
CPU time 36.75 seconds
Started Jul 22 04:48:31 PM PDT 24
Finished Jul 22 04:49:08 PM PDT 24
Peak memory 201232 kb
Host smart-f815ce6a-cc55-4a76-99d6-64ee2c9a8a8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253911772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.2253911772
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3552634850
Short name T238
Test name
Test status
Simulation time 99441364262 ps
CPU time 253.04 seconds
Started Jul 22 04:49:02 PM PDT 24
Finished Jul 22 04:53:15 PM PDT 24
Peak memory 201212 kb
Host smart-562dc5cc-0092-4bc2-a9b3-c467e4b2faf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552634850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.3552634850
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.293290422
Short name T274
Test name
Test status
Simulation time 3828052249 ps
CPU time 3.26 seconds
Started Jul 22 04:48:30 PM PDT 24
Finished Jul 22 04:48:34 PM PDT 24
Peak memory 201000 kb
Host smart-e0f36e3d-fd6c-4224-b114-385ecd6ecc61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293290422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ec_pwr_on_rst.293290422
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3251869827
Short name T140
Test name
Test status
Simulation time 4314214451 ps
CPU time 10.23 seconds
Started Jul 22 04:48:30 PM PDT 24
Finished Jul 22 04:48:40 PM PDT 24
Peak memory 201032 kb
Host smart-d1aa9f87-9367-42c8-94b7-e8ac9e970d9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251869827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3251869827
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.511266624
Short name T758
Test name
Test status
Simulation time 2614210068 ps
CPU time 7.03 seconds
Started Jul 22 04:48:26 PM PDT 24
Finished Jul 22 04:48:34 PM PDT 24
Peak memory 200932 kb
Host smart-50af301b-2ef7-4e31-9595-d6d1a11c4ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511266624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.511266624
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1861922140
Short name T580
Test name
Test status
Simulation time 2476725395 ps
CPU time 2.21 seconds
Started Jul 22 04:48:22 PM PDT 24
Finished Jul 22 04:48:25 PM PDT 24
Peak memory 200904 kb
Host smart-5f20e07d-2286-4f9c-918e-46f85189e3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861922140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1861922140
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3864568769
Short name T526
Test name
Test status
Simulation time 2109050665 ps
CPU time 1.33 seconds
Started Jul 22 04:48:21 PM PDT 24
Finished Jul 22 04:48:23 PM PDT 24
Peak memory 200872 kb
Host smart-248a9dae-2836-4a43-974b-20ad91e3af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864568769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.3864568769
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.100546374
Short name T771
Test name
Test status
Simulation time 2513217665 ps
CPU time 6.78 seconds
Started Jul 22 04:48:21 PM PDT 24
Finished Jul 22 04:48:29 PM PDT 24
Peak memory 200940 kb
Host smart-b29dd0f6-83af-40fc-b91c-60c3cd4cbbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100546374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.100546374
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.678182340
Short name T657
Test name
Test status
Simulation time 2112110243 ps
CPU time 6.31 seconds
Started Jul 22 04:48:22 PM PDT 24
Finished Jul 22 04:48:29 PM PDT 24
Peak memory 200832 kb
Host smart-903504fe-5e64-4cb2-b140-102f60c8b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678182340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.678182340
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.3743914632
Short name T583
Test name
Test status
Simulation time 1005261632003 ps
CPU time 7.05 seconds
Started Jul 22 04:48:27 PM PDT 24
Finished Jul 22 04:48:35 PM PDT 24
Peak memory 200928 kb
Host smart-1b74ce98-94d6-4029-bc79-0376a77beb1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743914632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.3743914632
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.249404352
Short name T722
Test name
Test status
Simulation time 35271902270 ps
CPU time 86.67 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:49:55 PM PDT 24
Peak memory 217608 kb
Host smart-c6b537fb-7fa0-45dc-965a-f3e7b7e084cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249404352 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.249404352
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3352020214
Short name T465
Test name
Test status
Simulation time 7072831256 ps
CPU time 2.43 seconds
Started Jul 22 04:48:31 PM PDT 24
Finished Jul 22 04:48:33 PM PDT 24
Peak memory 200964 kb
Host smart-e879d7d5-aadf-4d72-a7d6-a7b33d406025
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352020214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.3352020214
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3023426102
Short name T364
Test name
Test status
Simulation time 32191853151 ps
CPU time 19.37 seconds
Started Jul 22 04:52:02 PM PDT 24
Finished Jul 22 04:52:23 PM PDT 24
Peak memory 201168 kb
Host smart-8b4f3908-c5bb-48d3-9611-c589ab6ffae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023426102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.3023426102
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.687076939
Short name T706
Test name
Test status
Simulation time 21591517043 ps
CPU time 29.25 seconds
Started Jul 22 04:51:59 PM PDT 24
Finished Jul 22 04:52:29 PM PDT 24
Peak memory 201232 kb
Host smart-0b12d78d-5497-4686-9ca1-cffb3826c2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687076939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_wi
th_pre_cond.687076939
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2532897029
Short name T746
Test name
Test status
Simulation time 100502842535 ps
CPU time 254.46 seconds
Started Jul 22 04:52:54 PM PDT 24
Finished Jul 22 04:57:09 PM PDT 24
Peak memory 201188 kb
Host smart-06874531-24a6-433f-809c-cc8e61e5b90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532897029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.2532897029
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3455020071
Short name T728
Test name
Test status
Simulation time 89526846100 ps
CPU time 226.89 seconds
Started Jul 22 04:52:01 PM PDT 24
Finished Jul 22 04:55:49 PM PDT 24
Peak memory 201280 kb
Host smart-fdb33e12-aa79-40f4-bc76-0890328cdf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455020071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.3455020071
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2909354414
Short name T772
Test name
Test status
Simulation time 32945066368 ps
CPU time 81.67 seconds
Started Jul 22 04:52:08 PM PDT 24
Finished Jul 22 04:53:30 PM PDT 24
Peak memory 201292 kb
Host smart-0ba0ac85-b4db-43ac-aab0-fc4f18a600c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909354414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.2909354414
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.487810318
Short name T474
Test name
Test status
Simulation time 2026377983 ps
CPU time 1.98 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:48:31 PM PDT 24
Peak memory 201024 kb
Host smart-1cc3e66a-700b-4d89-94f0-47db36133007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487810318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test
.487810318
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.9407139
Short name T653
Test name
Test status
Simulation time 3269853614 ps
CPU time 1.25 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:48:30 PM PDT 24
Peak memory 200996 kb
Host smart-5fe06976-24b7-4f12-b549-15186e5a4e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9407139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.9407139
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3690618530
Short name T607
Test name
Test status
Simulation time 41327245545 ps
CPU time 26.93 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:48:56 PM PDT 24
Peak memory 201260 kb
Host smart-db377de8-5208-479c-a60e-4334cf0c016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690618530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.3690618530
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.381607528
Short name T398
Test name
Test status
Simulation time 2754490696 ps
CPU time 2 seconds
Started Jul 22 04:48:29 PM PDT 24
Finished Jul 22 04:48:32 PM PDT 24
Peak memory 201000 kb
Host smart-26594eb7-85b7-45f0-9bd7-d8f03240b4cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381607528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_ec_pwr_on_rst.381607528
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1535153313
Short name T702
Test name
Test status
Simulation time 2817609557 ps
CPU time 4.29 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:48:33 PM PDT 24
Peak memory 200952 kb
Host smart-d45967f2-6f82-4f84-b89d-29aa8cbda00c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535153313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1535153313
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3996946338
Short name T739
Test name
Test status
Simulation time 2630302626 ps
CPU time 2.06 seconds
Started Jul 22 04:48:29 PM PDT 24
Finished Jul 22 04:48:32 PM PDT 24
Peak memory 200988 kb
Host smart-3a93c7d4-75b3-4612-8988-157e177ea598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996946338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3996946338
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3918864484
Short name T505
Test name
Test status
Simulation time 2499970213 ps
CPU time 2.27 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:07 PM PDT 24
Peak memory 201016 kb
Host smart-fbeab83d-9d40-46a2-b83a-442931c8aae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918864484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.3918864484
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2989195899
Short name T181
Test name
Test status
Simulation time 2185962393 ps
CPU time 6.2 seconds
Started Jul 22 04:48:30 PM PDT 24
Finished Jul 22 04:48:37 PM PDT 24
Peak memory 201020 kb
Host smart-ddd3c933-c68e-499d-b6fa-616d6c3b2395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989195899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.2989195899
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2972046076
Short name T497
Test name
Test status
Simulation time 2511578634 ps
CPU time 6.88 seconds
Started Jul 22 04:48:38 PM PDT 24
Finished Jul 22 04:48:46 PM PDT 24
Peak memory 201000 kb
Host smart-271744a6-1d7d-40be-857d-c11d04ad4d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972046076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.2972046076
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.861397127
Short name T96
Test name
Test status
Simulation time 2118066702 ps
CPU time 3.18 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:48:32 PM PDT 24
Peak memory 200884 kb
Host smart-ba87ae2d-fe9c-4ab4-a170-a6ba40cfa0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861397127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.861397127
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.2018891211
Short name T425
Test name
Test status
Simulation time 13509107349 ps
CPU time 4.96 seconds
Started Jul 22 04:48:30 PM PDT 24
Finished Jul 22 04:48:35 PM PDT 24
Peak memory 200944 kb
Host smart-751100f0-c7e3-41fe-9c9c-25d9cb586eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018891211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.2018891211
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3867537118
Short name T747
Test name
Test status
Simulation time 29033951145 ps
CPU time 33.48 seconds
Started Jul 22 04:48:30 PM PDT 24
Finished Jul 22 04:49:04 PM PDT 24
Peak memory 209540 kb
Host smart-0e22f865-f55d-4ce5-9d64-4c957793b3c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867537118 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.3867537118
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2711601782
Short name T237
Test name
Test status
Simulation time 6105044832100 ps
CPU time 60.92 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:49:30 PM PDT 24
Peak memory 200860 kb
Host smart-92e78c6a-5d03-46b6-b259-2ea7c290854c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711601782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.2711601782
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.335491662
Short name T785
Test name
Test status
Simulation time 23336247278 ps
CPU time 30.03 seconds
Started Jul 22 04:52:08 PM PDT 24
Finished Jul 22 04:52:39 PM PDT 24
Peak memory 201292 kb
Host smart-c030c219-6bf5-4c02-bde0-122f3a9294c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335491662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi
th_pre_cond.335491662
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1387595635
Short name T793
Test name
Test status
Simulation time 48054567619 ps
CPU time 31.51 seconds
Started Jul 22 04:52:12 PM PDT 24
Finished Jul 22 04:52:45 PM PDT 24
Peak memory 201276 kb
Host smart-78ecf23e-f02f-4f67-b00e-03105b4de8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387595635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1387595635
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3773437780
Short name T789
Test name
Test status
Simulation time 22340571894 ps
CPU time 32.34 seconds
Started Jul 22 04:52:11 PM PDT 24
Finished Jul 22 04:52:44 PM PDT 24
Peak memory 201276 kb
Host smart-574c97a8-85c7-4689-8a89-83f58b482bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773437780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.3773437780
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3427382538
Short name T710
Test name
Test status
Simulation time 67131384384 ps
CPU time 38.72 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:52:48 PM PDT 24
Peak memory 201412 kb
Host smart-926238c3-eefd-4a23-837a-ec7cf7975fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427382538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3427382538
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3760301069
Short name T244
Test name
Test status
Simulation time 56618778421 ps
CPU time 22.72 seconds
Started Jul 22 04:52:08 PM PDT 24
Finished Jul 22 04:52:31 PM PDT 24
Peak memory 201364 kb
Host smart-ed2b85b4-9070-4eee-a349-1e10871587f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760301069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.3760301069
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1867359307
Short name T48
Test name
Test status
Simulation time 68699953303 ps
CPU time 164.36 seconds
Started Jul 22 04:52:08 PM PDT 24
Finished Jul 22 04:54:53 PM PDT 24
Peak memory 201268 kb
Host smart-cd31d040-347f-4f4a-b4a9-83bf538b6dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867359307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.1867359307
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4096130604
Short name T767
Test name
Test status
Simulation time 25912765591 ps
CPU time 7.64 seconds
Started Jul 22 04:54:43 PM PDT 24
Finished Jul 22 04:54:51 PM PDT 24
Peak memory 201288 kb
Host smart-758e416c-a30a-4801-a2f0-b6ee4b8b9edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096130604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.4096130604
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2496413593
Short name T604
Test name
Test status
Simulation time 31585300285 ps
CPU time 40.38 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:52:50 PM PDT 24
Peak memory 201296 kb
Host smart-7f3e73ac-23ab-458e-a936-a13466d7eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496413593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.2496413593
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.3014908188
Short name T503
Test name
Test status
Simulation time 2009772116 ps
CPU time 5.8 seconds
Started Jul 22 04:48:40 PM PDT 24
Finished Jul 22 04:48:47 PM PDT 24
Peak memory 200888 kb
Host smart-55510272-024b-4790-8162-bfc8414e3a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014908188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.3014908188
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3387967452
Short name T299
Test name
Test status
Simulation time 3654798490 ps
CPU time 1.08 seconds
Started Jul 22 04:48:51 PM PDT 24
Finished Jul 22 04:48:53 PM PDT 24
Peak memory 201088 kb
Host smart-0836f9de-29cd-46c2-80dd-70db75c884b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387967452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.3387967452
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.4110300499
Short name T81
Test name
Test status
Simulation time 46203170111 ps
CPU time 12.66 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:17 PM PDT 24
Peak memory 201240 kb
Host smart-cae96373-c7e4-4455-a0a7-624055a49bbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110300499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.4110300499
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.247987947
Short name T645
Test name
Test status
Simulation time 64979706775 ps
CPU time 43.98 seconds
Started Jul 22 04:48:39 PM PDT 24
Finished Jul 22 04:49:24 PM PDT 24
Peak memory 201220 kb
Host smart-31fe7f79-fee3-4ebe-8e3c-fd22887d8168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247987947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wit
h_pre_cond.247987947
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1949413245
Short name T672
Test name
Test status
Simulation time 4119397648 ps
CPU time 10.78 seconds
Started Jul 22 04:48:39 PM PDT 24
Finished Jul 22 04:48:51 PM PDT 24
Peak memory 200928 kb
Host smart-731995e5-138a-47f1-b0c6-f96db1878344
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949413245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.1949413245
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.1913226789
Short name T146
Test name
Test status
Simulation time 4760378863 ps
CPU time 10.43 seconds
Started Jul 22 04:48:36 PM PDT 24
Finished Jul 22 04:48:47 PM PDT 24
Peak memory 201040 kb
Host smart-e98ad6f0-ec43-439c-92a1-8de94c1d68aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913226789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.1913226789
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2292949097
Short name T593
Test name
Test status
Simulation time 2619913972 ps
CPU time 4.03 seconds
Started Jul 22 04:48:38 PM PDT 24
Finished Jul 22 04:48:43 PM PDT 24
Peak memory 200968 kb
Host smart-28a48620-a069-40df-9e70-24e3a990f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292949097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2292949097
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.391446424
Short name T569
Test name
Test status
Simulation time 2468276680 ps
CPU time 4.1 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:48:33 PM PDT 24
Peak memory 200948 kb
Host smart-f0b84717-3e41-4ef2-ae93-72daef2ff809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391446424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.391446424
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1801592132
Short name T197
Test name
Test status
Simulation time 2025105735 ps
CPU time 5.83 seconds
Started Jul 22 04:48:47 PM PDT 24
Finished Jul 22 04:48:54 PM PDT 24
Peak memory 200944 kb
Host smart-835f5868-7d30-4e4c-852c-c60574c9712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801592132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1801592132
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.814607673
Short name T221
Test name
Test status
Simulation time 2510369219 ps
CPU time 7.02 seconds
Started Jul 22 04:48:37 PM PDT 24
Finished Jul 22 04:48:44 PM PDT 24
Peak memory 200892 kb
Host smart-d7bbd541-c8be-4205-ac49-60224678ef21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814607673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.814607673
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.2850844782
Short name T605
Test name
Test status
Simulation time 2108448961 ps
CPU time 5.68 seconds
Started Jul 22 04:49:04 PM PDT 24
Finished Jul 22 04:49:10 PM PDT 24
Peak memory 200936 kb
Host smart-93cedaf6-80ff-466f-8ab5-4c16f81fd880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850844782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2850844782
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.3947730066
Short name T186
Test name
Test status
Simulation time 9058918946 ps
CPU time 25.84 seconds
Started Jul 22 04:48:38 PM PDT 24
Finished Jul 22 04:49:05 PM PDT 24
Peak memory 201276 kb
Host smart-47f0831b-6613-4f70-b300-5e99d1ab72e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947730066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.3947730066
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1301700683
Short name T317
Test name
Test status
Simulation time 35963958752 ps
CPU time 45.04 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:49:33 PM PDT 24
Peak memory 209632 kb
Host smart-e0bbf2bc-061f-48f3-a4c3-ca26277ed4a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301700683 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1301700683
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2579473508
Short name T787
Test name
Test status
Simulation time 4554607630 ps
CPU time 1.48 seconds
Started Jul 22 04:48:37 PM PDT 24
Finished Jul 22 04:48:40 PM PDT 24
Peak memory 201008 kb
Host smart-e99e1c6e-bc2c-4017-a2df-3e63a92406a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579473508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.2579473508
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1757814936
Short name T1
Test name
Test status
Simulation time 42212924786 ps
CPU time 105.01 seconds
Started Jul 22 04:52:08 PM PDT 24
Finished Jul 22 04:53:53 PM PDT 24
Peak memory 201264 kb
Host smart-fb79a591-3d91-4ce0-ac59-fe07a36c64ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757814936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.1757814936
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3625633435
Short name T269
Test name
Test status
Simulation time 24831963422 ps
CPU time 66.49 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:53:16 PM PDT 24
Peak memory 201316 kb
Host smart-2776dadd-6196-4b61-a5dd-2e59df1f4fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625633435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.3625633435
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.4187073374
Short name T366
Test name
Test status
Simulation time 43859358324 ps
CPU time 65.62 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:53:16 PM PDT 24
Peak memory 201196 kb
Host smart-c2fd216e-7cc0-4b50-b25c-9c893a64c37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187073374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.4187073374
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.482605291
Short name T701
Test name
Test status
Simulation time 46956171303 ps
CPU time 31.96 seconds
Started Jul 22 04:52:12 PM PDT 24
Finished Jul 22 04:52:45 PM PDT 24
Peak memory 201276 kb
Host smart-39161fa1-b8dc-46a2-99ca-cf40abc9acc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482605291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_wi
th_pre_cond.482605291
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.762460326
Short name T250
Test name
Test status
Simulation time 69848812801 ps
CPU time 171.47 seconds
Started Jul 22 04:52:13 PM PDT 24
Finished Jul 22 04:55:05 PM PDT 24
Peak memory 201288 kb
Host smart-cdae4128-c986-4ba4-b41e-27effe9948e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762460326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_wi
th_pre_cond.762460326
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1617173261
Short name T372
Test name
Test status
Simulation time 45310973835 ps
CPU time 113.62 seconds
Started Jul 22 04:54:43 PM PDT 24
Finished Jul 22 04:56:37 PM PDT 24
Peak memory 201332 kb
Host smart-086b3225-64ba-4530-978f-36e617f7a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617173261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.1617173261
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.209788009
Short name T689
Test name
Test status
Simulation time 23578000505 ps
CPU time 59.94 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:53:10 PM PDT 24
Peak memory 201216 kb
Host smart-534e91e1-5b36-40bb-a3c3-3756ba493e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209788009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_wi
th_pre_cond.209788009
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1242367815
Short name T606
Test name
Test status
Simulation time 26346722944 ps
CPU time 19.1 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:52:29 PM PDT 24
Peak memory 201264 kb
Host smart-d98e48c8-243e-42fb-840e-5da987acd3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242367815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.1242367815
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.2108911565
Short name T658
Test name
Test status
Simulation time 2010539310 ps
CPU time 5.76 seconds
Started Jul 22 04:48:38 PM PDT 24
Finished Jul 22 04:48:45 PM PDT 24
Peak memory 201020 kb
Host smart-93f0ce75-6d58-4c83-80e3-937fefee692e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108911565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.2108911565
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3706336769
Short name T784
Test name
Test status
Simulation time 183321570360 ps
CPU time 412.14 seconds
Started Jul 22 04:48:41 PM PDT 24
Finished Jul 22 04:55:34 PM PDT 24
Peak memory 200988 kb
Host smart-02eb7121-5d6e-450f-bd2f-fc0e68eb6ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706336769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.3706336769
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.1084810872
Short name T257
Test name
Test status
Simulation time 40533648577 ps
CPU time 41.58 seconds
Started Jul 22 04:48:38 PM PDT 24
Finished Jul 22 04:49:20 PM PDT 24
Peak memory 201036 kb
Host smart-edf60827-bd47-4222-b276-47156fc40121
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084810872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.1084810872
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2673380749
Short name T673
Test name
Test status
Simulation time 4944594075 ps
CPU time 13.91 seconds
Started Jul 22 04:48:39 PM PDT 24
Finished Jul 22 04:48:54 PM PDT 24
Peak memory 200928 kb
Host smart-5aec6be9-45ff-467e-8ac4-912fb6b3851d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673380749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.2673380749
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2872961002
Short name T46
Test name
Test status
Simulation time 3105647681 ps
CPU time 1.47 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:50 PM PDT 24
Peak memory 201004 kb
Host smart-7dcd43eb-4be7-4399-80bb-82154e073ac3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872961002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2872961002
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3925417622
Short name T170
Test name
Test status
Simulation time 2623051465 ps
CPU time 2.48 seconds
Started Jul 22 04:48:40 PM PDT 24
Finished Jul 22 04:48:43 PM PDT 24
Peak memory 200952 kb
Host smart-1bb06c5d-8633-47c5-b5e1-5b25f90ec7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925417622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3925417622
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2916898773
Short name T20
Test name
Test status
Simulation time 2477109037 ps
CPU time 2.5 seconds
Started Jul 22 04:48:39 PM PDT 24
Finished Jul 22 04:48:42 PM PDT 24
Peak memory 200996 kb
Host smart-bb0c9075-7886-46c5-8237-4ffe73160010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916898773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2916898773
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3705320961
Short name T211
Test name
Test status
Simulation time 2349440295 ps
CPU time 1.11 seconds
Started Jul 22 04:48:37 PM PDT 24
Finished Jul 22 04:48:38 PM PDT 24
Peak memory 200876 kb
Host smart-6222c084-723a-4a43-b509-d30a766d55b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705320961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3705320961
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2256632078
Short name T394
Test name
Test status
Simulation time 2511121556 ps
CPU time 6.61 seconds
Started Jul 22 04:49:07 PM PDT 24
Finished Jul 22 04:49:14 PM PDT 24
Peak memory 200908 kb
Host smart-db370dae-3351-4b51-a664-28f5e42c0e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256632078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2256632078
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.2115386641
Short name T715
Test name
Test status
Simulation time 2145825956 ps
CPU time 1.58 seconds
Started Jul 22 04:48:47 PM PDT 24
Finished Jul 22 04:48:49 PM PDT 24
Peak memory 200940 kb
Host smart-35651e04-686f-4dea-86b1-212d43e87837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115386641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.2115386641
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.3098415865
Short name T307
Test name
Test status
Simulation time 13992041662 ps
CPU time 35.46 seconds
Started Jul 22 04:49:08 PM PDT 24
Finished Jul 22 04:49:44 PM PDT 24
Peak memory 200864 kb
Host smart-716cb286-54e6-4287-a574-51d5fdb80844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098415865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.3098415865
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3340996681
Short name T704
Test name
Test status
Simulation time 53307403372 ps
CPU time 127.9 seconds
Started Jul 22 04:48:38 PM PDT 24
Finished Jul 22 04:50:47 PM PDT 24
Peak memory 209592 kb
Host smart-432f6bfc-3bbb-402d-b77f-bb6e8d7580d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340996681 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.3340996681
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4243351170
Short name T389
Test name
Test status
Simulation time 1836346639203 ps
CPU time 393.07 seconds
Started Jul 22 04:48:37 PM PDT 24
Finished Jul 22 04:55:11 PM PDT 24
Peak memory 200948 kb
Host smart-da175a1a-b590-41a5-8845-77baaf748955
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243351170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.4243351170
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.4009757169
Short name T251
Test name
Test status
Simulation time 56049047264 ps
CPU time 133.14 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:54:23 PM PDT 24
Peak memory 201288 kb
Host smart-42921fb8-2668-47d7-8a1a-eff639e6d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009757169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.4009757169
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3759584272
Short name T356
Test name
Test status
Simulation time 66940183538 ps
CPU time 88.54 seconds
Started Jul 22 04:52:09 PM PDT 24
Finished Jul 22 04:53:38 PM PDT 24
Peak memory 201380 kb
Host smart-66478893-54ed-4ca2-83d4-b64e6ea01eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759584272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.3759584272
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.449774234
Short name T634
Test name
Test status
Simulation time 54587641202 ps
CPU time 61.12 seconds
Started Jul 22 04:52:10 PM PDT 24
Finished Jul 22 04:53:12 PM PDT 24
Peak memory 201616 kb
Host smart-b7ad5886-3e24-4def-a2f2-8ea3863a15fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449774234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wi
th_pre_cond.449774234
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.292216468
Short name T362
Test name
Test status
Simulation time 117824341558 ps
CPU time 258.11 seconds
Started Jul 22 04:52:08 PM PDT 24
Finished Jul 22 04:56:26 PM PDT 24
Peak memory 201284 kb
Host smart-a46abe89-ebcb-4ef3-9650-16a544bd0e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292216468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_wi
th_pre_cond.292216468
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3715250098
Short name T355
Test name
Test status
Simulation time 83121266001 ps
CPU time 39.36 seconds
Started Jul 22 04:52:10 PM PDT 24
Finished Jul 22 04:52:50 PM PDT 24
Peak memory 201204 kb
Host smart-04503676-9a20-4fef-815d-8ec1696fa699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715250098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.3715250098
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1736129426
Short name T383
Test name
Test status
Simulation time 68972964299 ps
CPU time 20.32 seconds
Started Jul 22 04:52:20 PM PDT 24
Finished Jul 22 04:52:41 PM PDT 24
Peak memory 201188 kb
Host smart-85a1dab0-f13d-4de9-99b1-07eecb73513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736129426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.1736129426
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2524206167
Short name T361
Test name
Test status
Simulation time 94703967091 ps
CPU time 115.7 seconds
Started Jul 22 04:52:20 PM PDT 24
Finished Jul 22 04:54:16 PM PDT 24
Peak memory 201316 kb
Host smart-0b5bcee6-22a9-4e89-afdf-9528e86d47a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524206167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.2524206167
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3364837340
Short name T351
Test name
Test status
Simulation time 69864718629 ps
CPU time 147.11 seconds
Started Jul 22 04:53:53 PM PDT 24
Finished Jul 22 04:56:20 PM PDT 24
Peak memory 201256 kb
Host smart-3c7ac35a-49b0-4928-b50d-a46298871759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364837340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3364837340
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.752955564
Short name T700
Test name
Test status
Simulation time 2015809468 ps
CPU time 5.32 seconds
Started Jul 22 04:48:48 PM PDT 24
Finished Jul 22 04:48:54 PM PDT 24
Peak memory 201016 kb
Host smart-e1d745ff-ca77-4fcb-84ce-fa7b4023e4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752955564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test
.752955564
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.518745488
Short name T595
Test name
Test status
Simulation time 3441722211 ps
CPU time 9.41 seconds
Started Jul 22 04:48:37 PM PDT 24
Finished Jul 22 04:48:47 PM PDT 24
Peak memory 201088 kb
Host smart-17c9073d-b59e-4b17-858c-6aefba806135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518745488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.518745488
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.2128983149
Short name T86
Test name
Test status
Simulation time 106961872148 ps
CPU time 165.8 seconds
Started Jul 22 04:48:41 PM PDT 24
Finished Jul 22 04:51:28 PM PDT 24
Peak memory 201212 kb
Host smart-68d7d8e3-3d2b-41e1-9977-3ee10906e672
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128983149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.2128983149
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3759122993
Short name T611
Test name
Test status
Simulation time 3417225641 ps
CPU time 2.16 seconds
Started Jul 22 04:48:39 PM PDT 24
Finished Jul 22 04:48:43 PM PDT 24
Peak memory 200896 kb
Host smart-81b2f2c4-1201-4760-95d0-e31b5f42407b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759122993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3759122993
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.1948909913
Short name T555
Test name
Test status
Simulation time 1311090048741 ps
CPU time 13.21 seconds
Started Jul 22 04:49:03 PM PDT 24
Finished Jul 22 04:49:17 PM PDT 24
Peak memory 200992 kb
Host smart-ca68ed98-e703-429e-a31b-2aa0199462a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948909913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.1948909913
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.346658060
Short name T540
Test name
Test status
Simulation time 2610829140 ps
CPU time 6.92 seconds
Started Jul 22 04:48:37 PM PDT 24
Finished Jul 22 04:48:45 PM PDT 24
Peak memory 200928 kb
Host smart-bc4c56b8-ef08-456d-aec8-bbfe69779d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346658060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.346658060
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1387313469
Short name T741
Test name
Test status
Simulation time 2465790537 ps
CPU time 6.64 seconds
Started Jul 22 04:48:40 PM PDT 24
Finished Jul 22 04:48:47 PM PDT 24
Peak memory 200872 kb
Host smart-b32f6bc1-9bf3-4e78-b0c1-248fb21c50ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387313469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1387313469
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1915279874
Short name T718
Test name
Test status
Simulation time 2030414626 ps
CPU time 3.1 seconds
Started Jul 22 04:49:08 PM PDT 24
Finished Jul 22 04:49:12 PM PDT 24
Peak memory 200776 kb
Host smart-10d08b50-a8ea-4ad2-8925-5b32c14ad554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915279874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1915279874
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3725086133
Short name T570
Test name
Test status
Simulation time 2538756457 ps
CPU time 2.15 seconds
Started Jul 22 04:48:38 PM PDT 24
Finished Jul 22 04:48:41 PM PDT 24
Peak memory 200900 kb
Host smart-5c0739f9-0bfe-44e2-91f4-7f79204df799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725086133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3725086133
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.2921547236
Short name T436
Test name
Test status
Simulation time 2110151336 ps
CPU time 5.79 seconds
Started Jul 22 04:48:37 PM PDT 24
Finished Jul 22 04:48:43 PM PDT 24
Peak memory 200860 kb
Host smart-5decdf0f-aa1f-4c76-bf94-b45aa7f1bb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921547236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.2921547236
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1438403578
Short name T54
Test name
Test status
Simulation time 15567151512 ps
CPU time 10.07 seconds
Started Jul 22 04:50:10 PM PDT 24
Finished Jul 22 04:50:20 PM PDT 24
Peak memory 201004 kb
Host smart-a4ee6ee6-a89c-483c-a340-9020f4859935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438403578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1438403578
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2954043071
Short name T253
Test name
Test status
Simulation time 42984331676 ps
CPU time 59.58 seconds
Started Jul 22 04:52:21 PM PDT 24
Finished Jul 22 04:53:21 PM PDT 24
Peak memory 201204 kb
Host smart-6908b900-8569-4c48-9de1-2863b8a4fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954043071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.2954043071
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.4014857467
Short name T50
Test name
Test status
Simulation time 25601742181 ps
CPU time 18.2 seconds
Started Jul 22 04:53:09 PM PDT 24
Finished Jul 22 04:53:28 PM PDT 24
Peak memory 201340 kb
Host smart-0b1f3b79-ca16-45e0-8b4c-a3da355ea885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014857467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.4014857467
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4052496442
Short name T358
Test name
Test status
Simulation time 125732973595 ps
CPU time 326.14 seconds
Started Jul 22 04:52:22 PM PDT 24
Finished Jul 22 04:57:49 PM PDT 24
Peak memory 201308 kb
Host smart-248eb0cd-d97a-405b-baa6-59e805cd4ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052496442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.4052496442
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1710371535
Short name T515
Test name
Test status
Simulation time 51419893516 ps
CPU time 61.48 seconds
Started Jul 22 04:54:59 PM PDT 24
Finished Jul 22 04:56:01 PM PDT 24
Peak memory 201300 kb
Host smart-486fbfcf-6317-4c8d-9c9b-fef3fb8f0bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710371535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.1710371535
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3281809048
Short name T246
Test name
Test status
Simulation time 63081618698 ps
CPU time 149.83 seconds
Started Jul 22 04:52:21 PM PDT 24
Finished Jul 22 04:54:52 PM PDT 24
Peak memory 201312 kb
Host smart-22a3cab7-5a1e-4d20-9d69-21790b4d3b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281809048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3281809048
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1245559588
Short name T13
Test name
Test status
Simulation time 34370023251 ps
CPU time 70.23 seconds
Started Jul 22 04:53:53 PM PDT 24
Finished Jul 22 04:55:03 PM PDT 24
Peak memory 201220 kb
Host smart-3db7c2e9-6bbe-4e67-8881-f9bec0bb5745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245559588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.1245559588
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3811381726
Short name T686
Test name
Test status
Simulation time 23482337796 ps
CPU time 4.01 seconds
Started Jul 22 04:52:20 PM PDT 24
Finished Jul 22 04:52:25 PM PDT 24
Peak memory 201208 kb
Host smart-6c1ac93b-4961-44ed-85d6-ade8bf5c2f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811381726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.3811381726
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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