Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.56	97.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	97.56	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.56	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	2	60	96.77

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	2	29	93.55	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2023

1

T1

4

T2

50

T6

6

auto[1]

628

1

T1

1

T2

18

T6

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2115

1

T1

3

T2

68

T6

8

auto[1]

536

1

T1

2

T28

15

T29

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2047

1

T1

2

T2

59

T6

8

auto[1]

604

1

T1

3

T2

9

T29

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2018

1

T1

3

T2

54

T6

6

auto[1]

633

1

T1

2

T2

14

T6

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2369

1

T1

5

T2

40

T6

8

auto[1]

282

1

T2

28

T30

2

T31

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2406

1

T1

5

T2

22

T6

6

auto[1]

245

1

T2

46

T6

2

T28

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2435

1

T1

5

T2

68

T6

8

auto[1]

216

1

T28

27

T29

2

T30

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2373

1

T1

5

T2

50

T6

8

auto[1]

278

1

T2

18

T28

5

T29

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2485

1

T1

5

T2

68

T6

8

auto[1]

166

1

T28

2

T29

1

T30

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1960

1

T1

2

T2

45

T6

6

auto[1]

691

1

T1

3

T2

23

T6

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	2	29	93.55	2
Automatically Generated Cross Bins	31	2	29	93.55	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	959	1			T1	5		T42	17		T203	14
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	83	1			T27	12		T314	1		T238	9
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	43	1			T270	1		T200	4		T332	9
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	19	1			T31	2		T333	14		T171	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	55	1			T313	2		T238	13		T205	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	42	1			T67	1		T334	1		T335	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	20	1			T29	1		T30	5		T270	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	8	1			T69	3		T321	2		T332	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	68	1			T28	20		T29	2		T30	6
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	14	1			T317	10		T171	1		T336	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	16	1			T337	5		T338	6		T339	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T222	1		T334	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	40	1			T28	5		T31	2		T238	10
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T70	2		T310	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T338	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	28	1			T6	2		T29	3		T321	5
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	53	1			T2	26		T30	2		T27	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	20	1			T202	3		T232	3		T332	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T340	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	47	1			T2	14		T222	1		T232	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	11	1			T334	1		T341	8		T328	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	11	1			T202	1		T333	10		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T201	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	27	1			T31	2		T342	1		T311	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	3	1			T329	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	10	1			T28	2		T232	2		T333	4
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T338	1		T327	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	14	1			T238	8		T343	1		T344	5
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T205	3		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

135

1

T2

7

T206

7

T270

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

158

1

T2

13

T27

6

T321

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

87

1

T238

18

T205

10

T343

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

148

1

T2

13

T30

2

T308

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

66

1

T28

2

T30

6

T206

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

90

1

T28

10

T187

1

T225

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T6

2

T31

2

T270

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

164

1

T202

1

T273

12

T69

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

62

1

T203

5

T223

8

T312

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T1

2

T314

1

T224

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T2

7

T29

3

T72

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T42

4

T202

3

T223

16

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T1

1

T203

3

T108

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

36

1

T27

3

T77

3

T236

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T42

2

T308

1

T273

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

141

1

T28

10

T65

14

T273

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

36

1

T28

5

T29

1

T200

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T1

1

T35

2

T202

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T29

2

T31

2

T270

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T1

1

T332

9

T345

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T42

2

T206

3

T346

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

14

1

T203

2

T79

1

T346

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T347

1

T88

2

T178

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T42

9

T203

4

T27

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T30

5

T75

2

T72

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

17

1

T37

1

T313

2

T222

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T75

1

T236

2

T86

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T31

2

T108

1

T180

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T72

1

T348

1

T349

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T35

1

T225

1

T321

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T72

2

T84

2

T148

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded